Print this page
patch fix-lint
3317 dis(1) should support cross-target disassembly
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/lib/libdisasm/sparc/dis_sparc_fmt.c
+++ new/usr/src/lib/libdisasm/common/dis_sparc_fmt.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
↓ open down ↓ |
19 lines elided |
↑ open up ↑ |
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 28 * Copyright 2009 Jason King. All rights reserved.
29 29 * Use is subject to license terms.
30 + * Copyright 2012 Joshua M. Clulow <josh@sysmgr.org>
30 31 */
31 32
32 33
33 34 #include <sys/byteorder.h>
34 35 #include <stdarg.h>
35 36
36 37 #if !defined(DIS_STANDALONE)
37 38 #include <stdio.h>
38 39 #endif /* DIS_STANDALONE */
39 40
40 41 #include "libdisasm.h"
↓ open down ↓ |
1 lines elided |
↑ open up ↑ |
41 42 #include "libdisasm_impl.h"
42 43 #include "dis_sparc.h"
43 44 #include "dis_sparc_fmt.h"
44 45
45 46 extern char *strncpy(char *, const char *, size_t);
46 47 extern size_t strlen(const char *);
47 48 extern int strcmp(const char *, const char *);
48 49 extern int strncmp(const char *, const char *, size_t);
49 50 extern size_t strlcat(char *, const char *, size_t);
50 51 extern size_t strlcpy(char *, const char *, size_t);
51 -extern int snprintf(char *, size_t, const char *, ...);
52 -extern int vsnprintf(char *, size_t, const char *, va_list);
53 52
54 53 /*
55 54 * This file has the functions that do all the dirty work of outputting the
56 55 * disassembled instruction
57 56 *
58 57 * All the non-static functions follow the format_fcn (in dis_sparc.h):
59 58 * Input:
60 59 * disassembler handle/context
61 60 * instruction to disassemble
62 61 * instruction definition pointer (inst_t *)
63 62 * index in the table of the instruction
64 63 * Return:
65 64 * 0 Success
66 65 * !0 Invalid instruction
67 66 *
68 67 * Generally, instructions found in the same table use the same output format
69 68 * or have a few minor differences (which are described in the 'flags' field
70 69 * of the instruction definition. In some cases, certain instructions differ
71 70 * radically enough from those in the same table, that their own format
72 71 * function is used.
73 72 *
74 73 * Typically each table has a unique format function defined in this file. In
75 74 * some cases (such as branches) a common one for all the tables is used.
76 75 *
77 76 * When adding support for new instructions, it is largely a judgement call
78 77 * as to when a new format function is defined.
79 78 */
80 79
81 80 /* The various instruction formats of a sparc instruction */
82 81
83 82 #if defined(_BIT_FIELDS_HTOL)
84 83 typedef struct format1 {
85 84 uint32_t op:2;
86 85 uint32_t disp30:30;
87 86 } format1_t;
88 87 #elif defined(_BIT_FIELDS_LTOH)
89 88 typedef struct format1 {
90 89 uint32_t disp30:30;
91 90 uint32_t op:2;
92 91 } format1_t;
93 92 #else
94 93 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
95 94 #endif
96 95
97 96 #if defined(_BIT_FIELDS_HTOL)
98 97 typedef struct format2 {
99 98 uint32_t op:2;
100 99 uint32_t rd:5;
101 100 uint32_t op2:3;
102 101 uint32_t imm22:22;
103 102 } format2_t;
104 103 #elif defined(_BIT_FIELDS_LTOH)
105 104 typedef struct format2 {
106 105 uint32_t imm22:22;
107 106 uint32_t op2:3;
108 107 uint32_t rd:5;
109 108 uint32_t op:2;
110 109 } format2_t;
111 110 #else
112 111 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
113 112 #endif
114 113
115 114 #if defined(_BIT_FIELDS_HTOL)
116 115 typedef struct format2a {
117 116 uint32_t op:2;
118 117 uint32_t a:1;
119 118 uint32_t cond:4;
120 119 uint32_t op2:3;
121 120 uint32_t disp22:22;
122 121 } format2a_t;
123 122 #elif defined(_BIT_FIELDS_LTOH)
124 123 typedef struct format2a {
125 124 uint32_t disp22:22;
126 125 uint32_t op2:3;
127 126 uint32_t cond:4;
128 127 uint32_t a:1;
129 128 uint32_t op:2;
130 129 } format2a_t;
131 130 #else
132 131 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
133 132 #endif
134 133
135 134 #if defined(_BIT_FIELDS_HTOL)
136 135 typedef struct format2b {
137 136 uint32_t op:2;
138 137 uint32_t a:1;
139 138 uint32_t cond:4;
140 139 uint32_t op2:3;
141 140 uint32_t cc:2;
142 141 uint32_t p:1;
143 142 uint32_t disp19:19;
144 143 } format2b_t;
145 144 #elif defined(_BIT_FIELDS_LTOH)
146 145 typedef struct format2b {
147 146 uint32_t disp19:19;
148 147 uint32_t p:1;
149 148 uint32_t cc:2;
150 149 uint32_t op2:3;
151 150 uint32_t cond:4;
152 151 uint32_t a:1;
153 152 uint32_t op:2;
154 153 } format2b_t;
155 154 #else
156 155 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
157 156 #endif
158 157
159 158 #if defined(_BIT_FIELDS_HTOL)
160 159 typedef struct format2c {
161 160 uint32_t op:2;
162 161 uint32_t a:1;
163 162 uint32_t cond:4;
164 163 uint32_t op2:3;
165 164 uint32_t d16hi:2;
166 165 uint32_t p:1;
167 166 uint32_t rs1:5;
168 167 uint32_t d16lo:14;
169 168 } format2c_t;
170 169 #elif defined(_BIT_FIELDS_LTOH)
171 170 typedef struct format2c {
172 171 uint32_t d16lo:14;
173 172 uint32_t rs1:5;
174 173 uint32_t p:1;
175 174 uint32_t d16hi:2;
176 175 uint32_t op2:3;
177 176 uint32_t cond:4;
178 177 uint32_t a:1;
179 178 uint32_t op:2;
180 179 } format2c_t;
181 180 #else
182 181 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
183 182 #endif
184 183
185 184 #if defined(_BIT_FIELDS_HTOL)
186 185 typedef struct format3 {
187 186 uint32_t op:2;
188 187 uint32_t rd:5;
189 188 uint32_t op3:6;
190 189 uint32_t rs1:5;
191 190 uint32_t i:1;
192 191 uint32_t asi:8;
193 192 uint32_t rs2:5;
194 193 } format3_t;
195 194 #elif defined(_BIT_FIELDS_LTOH)
196 195 typedef struct format3 {
197 196 uint32_t rs2:5;
198 197 uint32_t asi:8;
199 198 uint32_t i:1;
200 199 uint32_t rs1:5;
201 200 uint32_t op3:6;
202 201 uint32_t rd:5;
203 202 uint32_t op:2;
204 203 } format3_t;
205 204 #else
206 205 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
207 206 #endif
208 207
209 208 #if defined(_BIT_FIELDS_HTOL)
210 209 typedef struct format3a {
211 210 uint32_t op:2;
212 211 uint32_t rd:5;
213 212 uint32_t op3:6;
214 213 uint32_t rs1:5;
215 214 uint32_t i:1;
216 215 uint32_t simm13:13;
217 216 } format3a_t;
218 217 #elif defined(_BIT_FIELDS_LTOH)
219 218 typedef struct format3a {
220 219 uint32_t simm13:13;
221 220 uint32_t i:1;
222 221 uint32_t rs1:5;
223 222 uint32_t op3:6;
224 223 uint32_t rd:5;
225 224 uint32_t op:2;
226 225 } format3a_t;
227 226 #else
228 227 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
229 228 #endif
230 229
231 230 #if defined(_BIT_FIELDS_HTOL)
232 231 typedef struct format3b {
233 232 uint32_t op:2;
234 233 uint32_t rd:5;
235 234 uint32_t op3:6;
236 235 uint32_t rs1:5;
237 236 uint32_t i:1;
238 237 uint32_t x:1;
239 238 uint32_t undef:6;
240 239 uint32_t shcnt:6;
241 240 } format3b_t;
242 241 #elif defined(_BIT_FIELDS_LTOH)
243 242 typedef struct format3b {
244 243 uint32_t shcnt:6;
245 244 uint32_t undef:6;
246 245 uint32_t x:1;
247 246 uint32_t i:1;
248 247 uint32_t rs1:5;
249 248 uint32_t op3:6;
250 249 uint32_t rd:5;
251 250 uint32_t op:2;
252 251 } format3b_t;
253 252 #else
254 253 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
255 254 #endif
256 255
257 256 #if defined(_BIT_FIELDS_HTOL)
258 257 typedef struct format3c {
259 258 uint32_t op:2;
260 259 uint32_t rd:5;
261 260 uint32_t op3:6;
262 261 uint32_t cc2:1;
263 262 uint32_t cond:4;
264 263 uint32_t i:1;
265 264 uint32_t cc:2;
266 265 uint32_t simm11:11;
267 266 } format3c_t;
268 267 #elif defined(_BIT_FIELDS_LTOH)
269 268 typedef struct format3c {
270 269 uint32_t simm11:11;
271 270 uint32_t cc:2;
272 271 uint32_t i:1;
273 272 uint32_t cond:4;
274 273 uint32_t cc2:1;
275 274 uint32_t op3:6;
276 275 uint32_t rd:5;
277 276 uint32_t op:2;
278 277 } format3c_t;
279 278 #else
280 279 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
281 280 #endif
282 281
283 282 #if defined(_BIT_FIELDS_HTOL)
284 283 typedef struct format3d {
285 284 uint32_t op:2;
286 285 uint32_t rd:5;
287 286 uint32_t op3:6;
288 287 uint32_t rs1:5;
289 288 uint32_t i:1;
290 289 uint32_t rcond:3;
291 290 uint32_t simm10:10;
292 291 } format3d_t;
293 292 #elif defined(_BIT_FIELDS_LTOH)
294 293 typedef struct format3d {
295 294 uint32_t simm10:10;
296 295 uint32_t rcond:3;
297 296 uint32_t i:1;
298 297 uint32_t rs1:5;
299 298 uint32_t op3:6;
300 299 uint32_t rd:5;
301 300 uint32_t op:2;
302 301 } format3d_t;
303 302 #else
304 303 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
305 304 #endif
306 305
307 306 #if defined(_BIT_FIELDS_HTOL)
308 307 typedef struct formatcp {
309 308 uint32_t op:2;
310 309 uint32_t rd:5;
311 310 uint32_t op3:6;
312 311 uint32_t rs1:5;
313 312 uint32_t opc:9;
314 313 uint32_t rs2:5;
315 314 } formatcp_t;
316 315 #elif defined(_BIT_FIELDS_LTOH)
317 316 typedef struct formatcp {
318 317 uint32_t rs2:5;
319 318 uint32_t opc:9;
320 319 uint32_t rs1:5;
321 320 uint32_t op3:6;
322 321 uint32_t rd:5;
323 322 uint32_t op:2;
324 323 } formatcp_t;
325 324 #else
326 325 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
327 326 #endif
328 327
329 328 #if defined(_BIT_FIELDS_HTOL)
330 329 typedef struct formattcc {
331 330 uint32_t op:2;
332 331 uint32_t undef:1;
333 332 uint32_t cond:4;
334 333 uint32_t op3:6;
335 334 uint32_t rs1:5;
336 335 uint32_t i:1;
337 336 uint32_t cc:2;
338 337 uint32_t undef2:3;
339 338 uint32_t immtrap:8;
340 339 } formattcc_t;
341 340 #elif defined(_BIT_FIELDS_LTOH)
342 341 typedef struct formattcc {
343 342 uint32_t immtrap:8;
344 343 uint32_t undef2:3;
345 344 uint32_t cc:2;
346 345 uint32_t i:1;
347 346 uint32_t rs1:5;
348 347 uint32_t op3:6;
349 348 uint32_t cond:4;
350 349 uint32_t undef:1;
351 350 uint32_t op:2;
352 351 } formattcc_t;
353 352 #else
354 353 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
355 354 #endif
356 355
357 356 #if defined(_BIT_FIELDS_HTOL)
358 357 typedef struct formattcc2 {
359 358 uint32_t op:2;
360 359 uint32_t undef:1;
361 360 uint32_t cond:4;
362 361 uint32_t op3:6;
363 362 uint32_t rs1:5;
364 363 uint32_t i:1;
365 364 uint32_t cc:2;
366 365 uint32_t undef2:6;
367 366 uint32_t rs2:5;
368 367 } formattcc2_t;
369 368 #elif defined(_BIT_FIELDS_LTOH)
370 369 typedef struct formattcc2 {
371 370 uint32_t rs2:5;
372 371 uint32_t undef2:6;
373 372 uint32_t cc:2;
374 373 uint32_t i:1;
375 374 uint32_t rs1:5;
376 375 uint32_t op3:6;
377 376 uint32_t cond:4;
378 377 uint32_t undef:1;
379 378 uint32_t op:2;
380 379 } formattcc2_t;
381 380 #else
382 381 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
383 382 #endif
384 383
385 384 #if defined(_BIT_FIELDS_HTOL)
386 385 typedef struct formatmbr {
387 386 uint32_t op:2;
388 387 uint32_t rd:5;
389 388 uint32_t op3:6;
390 389 uint32_t rs1:5;
391 390 uint32_t i:1;
392 391 uint32_t undef:6;
393 392 uint32_t cmask:3;
394 393 uint32_t mmask:4;
395 394 } formatmbr_t;
396 395 #elif defined(_BIT_FIELDS_LTOH)
397 396 typedef struct formatmbr {
398 397 uint32_t mmask:4;
399 398 uint32_t cmask:3;
400 399 uint32_t undef:6;
401 400 uint32_t i:1;
402 401 uint32_t rs1:5;
403 402 uint32_t op3:6;
404 403 uint32_t rd:5;
405 404 uint32_t op:2;
406 405 } formatmbr_t;
407 406 #else
408 407 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
409 408 #endif
410 409
411 410 #if defined(_BIT_FIELDS_HTOL)
412 411 typedef struct formatfcmp {
413 412 uint32_t op:2;
414 413 uint32_t undef:3;
415 414 uint32_t cc:2;
416 415 uint32_t op3:6;
417 416 uint32_t rs1:5;
418 417 uint32_t opf:9;
419 418 uint32_t rs2:5;
420 419 } formatfcmp_t;
421 420 #elif defined(_BIT_FIELDS_LTOH)
422 421 typedef struct formatfcmp {
423 422 uint32_t rs2:5;
424 423 uint32_t opf:9;
425 424 uint32_t rs1:5;
426 425 uint32_t op3:6;
427 426 uint32_t cc:2;
428 427 uint32_t undef:3;
429 428 uint32_t op:2;
430 429 } formatfcmp_t;
431 430 #else
432 431 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
433 432 #endif
434 433
435 434 #if defined(_BIT_FIELDS_HTOL)
436 435 typedef struct formatfmov {
437 436 uint32_t op:2;
438 437 uint32_t rd:5;
439 438 uint32_t op3:6;
440 439 uint32_t undef:1;
441 440 uint32_t cond:4;
442 441 uint32_t cc:3;
443 442 uint32_t opf:6;
444 443 uint32_t rs2:5;
445 444 } formatfmov_t;
446 445 #elif defined(_BIT_FIELDS_LTOH)
447 446 typedef struct formatfmov {
448 447 uint32_t rs2:5;
449 448 uint32_t opf:6;
450 449 uint32_t cc:3;
451 450 uint32_t cond:4;
452 451 uint32_t undef:1;
453 452 uint32_t op3:6;
454 453 uint32_t rd:5;
455 454 uint32_t op:2;
456 455 } formatfmov_t;
457 456 #else
458 457 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
459 458 #endif
460 459
461 460 #if defined(_BIT_FIELDS_HTOL)
462 461 typedef struct formatfused {
463 462 uint32_t op:2;
464 463 uint32_t rd:5;
465 464 uint32_t op3:6;
466 465 uint32_t rs1:5;
467 466 uint32_t rs3:5;
468 467 uint32_t op5:4;
469 468 uint32_t rs2:5;
470 469 } formatfused_t;
471 470 #elif defined(_BIT_FIELDS_LTOH)
472 471 typedef struct formatfused {
473 472 uint32_t rs2:5;
474 473 uint32_t op5:4;
475 474 uint32_t rs3:5;
476 475 uint32_t rs1:5;
477 476 uint32_t op3:6;
478 477 uint32_t rd:5;
479 478 uint32_t op:2;
480 479 } formatfused_t;
481 480 #else
482 481 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
483 482 #endif
484 483
485 484 typedef union ifmt {
486 485 uint32_t i;
487 486 format1_t f1;
488 487 format2_t f2;
489 488 format2a_t f2a;
490 489 format2b_t f2b;
491 490 format2c_t f2c;
492 491 format3_t f3;
493 492 format3a_t f3a;
494 493 format3b_t f3b;
495 494 format3c_t f3c;
496 495 format3d_t f3d;
497 496 formatcp_t fcp;
498 497 formattcc_t ftcc;
499 498 formattcc2_t ftcc2;
500 499 formatfcmp_t fcmp;
501 500 formatmbr_t fmb;
502 501 formatfmov_t fmv;
503 502 formatfused_t fused;
504 503 } ifmt_t;
505 504
506 505 /* integer register names */
507 506 static const char *reg_names[32] = {
508 507 "%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",
509 508 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7",
510 509 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7",
511 510 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7"
512 511 };
513 512
514 513 /* floating point register names */
515 514 static const char *freg_names[32] = {
516 515 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
517 516 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
518 517 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
519 518 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"
520 519 };
521 520
522 521 /* double precision register names */
523 522 static const char *fdreg_names[32] = {
524 523 "%d0", "%d32", "%d2", "%d34", "%d4", "%d36", "%d6", "%d38",
525 524 "%d8", "%d40", "%d10", "%d42", "%d12", "%d44", "%d14", "%d46",
526 525 "%d16", "%d48", "%d18", "%d50", "%d20", "%d52", "%d22", "%d54",
527 526 "%d24", "%d56", "%d26", "%d58", "%d28", "%d60", "%d30", "%d62"
528 527 };
529 528
530 529 static const char *compat_fdreg_names[32] = {
531 530 "%f0", "%f32", "%f2", "%f34", "%f4", "%f36", "%f6", "%f38",
532 531 "%f8", "%f40", "%f10", "%f42", "%f12", "%f44", "%f14", "%f46",
533 532 "%f16", "%f48", "%f18", "%f50", "%f20", "%f52", "%f22", "%f54",
534 533 "%f24", "%f56", "%f26", "%f58", "%f28", "%f60", "%f30", "%f62"
535 534 };
536 535
537 536
538 537 static const char *fqreg_names[32] = {
539 538 "%q0", "%q32", "%f2", "%f3", "%f4", "%q4", "%q36", "%f6",
540 539 "%f7", "%q8", "%q40", "%f10", "%f11", "%q12", "%q44", "%f14",
541 540 "%f15", "%q16", "%q48", "%f18", "%f19", "%q20", "%q52", "%f22",
542 541 "%f23", "%q24", "%q56", "%f26", "%f27", "%q28", "%q60", "%f30",
543 542 };
544 543
545 544
546 545 /* coprocessor register names -- sparcv8 only */
547 546 static const char *cpreg_names[32] = {
548 547 "%c0", "%c1", "%c2", "%c3", "%c4", "%c5", "%c6", "%c7",
549 548 "%c8", "%c9", "%c10", "%c11", "%c12", "%c13", "%c14", "%c15",
550 549 "%c16", "%c17", "%c18", "%c19", "%c20", "%c21", "%c22", "%c23",
551 550 "%c24", "%c25", "%c26", "%c27", "%c28", "%c29", "%c30", "%c31",
552 551 };
553 552
554 553 /* floating point condition code names */
555 554 static const char *fcc_names[4] = {
556 555 "%fcc0", "%fcc1", "%fcc2", "%fcc3"
557 556 };
558 557
559 558 /* condition code names */
560 559 static const char *icc_names[4] = {
561 560 "%icc", NULL, "%xcc", NULL
562 561 };
563 562
564 563 /* bitmask values for membar */
565 564 static const char *membar_mmask[4] = {
566 565 "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore"
567 566 };
568 567
569 568 static const char *membar_cmask[3] = {
570 569 "#Lookaside", "#MemIssue", "#Sync"
571 570 };
572 571
573 572 /* v8 ancillary state register names */
574 573 static const char *asr_names[32] = {
575 574 "%y", "%asr1", "%asr2", "%asr3",
576 575 "%asr4", "%asr5", "%asr6", "%asr7",
577 576 "%asr8", "%asr9", "%asr10", "%asr11",
578 577 "%asr12", "%asr13", "%asr14", "%asr15",
579 578 NULL, NULL, NULL, NULL,
580 579 NULL, NULL, NULL, NULL,
581 580 NULL, NULL, NULL, NULL,
582 581 NULL, NULL, NULL, NULL
583 582 };
584 583 static const uint32_t asr_rdmask = 0x0000ffffL;
585 584 static const uint32_t asr_wrmask = 0x0000ffffL;
586 585
587 586 static const char *v9_asr_names[32] = {
588 587 "%y", NULL, "%ccr", "%asi",
589 588 "%tick", "%pc", "%fprs", NULL,
590 589 NULL, NULL, NULL, NULL,
591 590 NULL, NULL, NULL, NULL,
592 591 "%pcr", "%pic", "%dcr", "%gsr",
593 592 "%softint_set", "%softint_clr", "%softint", "%tick_cmpr",
594 593 "%stick", "%stick_cmpr", NULL, NULL,
595 594 NULL, NULL, NULL, NULL
596 595 };
597 596 /*
598 597 * on v9, only certain registers are valid for read or writing
599 598 * these are bitmasks corresponding to which registers are valid in which
600 599 * case. Any access to %dcr is illegal.
601 600 */
602 601 static const uint32_t v9_asr_rdmask = 0x03cb007d;
603 602 static const uint32_t v9_asr_wrmask = 0x03fb004d;
604 603
605 604 /* privledged register names on v9 */
606 605 /* TODO: compat - NULL to %priv_nn */
607 606 static const char *v9_privreg_names[32] = {
608 607 "%tpc", "%tnpc", "%tstate", "%tt",
609 608 "%tick", "%tba", "%pstate", "%tl",
610 609 "%pil", "%cwp", "%cansave", "%canrestore",
611 610 "%cleanwin", "%otherwin", "%wstate", "%fq",
612 611 "%gl", NULL, NULL, NULL,
613 612 NULL, NULL, NULL, NULL,
614 613 NULL, NULL, NULL, NULL,
615 614 NULL, NULL, NULL, "%ver"
616 615 };
617 616
618 617 /* hyper privileged register names on v9 */
619 618 static const char *v9_hprivreg_names[32] = {
620 619 "%hpstate", "%htstate", NULL, "%hintp",
621 620 NULL, "%htba", "%hver", NULL,
622 621 NULL, NULL, NULL, NULL,
623 622 NULL, NULL, NULL, NULL,
624 623 NULL, NULL, NULL, NULL,
625 624 NULL, NULL, NULL, NULL,
626 625 NULL, NULL, NULL, NULL,
627 626 NULL, NULL, NULL, "%hstick_cmpr"
628 627 };
629 628
630 629 static const uint32_t v9_pr_rdmask = 0x80017fff;
631 630 static const uint32_t v9_pr_wrmask = 0x00017fff;
632 631 static const uint32_t v9_hpr_rdmask = 0x8000006b;
633 632 static const uint32_t v9_hpr_wrmask = 0x8000006b;
634 633
635 634 static const char *prefetch_str[32] = {
636 635 "#n_reads", "#one_read",
637 636 "#n_writes", "#one_write",
638 637 "#page", NULL, NULL, NULL,
639 638 NULL, NULL, NULL, NULL,
640 639 NULL, NULL, NULL, NULL,
641 640 NULL, "#unified", NULL, NULL,
642 641 "#n_reads_strong", "#one_read_strong",
643 642 "#n_writes_strong", "#one_write_strong",
644 643 NULL, NULL, NULL, NULL,
645 644 NULL, NULL, NULL, NULL
646 645 };
647 646
648 647 static void prt_field(const char *, uint32_t, int);
649 648
650 649 static const char *get_regname(dis_handle_t *, int, uint32_t);
651 650 static int32_t sign_extend(int32_t, int32_t);
652 651
653 652 static void prt_name(dis_handle_t *, const char *, int);
654 653
655 654 #define IMM_SIGNED 0x01 /* Is immediate value signed */
656 655 #define IMM_ADDR 0x02 /* Is immediate value part of an address */
657 656 static void prt_imm(dis_handle_t *, uint32_t, int);
658 657
659 658 static void prt_asi(dis_handle_t *, uint32_t);
660 659 static const char *get_asi_name(uint8_t);
661 660 static void prt_address(dis_handle_t *, uint32_t, int);
662 661 static void prt_aluargs(dis_handle_t *, uint32_t, uint32_t);
663 662 static void bprintf(dis_handle_t *, const char *, ...);
664 663
665 664 /*
666 665 * print out val (which is 'bitlen' bits long) in binary
667 666 */
668 667 #if defined(DIS_STANDALONE)
669 668 /* ARGSUSED */
670 669 void
671 670 prt_binary(uint32_t val, int bitlen)
672 671 {
673 672
674 673 }
675 674
676 675 #else
677 676
678 677 void
679 678 prt_binary(uint32_t val, int bitlen)
680 679 {
681 680 int i;
682 681
683 682 for (i = bitlen - 1; i >= 0; --i) {
684 683 (void) fprintf(stderr, ((val & (1L << i)) != 0) ? "1" : "0");
685 684
686 685 if (i % 4 == 0 && i != 0)
687 686 (void) fprintf(stderr, " ");
688 687 }
689 688 }
690 689 #endif /* DIS_STANDALONE */
↓ open down ↓ |
628 lines elided |
↑ open up ↑ |
691 690
692 691
693 692 /*
694 693 * print out a call instruction
695 694 * format: call address <name>
696 695 */
697 696 /* ARGSUSED1 */
698 697 int
699 698 fmt_call(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
700 699 {
700 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
701 701 ifmt_t *f = (ifmt_t *)&instr;
702 702
703 703 int32_t disp;
704 704 size_t curlen;
705 705
706 706 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
707 707
708 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
708 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
709 709 prt_field("op", f->f1.op, 2);
710 710 prt_field("disp30", f->f1.disp30, 30);
711 711 }
712 712
713 713 disp = sign_extend(f->f1.disp30, 30) * 4;
714 714
715 715 prt_name(dhp, inp->in_data.in_def.in_name, 1);
716 716
717 717 bprintf(dhp, (octal != 0) ? "%s0%-11lo" : "%s0x%-10lx",
718 718 (disp < 0) ? "-" : "+",
719 719 (disp < 0) ? (-disp) : disp);
720 720
721 - (void) strlcat(dhp->dh_buf, " <", dhp->dh_buflen);
721 + (void) strlcat(dhx->dhx_buf, " <", dhx->dhx_buflen);
722 722
723 - curlen = strlen(dhp->dh_buf);
723 + curlen = strlen(dhx->dhx_buf);
724 724 dhp->dh_lookup(dhp->dh_data, dhp->dh_addr + (int64_t)disp,
725 - dhp->dh_buf + curlen, dhp->dh_buflen - curlen - 1, NULL,
725 + dhx->dhx_buf + curlen, dhx->dhx_buflen - curlen - 1, NULL,
726 726 NULL);
727 - (void) strlcat(dhp->dh_buf, ">", dhp->dh_buflen);
727 + (void) strlcat(dhx->dhx_buf, ">", dhx->dhx_buflen);
728 728
729 729
730 730 return (0);
731 731 }
732 732
733 733 int
734 734 fmt_sethi(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
735 735 {
736 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
736 737 ifmt_t *f = (ifmt_t *)&instr;
737 738
738 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
739 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
739 740 prt_field("op", f->f2.op, 2);
740 741 prt_field("op2", f->f2.op2, 3);
741 742 prt_field("rd", f->f2.rd, 5);
742 743 prt_field("imm22", f->f2.imm22, 22);
743 744 }
744 745
745 746 if (idx == 0) {
746 747 /* unimp / illtrap */
747 748 prt_name(dhp, inp->in_data.in_def.in_name, 1);
748 749 prt_imm(dhp, f->f2.imm22, 0);
749 750 return (0);
750 751 }
751 752
752 753 if (f->f2.imm22 == 0 && f->f2.rd == 0) {
753 754 prt_name(dhp, "nop", 0);
754 755 return (0);
755 756 }
756 757
757 758 /* ?? Should we return -1 if rd == 0 && disp != 0 */
758 759
759 760 prt_name(dhp, inp->in_data.in_def.in_name, 1);
760 761
761 762 bprintf(dhp,
762 763 ((dhp->dh_flags & DIS_OCTAL) != 0) ?
763 764 "%%hi(0%lo), %s" : "%%hi(0x%lx), %s",
↓ open down ↓ |
15 lines elided |
↑ open up ↑ |
764 765 f->f2.imm22 << 10,
765 766 reg_names[f->f2.rd]);
766 767
767 768 return (0);
768 769 }
769 770
770 771 /* ARGSUSED3 */
771 772 int
772 773 fmt_branch(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
773 774 {
775 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
774 776 const char *name = inp->in_data.in_def.in_name;
775 777 const char *r = NULL;
776 778 const char *annul = "";
777 779 const char *pred = "";
778 780
779 781 char buf[15];
780 782
781 783 ifmt_t *f = (ifmt_t *)&instr;
782 784
783 785 size_t curlen;
784 786 int32_t disp;
785 787 uint32_t flags = inp->in_data.in_def.in_flags;
786 788 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
787 789
788 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
790 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
789 791 prt_field("op", f->f2.op, 2);
790 792 prt_field("op2", f->f2.op2, 3);
791 793
792 794 switch (FLG_DISP_VAL(flags)) {
793 795 case DISP22:
794 796 prt_field("cond", f->f2a.cond, 4);
795 797 prt_field("a", f->f2a.a, 1);
796 798 prt_field("disp22", f->f2a.disp22, 22);
797 799 break;
798 800
799 801 case DISP19:
800 802 prt_field("cond", f->f2a.cond, 4);
801 803 prt_field("a", f->f2a.a, 1);
802 804 prt_field("p", f->f2b.p, 1);
803 805 prt_field("cc", f->f2b.cc, 2);
804 806 prt_field("disp19", f->f2b.disp19, 19);
805 807 break;
806 808
807 809 case DISP16:
808 810 prt_field("bit 28", ((instr & (1L << 28)) >> 28), 1);
↓ open down ↓ |
10 lines elided |
↑ open up ↑ |
809 811 prt_field("rcond", f->f2c.cond, 3);
810 812 prt_field("p", f->f2c.p, 1);
811 813 prt_field("rs1", f->f2c.rs1, 5);
812 814 prt_field("d16hi", f->f2c.d16hi, 2);
813 815 prt_field("d16lo", f->f2c.d16lo, 14);
814 816 break;
815 817 }
816 818 }
817 819
818 820 if (f->f2b.op2 == 0x01 && idx == 0x00 && f->f2b.p == 1 &&
819 - f->f2b.cc == 0x02 && ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) != 0)) {
821 + f->f2b.cc == 0x02 && ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) != 0)) {
820 822 name = "iprefetch";
821 823 flags = FLG_RS1(REG_NONE)|FLG_DISP(DISP19);
822 824 }
823 825
824 826
825 827 switch (FLG_DISP_VAL(flags)) {
826 828 case DISP22:
827 829 disp = sign_extend(f->f2a.disp22, 22);
828 830 break;
829 831
830 832 case DISP19:
831 833 disp = sign_extend(f->f2b.disp19, 19);
832 834 break;
833 835
834 836 case DISP16:
835 837 disp = sign_extend((f->f2c.d16hi << 14)|f->f2c.d16lo, 16);
836 838 break;
837 839
838 840 }
839 841
840 842 disp *= 4;
841 843
842 844 if ((FLG_RS1_VAL(flags) == REG_ICC) || (FLG_RS1_VAL(flags) == REG_FCC))
843 845 r = get_regname(dhp, FLG_RS1_VAL(flags), f->f2b.cc);
844 846 else
845 847 r = get_regname(dhp, FLG_RS1_VAL(flags), f->f2c.rs1);
846 848
↓ open down ↓ |
17 lines elided |
↑ open up ↑ |
847 849 if (r == NULL)
848 850 return (-1);
849 851
850 852 if (f->f2a.a == 1)
851 853 annul = ",a";
852 854
853 855 if ((flags & FLG_PRED) != 0) {
854 856 if (f->f2b.p == 0) {
855 857 pred = ",pn";
856 858 } else {
857 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0)
859 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0)
858 860 pred = ",pt";
859 861 }
860 862 }
861 863
862 - (void) snprintf(buf, sizeof (buf), "%s%s%s", name, annul, pred);
864 + (void) dis_snprintf(buf, sizeof (buf), "%s%s%s", name, annul, pred);
863 865 prt_name(dhp, buf, 1);
864 866
865 867
866 868 switch (FLG_DISP_VAL(flags)) {
867 869 case DISP22:
868 870 bprintf(dhp,
869 871 (octal != 0) ? "%s0%-11lo <" : "%s0x%-10lx <",
870 872 (disp < 0) ? "-" : "+",
871 873 (disp < 0) ? (-disp) : disp);
872 874 break;
873 875
874 876 case DISP19:
875 877 bprintf(dhp,
876 878 (octal != 0) ? "%s, %s0%-5lo <" :
877 879 "%s, %s0x%-04lx <", r,
878 880 (disp < 0) ? "-" : "+",
879 881 (disp < 0) ? (-disp) : disp);
880 882 break;
↓ open down ↓ |
8 lines elided |
↑ open up ↑ |
881 883
882 884 case DISP16:
883 885 bprintf(dhp,
884 886 (octal != 0) ? "%s, %s0%-6lo <" : "%s, %s0x%-5lx <",
885 887 r,
886 888 (disp < 0) ? "-" : "+",
887 889 (disp < 0) ? (-disp) : disp);
888 890 break;
889 891 }
890 892
891 - curlen = strlen(dhp->dh_buf);
893 + curlen = strlen(dhx->dhx_buf);
892 894 dhp->dh_lookup(dhp->dh_data, dhp->dh_addr + (int64_t)disp,
893 - dhp->dh_buf + curlen, dhp->dh_buflen - curlen - 1, NULL, NULL);
895 + dhx->dhx_buf + curlen, dhx->dhx_buflen - curlen - 1, NULL, NULL);
894 896
895 - (void) strlcat(dhp->dh_buf, ">", dhp->dh_buflen);
897 + (void) strlcat(dhx->dhx_buf, ">", dhx->dhx_buflen);
896 898
897 899 return (0);
898 900 }
899 901
900 902
901 903
902 904 /*
903 905 * print out the compare and swap instructions (casa/casxa)
904 906 * format: casa/casxa [%rs1] imm_asi, %rs2, %rd
905 907 * casa/casxa [%rs1] %asi, %rs2, %rd
906 908 *
907 909 * If DIS_DEBUG_SYN_ALL is set, synthetic instructions are emitted
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
908 910 * when an immediate ASI value is given as follows:
909 911 *
910 912 * casa [%rs1]#ASI_P, %rs2, %rd -> cas [%rs1], %rs2, %rd
911 913 * casa [%rs1]#ASI_P_L, %rs2, %rd -> casl [%rs1], %rs2, %rd
912 914 * casxa [%rs1]#ASI_P, %rs2, %rd -> casx [%rs1], %rs2, %rd
913 915 * casxa [%rs1]#ASI_P_L, %rs2, %rd -> casxl [%rs1], %rs2, %rd
914 916 */
915 917 static int
916 918 fmt_cas(dis_handle_t *dhp, uint32_t instr, const char *name)
917 919 {
920 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
918 921 ifmt_t *f = (ifmt_t *)&instr;
919 922 const char *asistr = NULL;
920 923 int noasi = 0;
921 924
922 925 asistr = get_asi_name(f->f3.asi);
923 926
924 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT)) != 0) {
927 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT)) != 0) {
925 928 if (f->f3.op3 == 0x3c && f->f3.i == 0) {
926 929 if (f->f3.asi == 0x80) {
927 930 noasi = 1;
928 931 name = "cas";
929 932 }
930 933
931 934 if (f->f3.asi == 0x88) {
932 935 noasi = 1;
933 936 name = "casl";
934 937 }
935 938 }
936 939
937 940 if (f->f3.op3 == 0x3e && f->f3.i == 0) {
938 941 if (f->f3.asi == 0x80) {
939 942 noasi = 1;
940 943 name = "casx";
941 944 }
942 945
943 946 if (f->f3.asi == 0x88) {
944 947 noasi = 1;
↓ open down ↓ |
10 lines elided |
↑ open up ↑ |
945 948 name = "casxl";
946 949 }
947 950 }
948 951 }
949 952
950 953 prt_name(dhp, name, 1);
951 954
952 955 bprintf(dhp, "[%s]", reg_names[f->f3.rs1]);
953 956
954 957 if (noasi == 0) {
955 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
958 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
956 959 prt_asi(dhp, instr);
957 960 }
958 961
959 962 bprintf(dhp, ", %s, %s", reg_names[f->f3.rs2], reg_names[f->f3.rd]);
960 963
961 964 if (noasi == 0 && asistr != NULL)
962 965 bprintf(dhp, "\t<%s>", asistr);
963 966
964 967 return (0);
965 968 }
966 969
967 970 /*
968 971 * format a load/store instruction
969 972 * format: ldXX [%rs1 + %rs2], %rd load, i==0
970 973 * ldXX [%rs1 +/- nn], %rd load, i==1
971 974 * ldXX [%rs1 + %rs2] #XX, %rd load w/ imm_asi, i==0
972 975 * ldXX [%rs1 +/- nn] %asi, %rd load from asi[%asi], i==1
973 976 *
974 977 * stXX %rd, [%rs1 + %rs2] store, i==0
975 978 * stXX %rd, [%rs1 +/- nn] store, i==1
976 979 * stXX %rd, [%rs1 + %rs1] #XX store to imm_asi, i==0
977 980 * stXX %rd, [%rs1 +/-nn] %asi store to asi[%asi], i==1
978 981 *
979 982 * The register sets used for %rd are set in the instructions flags field
980 983 * The asi variants are used if FLG_ASI is set in the instructions flags field
981 984 *
982 985 * If DIS_DEBUG_SYNTH_ALL or DIS_DEBUG_COMPAT are set,
983 986 * When %rs1, %rs2 or nn are 0, they are not printed, i.e.
984 987 * [ %rs1 + 0x0 ], %rd -> [%rs1], %rd for example
985 988 *
986 989 * The following synthetic instructions are also implemented:
987 990 *
988 991 * stb %g0, [addr] -> clrb [addr] DIS_DEBUG_SYNTH_ALL
989 992 * sth %g0, [addr] -> crlh [addr] DIS_DEBUG_SYNTH_ALL
990 993 * stw %g0, [addr] -> clr [addr] DIS_DEBUG_SYNTH_ALL|DIS_DEBUG_COMPAT
991 994 * stx %g0, [addr] -> clrx [addr] DIS_DEBUG_SYNTH_ALL
↓ open down ↓ |
26 lines elided |
↑ open up ↑ |
992 995 *
993 996 * If DIS_DEBUG_COMPAT is set, the following substitutions also take place
994 997 * lduw -> ld
995 998 * ldtw -> ld
996 999 * stuw -> st
997 1000 * sttw -> st
998 1001 */
999 1002 int
1000 1003 fmt_ls(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1001 1004 {
1005 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1002 1006 ifmt_t *f = (ifmt_t *)&instr;
1003 1007 const char *regstr = NULL;
1004 1008 const char *asistr = NULL;
1005 1009
1006 1010 const char *iname = inp->in_data.in_def.in_name;
1007 1011 uint32_t flags = inp->in_data.in_def.in_flags;
1008 1012
1009 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1013 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1010 1014 prt_field("op", f->f3.op, 2);
1011 1015 prt_field("op3", f->f3.op3, 6);
1012 1016 prt_field("rs1", f->f3.rs1, 5);
1013 1017 prt_field("i", f->f3.i, 1);
1014 1018 if (f->f3.i != 0) {
1015 1019 prt_field("simm13", f->f3a.simm13, 13);
1016 1020 } else {
1017 1021 if ((flags & FLG_ASI) != 0)
1018 1022 prt_field("imm_asi", f->f3.asi, 8);
1019 1023 prt_field("rs2", f->f3.rs2, 5);
1020 1024 }
1021 1025 prt_field("rd", f->f3.rd, 5);
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
1022 1026 }
1023 1027
1024 1028 if (idx == 0x2d || idx == 0x3d) {
1025 1029 /* prefetch / prefetcha */
1026 1030
1027 1031 prt_name(dhp, iname, 1);
1028 1032
1029 1033 prt_address(dhp, instr, 0);
1030 1034
1031 1035 if (idx == 0x3d) {
1032 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
1036 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
1033 1037 prt_asi(dhp, instr);
1034 1038 }
1035 1039
1036 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1040 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1037 1041
1038 1042 /* fcn field is the same as rd */
1039 1043 if (prefetch_str[f->f3.rd] != NULL)
1040 - (void) strlcat(dhp->dh_buf, prefetch_str[f->f3.rd],
1041 - dhp->dh_buflen);
1044 + (void) strlcat(dhx->dhx_buf, prefetch_str[f->f3.rd],
1045 + dhx->dhx_buflen);
1042 1046 else
1043 1047 prt_imm(dhp, f->f3.rd, 0);
1044 1048
1045 1049 if (idx == 0x3d && f->f3.i == 0) {
1046 1050 asistr = get_asi_name(f->f3.asi);
1047 1051 if (asistr != NULL)
1048 1052 bprintf(dhp, "\t<%s>", asistr);
1049 1053 }
1050 1054
1051 1055 return (0);
1052 1056 }
1053 1057
1054 1058 /* casa / casxa */
1055 1059 if (idx == 0x3c || idx == 0x3e)
1056 1060 return (fmt_cas(dhp, instr, iname));
1057 1061
1058 1062 /* synthetic instructions & special cases */
1059 1063 switch (idx) {
1060 1064 case 0x00:
1061 1065 /* ld */
1062 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1066 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1063 1067 iname = "lduw";
1064 1068 break;
1065 1069
1066 1070 case 0x03:
1067 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1071 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1068 1072 iname = "ldtw";
1069 1073 break;
1070 1074
1071 1075 case 0x04:
1072 1076 /* stw */
1073 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1077 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1074 1078 iname = "stuw";
1075 1079
1076 1080 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1077 1081 == 0)
1078 1082 break;
1079 1083
1080 1084 if (f->f3.rd == 0) {
1081 1085 iname = "clr";
1082 1086 flags = FLG_RD(REG_NONE);
1083 1087 }
1084 1088 break;
1085 1089
1086 1090 case 0x05:
1087 1091 /* stb */
1088 1092 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1089 1093 == 0)
1090 1094 break;
1091 1095
1092 1096 if (f->f3.rd == 0) {
1093 1097 iname = "clrb";
1094 1098 flags = FLG_RD(REG_NONE);
1095 1099 }
1096 1100 break;
1097 1101
1098 1102 case 0x06:
1099 1103 /* sth */
1100 1104 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
↓ open down ↓ |
17 lines elided |
↑ open up ↑ |
1101 1105 == 0)
1102 1106 break;
1103 1107
1104 1108 if (f->f3.rd == 0) {
1105 1109 iname = "clrh";
1106 1110 flags = FLG_RD(REG_NONE);
1107 1111 }
1108 1112 break;
1109 1113
1110 1114 case 0x07:
1111 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1115 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1112 1116 iname = "sttw";
1113 1117 break;
1114 1118
1115 1119 case 0x0e:
1116 1120 /* stx */
1117 1121
1118 1122 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1119 1123 == 0)
1120 1124 break;
1121 1125
1122 1126 if (f->f3.rd == 0) {
1123 1127 iname = "clrx";
1124 1128 flags = FLG_RD(REG_NONE);
1125 1129 }
1126 1130 break;
1127 1131
1128 1132 case 0x13:
1129 1133 /* ldtwa */
1130 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0) &&
1134 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0) &&
1131 1135 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0))
1132 1136 iname = "ldtwa";
1133 1137 break;
1134 1138
1135 1139 case 0x17:
1136 1140 /* sttwa */
1137 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0) &&
1141 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0) &&
1138 1142 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0))
1139 1143 iname = "sttwa";
1140 1144 break;
1141 1145
1142 1146 case 0x21:
1143 1147 case 0x25:
1144 1148 /*
1145 1149 * on sparcv8 it merely says that rd != 1 should generate an
1146 1150 * exception, on v9, it is illegal
1147 1151 */
1148 1152 if ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) == 0)
1149 1153 break;
1150 1154
1151 1155 iname = (idx == 0x21) ? "ldx" : "stx";
1152 1156
1153 1157 if (f->f3.rd > 1)
1154 1158 return (-1);
1155 1159
1156 1160 break;
1157 1161
1158 1162 case 0x31:
1159 1163 /* stda */
1160 1164 switch (f->f3.asi) {
1161 1165 case 0xc0:
1162 1166 case 0xc1:
1163 1167 case 0xc8:
1164 1168 case 0xc9:
1165 1169 case 0xc2:
1166 1170 case 0xc3:
1167 1171 case 0xca:
1168 1172 case 0xcb:
1169 1173 case 0xc4:
1170 1174 case 0xc5:
1171 1175 case 0xcc:
1172 1176 case 0xcd:
1173 1177 /*
1174 1178 * store partial floating point, only valid w/
1175 1179 * vis
1176 1180 *
1177 1181 * Somewhat confusingly, it uses the same op
1178 1182 * code as 'stda' -- store double to alternate
1179 1183 * space. It is distinguised by specific
1180 1184 * imm_asi values (as seen above), and
1181 1185 * has a slightly different output syntax
1182 1186 */
1183 1187
1184 1188 if ((dhp->dh_flags & DIS_SPARC_V9_SGI) == 0)
1185 1189 break;
1186 1190 if (f->f3.i != 0)
1187 1191 break;
1188 1192 prt_name(dhp, iname, 1);
1189 1193 bprintf(dhp, "%s, %s, [%s] ",
1190 1194 get_regname(dhp, REG_FPD, f->f3.rd),
1191 1195 get_regname(dhp, REG_FPD, f->f3.rs2),
1192 1196 get_regname(dhp, REG_FPD, f->f3.rs1));
1193 1197 prt_asi(dhp, instr);
1194 1198 asistr = get_asi_name(f->f3.asi);
1195 1199 if (asistr != NULL)
1196 1200 bprintf(dhp, "\t<%s>", asistr);
1197 1201
1198 1202 return (0);
1199 1203
1200 1204 default:
1201 1205 break;
1202 1206 }
1203 1207
1204 1208 }
↓ open down ↓ |
57 lines elided |
↑ open up ↑ |
1205 1209
1206 1210 regstr = get_regname(dhp, FLG_RD_VAL(flags), f->f3.rd);
1207 1211
1208 1212 if (f->f3.i == 0)
1209 1213 asistr = get_asi_name(f->f3.asi);
1210 1214
1211 1215 prt_name(dhp, iname, 1);
1212 1216
1213 1217 if ((flags & FLG_STORE) != 0) {
1214 1218 if (regstr[0] != '\0') {
1215 - (void) strlcat(dhp->dh_buf, regstr, dhp->dh_buflen);
1216 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1219 + (void) strlcat(dhx->dhx_buf, regstr, dhx->dhx_buflen);
1220 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1217 1221 }
1218 1222
1219 1223 prt_address(dhp, instr, 0);
1220 1224 if ((flags & FLG_ASI) != 0) {
1221 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
1225 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
1222 1226 prt_asi(dhp, instr);
1223 1227 }
1224 1228 } else {
1225 1229 prt_address(dhp, instr, 0);
1226 1230 if ((flags & FLG_ASI) != 0) {
1227 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
1231 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
1228 1232 prt_asi(dhp, instr);
1229 1233 }
1230 1234
1231 1235 if (regstr[0] != '\0') {
1232 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1233 - (void) strlcat(dhp->dh_buf, regstr, dhp->dh_buflen);
1236 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1237 + (void) strlcat(dhx->dhx_buf, regstr, dhx->dhx_buflen);
1234 1238 }
1235 1239 }
1236 1240
1237 1241 if ((flags & FLG_ASI) != 0 && asistr != NULL)
1238 1242 bprintf(dhp, "\t<%s>", asistr);
1239 1243
1240 1244 return (0);
1241 1245 }
1242 1246
1243 1247 static int
1244 1248 fmt_cpop(dis_handle_t *dhp, uint32_t instr, const inst_t *inp)
1245 1249 {
1250 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1246 1251 ifmt_t *f = (ifmt_t *)&instr;
1247 1252 int flags = FLG_P1(REG_CP)|FLG_P2(REG_CP)|FLG_NOIMM|FLG_P3(REG_CP);
1248 1253
1249 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1254 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1250 1255 prt_field("op", f->fcp.op, 2);
1251 1256 prt_field("op3", f->fcp.op3, 6);
1252 1257 prt_field("opc", f->fcp.opc, 9);
1253 1258 prt_field("rs1", f->fcp.rs1, 5);
1254 1259 prt_field("rs2", f->fcp.rs2, 5);
1255 1260 prt_field("rd", f->fcp.rd, 5);
1256 1261 }
1257 1262
1258 1263 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1259 1264 prt_imm(dhp, f->fcp.opc, 0);
1260 1265
1261 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1266 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1262 1267 (void) prt_aluargs(dhp, instr, flags);
1263 1268
1264 1269 return (0);
1265 1270 }
1266 1271
1267 1272 static int
1268 1273 dis_fmt_rdwr(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1269 1274 {
1275 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1270 1276 const char *psr_str = "%psr";
1271 1277 const char *wim_str = "%wim";
1272 1278 const char *tbr_str = "%tbr";
1273 1279
1274 1280 const char *name = inp->in_data.in_def.in_name;
1275 1281 const char *regstr = NULL;
1276 1282
1277 1283 ifmt_t *f = (ifmt_t *)&instr;
1278 1284
1279 1285 int rd = (idx < 0x30);
1280 1286 int v9 = (dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI));
1281 1287 int ridx = f->f3.rs1;
1282 1288 int i, first;
1283 1289 int pr_rs1 = 1;
1284 1290 int pr_rs2 = 1;
1285 1291
1286 1292 int use_mask = 1;
1287 1293 uint32_t mask;
1288 1294
1289 1295 if (rd == 0)
1290 1296 ridx = f->f3.rd;
1291 1297
1292 1298 switch (idx) {
1293 1299 case 0x28:
1294 1300 /* rd */
1295 1301
1296 1302 /* stbar */
1297 1303 if ((f->f3.rd == 0) && (f->f3.rs1 == 15) && (f->f3.i == 0)) {
1298 1304 prt_name(dhp, "stbar", 0);
1299 1305 return (0);
1300 1306 }
1301 1307
1302 1308 /* membar */
1303 1309 if ((v9 != 0) && (f->f3.rd == 0) && (f->f3.rs1 == 15) &&
1304 1310 (f->f3.i == 1) && ((f->i & (1L << 12)) == 0)) {
1305 1311
1306 1312 prt_name(dhp, "membar",
1307 1313 ((f->fmb.cmask != 0) || (f->fmb.mmask != 0)));
1308 1314
1309 1315 first = 0;
1310 1316
1311 1317 for (i = 0; i < 4; ++i) {
1312 1318 if ((f->fmb.cmask & (1L << i)) != 0) {
1313 1319 bprintf(dhp, "%s%s",
1314 1320 (first != 0) ? "|" : "",
1315 1321 membar_cmask[i]);
1316 1322 first = 1;
1317 1323 }
1318 1324 }
1319 1325
1320 1326 for (i = 0; i < 5; ++i) {
1321 1327 if ((f->fmb.mmask & (1L << i)) != 0) {
1322 1328 bprintf(dhp, "%s%s",
1323 1329 (first != 0) ? "|" : "",
1324 1330 membar_mmask[i]);
1325 1331 first = 1;
1326 1332 }
1327 1333 }
1328 1334
1329 1335 return (0);
1330 1336 }
1331 1337
1332 1338 if (v9 != 0) {
1333 1339 regstr = v9_asr_names[ridx];
1334 1340 mask = v9_asr_rdmask;
1335 1341 } else {
1336 1342 regstr = asr_names[ridx];
1337 1343 mask = asr_rdmask;
1338 1344 }
1339 1345 break;
1340 1346
1341 1347 case 0x29:
1342 1348 if (v9 != 0) {
1343 1349 regstr = v9_hprivreg_names[ridx];
1344 1350 mask = v9_hpr_rdmask;
1345 1351 } else {
1346 1352 regstr = psr_str;
1347 1353 use_mask = 0;
1348 1354 }
1349 1355 break;
1350 1356
1351 1357 case 0x2a:
1352 1358 if (v9 != 0) {
1353 1359 regstr = v9_privreg_names[ridx];
1354 1360 mask = v9_pr_rdmask;
1355 1361 } else {
1356 1362 regstr = wim_str;
1357 1363 use_mask = 0;
1358 1364 }
1359 1365 break;
1360 1366
1361 1367 case 0x2b:
1362 1368 if (v9 != 0) {
1363 1369 /* flushw */
1364 1370 prt_name(dhp, name, 0);
1365 1371 return (0);
1366 1372 }
1367 1373
1368 1374 regstr = tbr_str;
1369 1375 use_mask = 0;
1370 1376 break;
1371 1377
1372 1378 case 0x30:
1373 1379 if (v9 != 0) {
1374 1380 regstr = v9_asr_names[ridx];
1375 1381 mask = v9_asr_wrmask;
1376 1382 } else {
1377 1383 regstr = asr_names[ridx];
1378 1384 mask = asr_wrmask;
1379 1385 }
1380 1386
1381 1387 /*
1382 1388 * sir is shoehorned in here, per Ultrasparc 2007
1383 1389 * hyperprivileged edition, section 7.88, all of
1384 1390 * these must be true to distinguish from WRasr
↓ open down ↓ |
105 lines elided |
↑ open up ↑ |
1385 1391 */
1386 1392 if (v9 != 0 && f->f3.rd == 15 && f->f3.rs1 == 0 &&
1387 1393 f->f3.i == 1) {
1388 1394 prt_name(dhp, "sir", 1);
1389 1395 prt_imm(dhp, sign_extend(f->f3a.simm13, 13),
1390 1396 IMM_SIGNED);
1391 1397 return (0);
1392 1398 }
1393 1399
1394 1400 /* synth: mov */
1395 - if ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1401 + if ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1396 1402 == 0)
1397 1403 break;
1398 1404
1399 1405 if (v9 == 0) {
1400 1406 if (f->f3.rs1 == 0) {
1401 1407 name = "mov";
1402 1408 pr_rs1 = 0;
1403 1409 }
1404 1410
1405 1411 if ((f->f3.i == 0 && f->f3.rs2 == 0) ||
1406 1412 (f->f3.i == 1 && f->f3a.simm13 == 0)) {
1407 1413 name = "mov";
1408 1414 pr_rs2 = 0;
1409 1415 }
1410 1416 }
1411 1417
1412 1418 if (pr_rs1 == 0)
1413 1419 pr_rs2 = 1;
1414 1420
1415 1421 break;
1416 1422
1417 1423 case 0x31:
1418 1424 /*
1419 1425 * NOTE: due to the presence of an overlay entry for another
1420 1426 * table, this case only happens when doing v8 instructions
1421 1427 * only
1422 1428 */
1423 1429 regstr = psr_str;
1424 1430 use_mask = 0;
1425 1431 break;
1426 1432
1427 1433 case 0x32:
1428 1434 if (v9 != 0) {
1429 1435 regstr = v9_privreg_names[ridx];
1430 1436 mask = v9_pr_wrmask;
1431 1437 } else {
1432 1438 regstr = wim_str;
1433 1439 use_mask = 0;
1434 1440 }
1435 1441 break;
1436 1442
1437 1443 case 0x33:
1438 1444 if (v9 != 0) {
1439 1445 regstr = v9_hprivreg_names[ridx];
1440 1446 mask = v9_hpr_wrmask;
1441 1447 } else {
1442 1448 regstr = tbr_str;
1443 1449 use_mask = 0;
1444 1450 }
1445 1451 break;
1446 1452 }
1447 1453
1448 1454 if (regstr == NULL)
1449 1455 return (-1);
1450 1456
1451 1457 if (use_mask != 0 && ((1L << ridx) & mask) == 0)
1452 1458 return (-1);
1453 1459
1454 1460 prt_name(dhp, name, 1);
1455 1461
1456 1462 if (rd != 0) {
↓ open down ↓ |
51 lines elided |
↑ open up ↑ |
1457 1463 bprintf(dhp, "%s, %s", regstr, reg_names[f->f3.rd]);
1458 1464 } else {
1459 1465 if (pr_rs1 == 1)
1460 1466 bprintf(dhp, "%s, ", reg_names[f->f3.rs1]);
1461 1467
1462 1468 if (pr_rs2 != 0) {
1463 1469 if (f->f3.i == 1)
1464 1470 prt_imm(dhp, sign_extend(f->f3a.simm13, 13),
1465 1471 IMM_SIGNED);
1466 1472 else
1467 - (void) strlcat(dhp->dh_buf,
1468 - reg_names[f->f3.rs2], dhp->dh_buflen);
1469 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1473 + (void) strlcat(dhx->dhx_buf,
1474 + reg_names[f->f3.rs2], dhx->dhx_buflen);
1475 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1470 1476 }
1471 1477
1472 - (void) strlcat(dhp->dh_buf, regstr, dhp->dh_buflen);
1478 + (void) strlcat(dhx->dhx_buf, regstr, dhx->dhx_buflen);
1473 1479 }
1474 1480
1475 1481 return (0);
1476 1482 }
1477 1483
1478 1484 /* ARGSUSED3 */
1479 1485 int
1480 1486 fmt_trap(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1481 1487 {
1488 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1482 1489 ifmt_t *f = (ifmt_t *)&instr;
1483 1490
1484 1491 int v9 = ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0);
1485 1492 int p_rs1, p_t;
1486 1493
1487 1494 if (f->ftcc.undef != 0)
1488 1495 return (-1);
1489 1496
1490 1497 if (icc_names[f->ftcc.cc] == NULL)
1491 1498 return (-1);
1492 1499
1493 1500 if (f->ftcc.i == 1 && f->ftcc.undef2 != 0)
1494 1501 return (-1);
1495 1502
1496 1503 if (f->ftcc2.i == 0 && f->ftcc2.undef2 != 0)
1497 1504 return (-1);
1498 1505
1499 1506 p_rs1 = ((f->ftcc.rs1 != 0) ||
1500 - ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0));
1507 + ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0));
1501 1508
1502 1509 if (f->ftcc.i == 0) {
1503 1510 p_t = (f->f3.rs2 != 0 || p_rs1 == 0);
1504 1511
1505 1512 bprintf(dhp, "%-9s %s%s%s%s%s", inp->in_data.in_def.in_name,
1506 1513 (v9 != 0) ? icc_names[f->ftcc2.cc] : "",
1507 1514 (v9 != 0) ? ", " : "",
1508 1515 (p_rs1 != 0) ? reg_names[f->ftcc2.rs1] : "",
1509 1516 (p_rs1 != 0) ? " + " : "",
1510 1517 (p_t != 0) ? reg_names[f->f3.rs2] : "");
1511 1518 } else {
1512 1519 bprintf(dhp, "%-9s %s%s%s%s0x%x", inp->in_data.in_def.in_name,
1513 1520 (v9 != 0) ? icc_names[f->ftcc2.cc] : "",
1514 1521 (v9 != 0) ? ", " : "",
1515 1522 (p_rs1 != 0) ? reg_names[f->ftcc2.rs1] : "",
1516 1523 (p_rs1 != 0) ? " + " : "",
1517 1524 f->ftcc.immtrap);
1518 1525 }
1519 1526 return (0);
1520 1527 }
1521 1528
1522 1529 static int
1523 1530 prt_shift(dis_handle_t *dhp, uint32_t instr, const inst_t *inp)
1524 1531 {
1525 1532 char name[5];
1526 1533 uint32_t cnt;
1527 1534
1528 1535 ifmt_t *f = (ifmt_t *)&instr;
1529 1536 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
1530 1537
1531 1538 name[0] = '\0';
1532 1539 (void) strlcat(name, inp->in_data.in_def.in_name, sizeof (name));
1533 1540
1534 1541 if (f->f3b.i == 1)
1535 1542 cnt = f->f3.rs2;
1536 1543
1537 1544 if (f->f3b.x == 1 && ((dhp->dh_flags & DIS_SPARC_V8) == 0)) {
1538 1545 cnt = f->f3b.shcnt;
1539 1546 (void) strlcat(name, "x", sizeof (name));
1540 1547 }
1541 1548
1542 1549 prt_name(dhp, name, 1);
1543 1550
1544 1551 if (f->f3b.i == 1)
1545 1552 bprintf(dhp, (octal != 0) ? "%s, 0%lo, %s" : "%s, 0x%lx, %s",
1546 1553 reg_names[f->f3.rs1], cnt, reg_names[f->f3.rd]);
1547 1554 else
↓ open down ↓ |
37 lines elided |
↑ open up ↑ |
1548 1555 bprintf(dhp, "%s, %s, %s", reg_names[f->f3.rs1],
1549 1556 reg_names[f->f3.rs2], reg_names[f->f3.rd]);
1550 1557
1551 1558 return (0);
1552 1559 }
1553 1560
1554 1561 /* ARGSUSED3 */
1555 1562 static int
1556 1563 prt_jmpl(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1557 1564 {
1565 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1558 1566 const char *name = inp->in_data.in_def.in_name;
1559 1567 ifmt_t *f = (ifmt_t *)&instr;
1560 1568
1561 - if (f->f3.rd == 15 && ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0))
1569 + if (f->f3.rd == 15 && ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0))
1562 1570 name = "call";
1563 1571
1564 1572 if (f->f3.rd == 0) {
1565 1573 if (f->f3.i == 1 && f->f3a.simm13 == 8) {
1566 1574 if (f->f3.rs1 == 15) {
1567 1575 prt_name(dhp, "retl", 0);
1568 1576 return (0);
1569 1577 }
1570 1578
1571 1579 if (f->f3.rs1 == 31) {
1572 1580 prt_name(dhp, "ret", 0);
1573 1581 return (0);
1574 1582 }
1575 1583 }
↓ open down ↓ |
4 lines elided |
↑ open up ↑ |
1576 1584
1577 1585 name = "jmp";
1578 1586 }
1579 1587
1580 1588 prt_name(dhp, name, 1);
1581 1589 prt_address(dhp, instr, 1);
1582 1590
1583 1591 if (f->f3.rd == 0)
1584 1592 return (0);
1585 1593
1586 - if (f->f3.rd == 15 && ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0))
1594 + if (f->f3.rd == 15 && ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0))
1587 1595 return (0);
1588 1596
1589 1597 bprintf(dhp, ", %s", reg_names[f->f3.rd]);
1590 1598
1591 1599 return (0);
1592 1600 }
1593 1601
1594 1602 int
1595 1603 fmt_alu(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1596 1604 {
1605 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1597 1606 ifmt_t *f = (ifmt_t *)&instr;
1598 1607
1599 1608 const char *name = inp->in_data.in_def.in_name;
1600 1609 int flags = inp->in_data.in_def.in_flags;
1601 1610 int arg = 0;
1602 1611
1603 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1612 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1604 1613 prt_field("op", f->f3.op, 2);
1605 1614 prt_field("op3", f->f3.op3, 6);
1606 1615 prt_field("rs1", f->f3.rs1, 5);
1607 1616
1608 1617 switch (idx) {
1609 1618 /* TODO: more formats */
1610 1619
1611 1620 default:
1612 1621 if (f->f3.i == 0)
1613 1622 prt_field("rs2", f->f3.rs2, 5);
1614 1623 else
1615 1624 prt_field("simm13", f->f3a.simm13, 13);
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
1616 1625
1617 1626 prt_field("rd", f->f3.rd, 5);
1618 1627 }
1619 1628
1620 1629 }
1621 1630
1622 1631 switch (idx) {
1623 1632 case 0x00:
1624 1633 /* add */
1625 1634
1626 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) == 0)
1635 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) == 0)
1627 1636 break;
1628 1637
1629 1638 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1630 1639 f->f3a.simm13 == 1) {
1631 1640 name = "inc";
1632 1641 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1633 1642 break;
1634 1643 }
1635 1644
1636 1645 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1637 1646 f->f3a.simm13 != 1) {
1638 1647 name = "inc";
1639 1648 flags = FLG_P1(REG_NONE);
1640 1649 break;
1641 1650 }
1642 1651 break;
1643 1652
1644 1653 case 0x02:
1645 1654 /* or */
1646 1655
1647 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1656 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1648 1657 == 0)
1649 1658 break;
1650 1659
1651 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) != 0) {
1660 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) != 0) {
1652 1661 if (f->f3.rs1 == f->f3.rd) {
1653 1662 name = "bset";
1654 1663 flags = FLG_P1(REG_NONE);
1655 1664 break;
1656 1665 }
1657 1666 }
1658 1667
1659 1668 if (((f->f3.i == 0 && f->f3.rs2 == 0) ||
1660 1669 (f->f3.i == 1 && f->f3a.simm13 == 0)) &&
1661 1670 (f->f3.rs1 == 0)) {
1662 1671 name = "clr";
1663 1672 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1664 1673 break;
1665 1674 }
1666 1675
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
1667 1676 if (f->f3.rs1 == 0) {
1668 1677 name = "mov";
1669 1678 flags = FLG_P1(REG_NONE);
1670 1679 break;
1671 1680 }
1672 1681 break;
1673 1682
1674 1683 case 0x04:
1675 1684 /* sub */
1676 1685
1677 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1686 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1678 1687 == 0)
1679 1688 break;
1680 1689
1681 1690 if (f->f3.rs1 == 0 && f->f3.i == 0 && f->f3.rs2 == f->f3.rd) {
1682 1691 name = "neg";
1683 1692 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE);
1684 1693 break;
1685 1694 }
1686 1695
1687 1696 if (f->f3.rs1 == 0 && f->f3.i == 0 && f->f3.rs2 != f->f3.rd) {
1688 1697 name = "neg";
1689 1698 flags = FLG_P1(REG_NONE);
1690 1699 break;
1691 1700 }
1692 1701
1693 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) == 0)
1702 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) == 0)
1694 1703 break;
1695 1704
1696 1705 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1697 1706 f->f3a.simm13 == 1) {
1698 1707 name = "dec";
1699 1708 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1700 1709 break;
1701 1710 }
1702 1711
1703 1712 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1704 1713 f->f3a.simm13 != 1) {
1705 1714 name = "dec";
1706 1715 flags = FLG_P1(REG_NONE);
1707 1716 break;
1708 1717 }
1709 1718 break;
1710 1719
1711 1720 case 0x07:
1712 1721 /* xnor */
1713 1722
1714 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1723 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1715 1724 == 0)
1716 1725 break;
1717 1726
1718 1727 /*
1719 1728 * xnor -> not when you have:
1720 1729 * xnor %rs1, 0x0 or %g0, %rd
1721 1730 */
1722 1731 if ((f->f3.i == 0 && f->f3.rs2 != 0) ||
1723 1732 (f->f3.i == 1 && f->f3a.simm13 != 0))
1724 1733 break;
1725 1734
1726 1735 name = "not";
1727 1736
1728 1737 if (f->f3.rs1 == f->f3.rd)
1729 1738 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
1730 1739 FLG_P3(REG_INT);
1731 1740 else
1732 1741 flags = FLG_P1(REG_INT)|FLG_P2(REG_NONE)|FLG_NOIMM|
1733 1742 FLG_P3(REG_INT);
1734 1743
1735 1744 break;
1736 1745
1737 1746 case 0x10:
1738 1747 /* addcc */
1739 1748
1740 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) == 0)
1749 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) == 0)
1741 1750 break;
1742 1751
1743 1752 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1744 1753 f->f3a.simm13 == 1) {
1745 1754 name = "inccc";
1746 1755 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1747 1756 break;
1748 1757 }
1749 1758
1750 1759 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1751 1760 f->f3a.simm13 != 1) {
1752 1761 name = "inccc";
1753 1762 flags = FLG_P1(REG_NONE);
↓ open down ↓ |
3 lines elided |
↑ open up ↑ |
1754 1763 break;
1755 1764 }
1756 1765 break;
1757 1766
1758 1767 case 0x11:
1759 1768 /* andcc */
1760 1769
1761 1770 if (f->f3.rd != 0)
1762 1771 break;
1763 1772
1764 - if ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1773 + if ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1765 1774 == 0)
1766 1775 break;
1767 1776
1768 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0) &&
1777 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0) &&
1769 1778 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) == 0))
1770 1779 break;
1771 1780
1772 1781 name = "btst";
1773 1782 flags = FLG_P1(REG_NONE);
1774 1783 f->f3.rd = f->f3.rs1;
1775 1784 break;
1776 1785
1777 1786 case 0x12:
1778 1787 /* orcc */
1779 1788
1780 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1789 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1781 1790 == 0)
1782 1791 break;
1783 1792
1784 1793 if (f->f3.rs1 == 0 && f->f3.rd == 0 && f->f3.i == 0) {
1785 1794 name = "tst";
1786 1795 flags = FLG_P1(REG_NONE)|FLG_P3(REG_NONE);
1787 1796 break;
1788 1797 }
1789 1798
1790 1799 if (f->f3.rs2 == 0 && f->f3.rd == 0 && f->f3.i == 0) {
1791 1800 name = "tst";
1792 1801 flags = FLG_P2(REG_NONE)|FLG_P3(REG_NONE);
1793 1802 break;
1794 1803 }
1795 1804
1796 1805 break;
1797 1806
1798 1807 case 0x14:
1799 1808 /* subcc */
1800 1809
1801 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1810 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1802 1811 == 0)
1803 1812 break;
1804 1813
1805 1814 if (f->f3.rd == 0) {
1806 1815 name = "cmp";
1807 1816 flags = FLG_P3(REG_NONE);
1808 1817 break;
1809 1818 }
1810 1819
1811 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0)
1820 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0)
1812 1821 break;
1813 1822
1814 1823 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1815 1824 f->f3a.simm13 == 1) {
1816 1825 name = "deccc";
1817 1826 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1818 1827 break;
1819 1828 }
1820 1829
1821 1830 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1822 1831 f->f3a.simm13 != 1) {
1823 1832 name = "deccc";
1824 1833 flags = FLG_P1(REG_NONE);
1825 1834 break;
1826 1835 }
1827 1836
1828 1837 break;
1829 1838
1830 1839 case 0x25:
1831 1840 case 0x26:
1832 1841 case 0x27:
1833 1842 return (prt_shift(dhp, instr, inp));
1834 1843
1835 1844 case 0x28:
1836 1845 case 0x29:
1837 1846 case 0x2a:
1838 1847 case 0x2b:
1839 1848 case 0x30:
1840 1849 case 0x31:
1841 1850 case 0x32:
1842 1851 case 0x33:
1843 1852 return (dis_fmt_rdwr(dhp, instr, inp, idx));
1844 1853
1845 1854 case 0x36:
1846 1855 case 0x37:
1847 1856 /* NOTE: overlayed on v9 */
1848 1857 if ((dhp->dh_flags & DIS_SPARC_V8) != 0)
1849 1858 return (fmt_cpop(dhp, instr, inp));
1850 1859 break;
1851 1860
1852 1861 case 0x38:
1853 1862 /* jmpl */
1854 1863 return (prt_jmpl(dhp, instr, inp, idx));
1855 1864
1856 1865 case 0x39:
1857 1866 /* rett / return */
1858 1867 prt_name(dhp, name, 1);
1859 1868 prt_address(dhp, instr, 1);
1860 1869 return (0);
↓ open down ↓ |
39 lines elided |
↑ open up ↑ |
1861 1870
1862 1871 case 0x3b:
1863 1872 /* flush */
1864 1873 prt_name(dhp, name, 1);
1865 1874 prt_address(dhp, instr, 0);
1866 1875 return (0);
1867 1876
1868 1877 case 0x3c:
1869 1878 case 0x3d:
1870 1879 /* save / restore */
1871 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1880 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1872 1881 == 0)
1873 1882 break;
1874 1883
1875 1884 if (f->f3.rs1 != 0 || f->f3.rs2 != 0 || f->f3.rd != 0)
1876 1885 break;
1877 1886
1878 - if (f->f3.i != 0 && ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0))
1887 + if (f->f3.i != 0 && ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0))
1879 1888 break;
1880 1889
1881 1890 prt_name(dhp, name, 0);
1882 1891 return (0);
1883 1892 }
1884 1893
1885 1894 if (FLG_P1_VAL(flags) != REG_NONE || FLG_P2_VAL(flags) != REG_NONE ||
1886 1895 FLG_P3_VAL(flags) != REG_NONE)
1887 1896 arg = 1;
1888 1897
1889 1898 prt_name(dhp, name, (arg != 0));
1890 1899 prt_aluargs(dhp, instr, flags);
1891 1900
1892 1901 return (0);
1893 1902 }
1894 1903
1895 1904 /* ARGSUSED1 */
1896 1905 int
1897 1906 fmt_regwin(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1898 1907 {
1899 1908 prt_name(dhp, inp->in_data.in_def.in_name, 0);
1900 1909 return (0);
1901 1910 }
1902 1911
1903 1912 /* ARGSUSED1 */
1904 1913 int
1905 1914 fmt_trap_ret(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1906 1915 {
1907 1916 ifmt_t *f = (ifmt_t *)&instr;
1908 1917 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1909 1918
1910 1919 if (f->f3.rd == 0xf) {
1911 1920 /* jpriv */
↓ open down ↓ |
23 lines elided |
↑ open up ↑ |
1912 1921 prt_address(dhp, instr, 1);
1913 1922 }
1914 1923
1915 1924 return (0);
1916 1925 }
1917 1926
1918 1927 /* ARGSUSED3 */
1919 1928 int
1920 1929 fmt_movcc(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1921 1930 {
1931 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1922 1932 ifmt_t *f = (ifmt_t *)&instr;
1923 1933 const char **regs = NULL;
1924 1934
1925 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1935 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1926 1936 prt_field("op", f->f3c.op, 2);
1927 1937 prt_field("op3", f->f3c.op3, 6);
1928 1938 prt_field("cond", f->f3c.cond, 4);
1929 1939 prt_field("cc2", f->f3c.cc2, 1);
1930 1940 prt_field("cc", f->f3c.cc, 2);
1931 1941 prt_field("i", f->f3c.i, 1);
1932 1942
1933 1943 if (f->f3c.i == 0)
1934 1944 prt_field("rs2", f->f3.rs2, 5);
1935 1945 else
1936 1946 prt_field("simm11", f->f3c.simm11, 11);
1937 1947
1938 1948 prt_field("rd", f->f3.rd, 5);
1939 1949 }
1940 1950
1941 1951 if (f->f3c.cc2 == 0) {
1942 1952 regs = fcc_names;
1943 1953 } else {
1944 1954 regs = icc_names;
1945 1955 if (regs[f->f3c.cc] == NULL)
↓ open down ↓ |
10 lines elided |
↑ open up ↑ |
1946 1956 return (-1);
1947 1957 }
1948 1958
1949 1959 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1950 1960
1951 1961 bprintf(dhp, "%s, ", regs[f->f3c.cc]);
1952 1962
1953 1963 if (f->f3c.i == 1)
1954 1964 prt_imm(dhp, sign_extend(f->f3c.simm11, 11), IMM_SIGNED);
1955 1965 else
1956 - (void) strlcat(dhp->dh_buf, reg_names[f->f3.rs2],
1957 - dhp->dh_buflen);
1966 + (void) strlcat(dhx->dhx_buf, reg_names[f->f3.rs2],
1967 + dhx->dhx_buflen);
1958 1968
1959 1969 bprintf(dhp, ", %s", reg_names[f->f3.rd]);
1960 1970
1961 1971 return (0);
1962 1972 }
1963 1973
1964 1974 /* ARGSUSED3 */
1965 1975 int
1966 1976 fmt_movr(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1967 1977 {
1978 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1968 1979 ifmt_t *f = (ifmt_t *)&instr;
1969 1980
1970 1981 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1971 1982
1972 1983 bprintf(dhp, "%s, ", reg_names[f->f3d.rs1]);
1973 1984
1974 1985 if (f->f3d.i == 1)
1975 1986 prt_imm(dhp, sign_extend(f->f3d.simm10, 10), IMM_SIGNED);
1976 1987 else
1977 - (void) strlcat(dhp->dh_buf, reg_names[f->f3.rs2],
1978 - dhp->dh_buflen);
1988 + (void) strlcat(dhx->dhx_buf, reg_names[f->f3.rs2],
1989 + dhx->dhx_buflen);
1979 1990
1980 1991 bprintf(dhp, ", %s", reg_names[f->f3.rd]);
1981 1992
1982 1993 return (0);
1983 1994 }
1984 1995
1985 1996 /* ARGSUSED3 */
1986 1997 int
1987 1998 fmt_fpop1(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1988 1999 {
2000 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1989 2001 ifmt_t *f = (ifmt_t *)&instr;
1990 2002 int flags = inp->in_data.in_def.in_flags;
1991 2003
1992 2004 flags |= FLG_NOIMM;
1993 2005
1994 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
2006 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1995 2007 prt_field("op", f->f3.op, 2);
1996 2008 prt_field("op3", f->f3.op3, 6);
1997 2009 prt_field("opf", f->fcmp.opf, 9);
1998 2010 prt_field("rs1", f->f3.rs1, 5);
1999 2011 prt_field("rs2", f->f3.rs2, 5);
2000 2012 prt_field("rd", f->f3.rd, 5);
2001 2013 }
2002 2014
2003 2015 prt_name(dhp, inp->in_data.in_def.in_name, 1);
2004 2016 prt_aluargs(dhp, instr, flags);
2005 2017
2006 2018 return (0);
2007 2019 }
2008 2020
2009 2021 int
2010 2022 fmt_fpop2(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
2011 2023 {
↓ open down ↓ |
7 lines elided |
↑ open up ↑ |
2012 2024 static const char *condstr_icc[16] = {
2013 2025 "n", "e", "le", "l", "leu", "lu", "neg", "vs",
2014 2026 "a", "nz", "g", "ge", "gu", "geu", "pos", "vc"
2015 2027 };
2016 2028
2017 2029 static const char *condstr_fcc[16] = {
2018 2030 "n", "nz", "lg", "ul", "l", "ug", "g", "u",
2019 2031 "a", "e", "ue", "ge", "uge", "le", "ule", "o"
2020 2032 };
2021 2033
2034 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2022 2035 ifmt_t *f = (ifmt_t *)&instr;
2023 2036 const char *ccstr = "";
2024 2037 char name[15];
2025 2038
2026 2039 int flags = inp->in_data.in_def.in_flags;
2027 2040 int is_cmp = (idx == 0x51 || idx == 0x52 || idx == 0x53 ||
2028 2041 idx == 0x55 || idx == 0x56 || idx == 0x57);
2029 2042 int is_fmov = (idx & 0x3f);
2030 2043 int is_v9 = ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0);
2031 - int is_compat = ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0);
2044 + int is_compat = ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0);
2032 2045
2033 2046 int p_cc = 0;
2034 2047
2035 2048 is_fmov = (is_fmov == 0x1 || is_fmov == 0x2 || is_fmov == 0x3);
2036 2049
2037 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
2050 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
2038 2051 prt_field("op", f->f3.op, 2);
2039 2052 prt_field("op3", f->f3.op3, 6);
2040 2053 prt_field("opf", f->fcmp.opf, 9);
2041 2054
2042 2055 switch (idx & 0x3f) {
2043 2056 case 0x51:
2044 2057 case 0x52:
2045 2058 case 0x53:
2046 2059 case 0x55:
2047 2060 case 0x56:
2048 2061 case 0x57:
2049 2062 prt_field("cc", f->fcmp.cc, 2);
2050 2063 prt_field("rs1", f->f3.rs1, 5);
2051 2064 prt_field("rs2", f->f3.rs2, 5);
2052 2065 break;
2053 2066
2054 2067 case 0x01:
2055 2068 case 0x02:
2056 2069 case 0x03:
2057 2070 prt_field("opf_low", f->fmv.opf, 6);
2058 2071 prt_field("cond", f->fmv.cond, 4);
2059 2072 prt_field("opf_cc", f->fmv.cc, 3);
2060 2073 prt_field("rs2", f->fmv.rs2, 5);
2061 2074 break;
2062 2075
2063 2076 default:
2064 2077 prt_field("rs1", f->f3.rs1, 5);
2065 2078 prt_field("rs2", f->f3.rs2, 5);
2066 2079 prt_field("rd", f->f3.rd, 5);
2067 2080 }
2068 2081 }
2069 2082
2070 2083 name[0] = '\0';
2071 2084 (void) strlcat(name, inp->in_data.in_def.in_name, sizeof (name));
2072 2085
2073 2086 if (is_fmov != 0) {
2074 2087 (void) strlcat(name,
2075 2088 (f->fmv.cc < 4) ? condstr_fcc[f->fmv.cond]
2076 2089 : condstr_icc[f->fmv.cond],
2077 2090 sizeof (name));
2078 2091 }
2079 2092
2080 2093 prt_name(dhp, name, 1);
2081 2094
2082 2095 if (is_cmp != 0)
2083 2096 ccstr = fcc_names[f->fcmp.cc];
2084 2097
2085 2098 if (is_fmov != 0)
2086 2099 ccstr = (f->fmv.cc < 4) ? fcc_names[f->fmv.cc & 0x3]
2087 2100 : icc_names[f->fmv.cc & 0x3];
2088 2101
2089 2102 if (ccstr == NULL)
2090 2103 return (-1);
2091 2104
2092 2105 p_cc = (is_compat == 0 || is_v9 != 0 ||
2093 2106 (is_cmp != 0 && f->fcmp.cc != 0) ||
2094 2107 (is_fmov != 0 && f->fmv.cc != 0));
2095 2108
2096 2109 if (p_cc != 0)
↓ open down ↓ |
49 lines elided |
↑ open up ↑ |
2097 2110 bprintf(dhp, "%s, ", ccstr);
2098 2111
2099 2112 prt_aluargs(dhp, instr, flags);
2100 2113
2101 2114 return (0);
2102 2115 }
2103 2116
2104 2117 int
2105 2118 fmt_vis(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
2106 2119 {
2120 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2107 2121 ifmt_t *f = (ifmt_t *)&instr;
2108 2122 int flags = inp->in_data.in_def.in_flags;
2109 2123
2110 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
2124 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
2111 2125 prt_field("op", f->f3.op, 2);
2112 2126 prt_field("op3", f->f3.op3, 6);
2113 2127 prt_field("opf", f->fcmp.opf, 9);
2114 2128
2115 2129 if (idx == 0x081) {
2116 2130 prt_field("mode", instr & 02L, 2);
2117 2131 } else {
2118 2132 prt_field("rs1", f->f3.rs1, 5);
2119 2133 prt_field("rs2", f->f3.rs2, 5);
2120 2134 prt_field("rd", f->f3.rd, 5);
2121 2135 }
2122 2136 }
2123 2137
2124 2138 prt_name(dhp, inp->in_data.in_def.in_name, 1);
2125 2139
2126 2140 if (idx == 0x081) {
2127 2141 /* siam */
2128 2142 bprintf(dhp, "%d", instr & 0x7L);
2129 2143 return (0);
2130 2144 }
2131 2145
2132 2146 prt_aluargs(dhp, instr, flags);
2133 2147
2134 2148 return (0);
2135 2149 }
2136 2150
2137 2151 /* ARGSUSED3 */
2138 2152 int
2139 2153 fmt_fused(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
2140 2154 {
2141 2155 ifmt_t *f = (ifmt_t *)&instr;
2142 2156 int flags = inp->in_data.in_def.in_flags;
2143 2157
2144 2158 prt_name(dhp, inp->in_data.in_def.in_name, 1);
2145 2159 bprintf(dhp, "%s, %s, %s, %s",
2146 2160 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs1),
2147 2161 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs2),
2148 2162 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs3),
2149 2163 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rd));
2150 2164
2151 2165 return (0);
2152 2166 }
2153 2167 /*
2154 2168 * put name into the output buffer
2155 2169 * if add_space !=0, append a space after it
2156 2170 */
2157 2171 static void
2158 2172 prt_name(dis_handle_t *dhp, const char *name, int add_space)
2159 2173 {
2160 2174 bprintf(dhp, (add_space == 0) ? "%s" : "%-9s ", name);
2161 2175 }
2162 2176
2163 2177 /*
2164 2178 * For debugging, print out a field of the instruction
2165 2179 * field is the name of the field
2166 2180 * val is the value of the field
2167 2181 * len is the length of the field (in bits)
2168 2182 */
2169 2183 #if defined(DIS_STANDALONE)
2170 2184 /* ARGSUSED */
2171 2185 static void
2172 2186 prt_field(const char *field, uint32_t val, int len)
2173 2187 {
2174 2188
2175 2189 }
2176 2190
2177 2191 #else
2178 2192 static void
2179 2193 prt_field(const char *field, uint32_t val, int len)
2180 2194 {
2181 2195 (void) fprintf(stderr, "DISASM: %8s = 0x%-8x (", field, val);
2182 2196 prt_binary(val, len);
2183 2197 (void) fprintf(stderr, ")\n");
2184 2198 }
2185 2199 #endif /* DIS_STANDALONE */
2186 2200
2187 2201 /*
2188 2202 * sign extend a val (that is 'bits' bits in length) to a 32-bit signed
2189 2203 * integer
2190 2204 */
2191 2205 static int32_t
2192 2206 sign_extend(int32_t val, int32_t bits)
2193 2207 {
2194 2208 if ((val & (1L << (bits - 1))) == 0)
2195 2209 return (val);
2196 2210
2197 2211 return ((-1L << bits) | val);
2198 2212 }
2199 2213
2200 2214 /*
2201 2215 * print out an immediate (i.e. constant) value
2202 2216 * val is the value
2203 2217 * format indicates if it is:
2204 2218 * 0 Unsigned
2205 2219 * IMM_SIGNED A signed value (prepend +/- to the value)
2206 2220 * IMM_ADDR Part of an address expression (prepend +/- but with a space
2207 2221 * between the sign and the value for things like [%i1 + 0x55]
2208 2222 */
2209 2223 static void
2210 2224 prt_imm(dis_handle_t *dhp, uint32_t val, int format)
2211 2225 {
2212 2226 const char *fmtstr = NULL;
2213 2227 int32_t sv = (int32_t)val;
2214 2228 int octal = dhp->dh_flags & DIS_OCTAL;
2215 2229
2216 2230 switch (format) {
2217 2231 case IMM_ADDR:
2218 2232 if (sv < 0) {
2219 2233 sv = -sv;
2220 2234 fmtstr = (octal != 0) ? "- 0%lo" : "- 0x%lx";
2221 2235 } else {
2222 2236 fmtstr = (octal != 0) ? "+ 0%lo" : "+ 0x%lx";
2223 2237 }
2224 2238 break;
2225 2239
2226 2240 case IMM_SIGNED:
2227 2241 if (sv < 0) {
2228 2242 sv = -sv;
2229 2243 fmtstr = (octal != 0) ? "-0%lo" : "-0x%lx";
2230 2244 break;
2231 2245 }
2232 2246 /* fall through */
2233 2247
2234 2248 default:
2235 2249 fmtstr = (octal != 0) ? "0%lo" : "0x%lx";
2236 2250 }
2237 2251
2238 2252 bprintf(dhp, fmtstr, sv);
2239 2253 }
2240 2254
2241 2255 /*
2242 2256 * return the symbolic name of a register
2243 2257 * regset is one of the REG_* values indicating which type of register it is
↓ open down ↓ |
123 lines elided |
↑ open up ↑ |
2244 2258 * such as integer, floating point, etc.
2245 2259 * idx is the numeric value of the register
2246 2260 *
2247 2261 * If regset is REG_NONE, an empty, but non-NULL string is returned
2248 2262 * NULL may be returned if the index indicates an invalid register value
2249 2263 * such as with the %icc/%xcc sets
2250 2264 */
2251 2265 static const char *
2252 2266 get_regname(dis_handle_t *dhp, int regset, uint32_t idx)
2253 2267 {
2268 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2254 2269 const char *regname = NULL;
2255 2270
2256 2271 switch (regset) {
2257 2272 case REG_INT:
2258 2273 regname = reg_names[idx];
2259 2274 break;
2260 2275
2261 2276 case REG_FP:
2262 2277 regname = freg_names[idx];
2263 2278 break;
2264 2279
2265 2280 case REG_FPD:
2266 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0) ||
2281 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0) ||
2267 2282 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0))
2268 2283 regname = fdreg_names[idx];
2269 2284 else
2270 2285 regname = compat_fdreg_names[idx];
2271 2286
2272 2287 break;
2273 2288
2274 2289 case REG_FPQ:
2275 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
2290 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
2276 2291 regname = fqreg_names[idx];
2277 2292 else
2278 2293 regname = freg_names[idx];
2279 2294
2280 2295 break;
2281 2296
2282 2297 case REG_CP:
2283 2298 regname = cpreg_names[idx];
2284 2299 break;
2285 2300
2286 2301 case REG_ICC:
2287 2302 regname = icc_names[idx];
2288 2303 break;
2289 2304
2290 2305 case REG_FCC:
2291 2306 regname = fcc_names[idx];
2292 2307 break;
2293 2308
2294 2309 case REG_FSR:
2295 2310 regname = "%fsr";
2296 2311 break;
2297 2312
2298 2313 case REG_CSR:
2299 2314 regname = "%csr";
2300 2315 break;
2301 2316
2302 2317 case REG_CQ:
2303 2318 regname = "%cq";
2304 2319 break;
2305 2320
2306 2321 case REG_NONE:
2307 2322 regname = "";
2308 2323 break;
2309 2324 }
2310 2325
2311 2326 return (regname);
2312 2327 }
2313 2328
2314 2329 /*
2315 2330 * output the asi value from the instruction
2316 2331 *
2317 2332 * TODO: investigate if this should perhaps have a mask -- are undefined ASI
2318 2333 * values for an instruction still disassembled??
2319 2334 */
2320 2335 static void
2321 2336 prt_asi(dis_handle_t *dhp, uint32_t instr)
2322 2337 {
2323 2338 ifmt_t *f = (ifmt_t *)&instr;
2324 2339 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
2325 2340
2326 2341 if (f->f3.i != 0)
2327 2342 bprintf(dhp, "%%asi");
2328 2343 else
2329 2344 bprintf(dhp, (octal != 0) ? "0%03o" : "0x%02x", f->f3.asi);
2330 2345
2331 2346 }
2332 2347
2333 2348 /*
2334 2349 * put an address expression into the output buffer
2335 2350 *
2336 2351 * instr is the instruction to use
2337 2352 * if nobrackets != 0, [] are not added around the instruction
2338 2353 *
2339 2354 * Currently this option is set when printing out the address portion
2340 2355 * of a jmpl instruction, but otherwise 0 for load/stores
2341 2356 *
2342 2357 * If no debug flags are set, the full expression is output, even when
↓ open down ↓ |
57 lines elided |
↑ open up ↑ |
2343 2358 * %g0 or 0x0 appears in the address
2344 2359 *
2345 2360 * If DIS_DEBUG_SYN_ALL or DIS_DEBUG_COMPAT are set, when %g0 or 0x0
2346 2361 * appear in the address, they are not output. If the wierd (and probably
2347 2362 * shouldn't happen) address of [%g0 + %g0] or [%g0 + 0x0] is encountered,
2348 2363 * [%g0] is output
2349 2364 */
2350 2365 static void
2351 2366 prt_address(dis_handle_t *dhp, uint32_t instr, int nobrackets)
2352 2367 {
2368 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2353 2369 ifmt_t *f = (ifmt_t *)&instr;
2354 2370 int32_t simm13;
2355 2371 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
2356 - int p1 = ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2357 - int p2 = ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2372 + int p1 = ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2373 + int p2 = ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2358 2374
2359 2375 if (f->f3a.i == 0) {
2360 2376 p1 |= ((f->f3a.rs1 != 0) || f->f3.rs2 == 0);
2361 2377 p2 |= (f->f3.rs2 != 0);
2362 2378
2363 2379 bprintf(dhp, "%s%s%s%s%s",
2364 2380 (nobrackets == 0) ? "[" : "",
2365 2381 (p1 != 0) ? reg_names[f->f3a.rs1] : "",
2366 2382 (p1 != 0 && p2 != 0) ? " + " : "",
2367 2383 (p2 != 0) ? reg_names[f->f3.rs2] : "",
2368 2384 (nobrackets == 0) ? "]" : "");
2369 2385 } else {
2370 2386 const char *sign;
2371 2387
2372 2388 simm13 = sign_extend(f->f3a.simm13, 13);
2373 2389 sign = (simm13 < 0) ? "-" : "+";
2374 2390
2375 2391 p1 |= (f->f3a.rs1 != 0);
2376 2392 p2 |= (p1 == 0 || simm13 != 0);
2377 2393
2378 2394 if (p1 == 0 && simm13 == 0)
2379 2395 p2 = 1;
2380 2396
2381 2397 if (p1 == 0 && simm13 >= 0)
2382 2398 sign = "";
2383 2399
2384 2400 if (p2 != 0)
2385 2401 bprintf(dhp,
2386 2402 (octal != 0) ? "%s%s%s%s%s0%lo%s" :
2387 2403 "%s%s%s%s%s0x%lx%s",
2388 2404 (nobrackets == 0) ? "[" : "",
2389 2405 (p1 != 0) ? reg_names[f->f3a.rs1] : "",
2390 2406 (p1 != 0) ? " " : "",
2391 2407 sign,
2392 2408 (p1 != 0) ? " " : "",
2393 2409 (simm13 < 0) ? -(simm13) : simm13,
2394 2410 (nobrackets == 0) ? "]" : "");
2395 2411 else
2396 2412 bprintf(dhp, "%s%s%s",
2397 2413 (nobrackets == 0) ? "[" : "",
2398 2414 reg_names[f->f3a.rs1],
2399 2415 (nobrackets == 0) ? "]" : "");
2400 2416 }
2401 2417 }
2402 2418
2403 2419 /*
2404 2420 * print out the arguments to an alu operation (add, sub, etc.)
2405 2421 * conatined in 'instr'
2406 2422 *
2407 2423 * alu instructions have the following format:
2408 2424 * %rs1, %rs2, %rd (i == 0)
2409 2425 * %rs1, 0xnnn, %rd (i == 1)
2410 2426 * ^ ^ ^
2411 2427 * | | |
2412 2428 * p1 p2 p3
2413 2429 *
↓ open down ↓ |
46 lines elided |
↑ open up ↑ |
2414 2430 * flags indicates the register set to use for each position (p1, p2, p3)
2415 2431 * as well as if immediate values (i == 1) are allowed
2416 2432 *
2417 2433 * if flags indicates a specific position has REG_NONE set as it's register
2418 2434 * set, it is omitted from the output. This is primarly used for certain
2419 2435 * floating point operations
2420 2436 */
2421 2437 static void
2422 2438 prt_aluargs(dis_handle_t *dhp, uint32_t instr, uint32_t flags)
2423 2439 {
2440 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2424 2441 ifmt_t *f = (ifmt_t *)&instr;
2425 2442 const char *r1, *r2, *r3;
2426 2443 int p1, p2, p3;
2427 2444 unsigned int opf = 0;
2428 2445
2429 2446 r1 = get_regname(dhp, FLG_P1_VAL(flags), f->f3.rs1);
2430 2447 r2 = get_regname(dhp, FLG_P2_VAL(flags), f->f3.rs2);
2431 2448 r3 = get_regname(dhp, FLG_P3_VAL(flags), f->f3.rd);
2432 2449
2433 2450 p1 = (FLG_P1_VAL(flags) != REG_NONE);
2434 2451 p2 = (((flags & FLG_NOIMM) == 0) || (FLG_P2_VAL(flags) != REG_NONE));
2435 2452 p3 = (FLG_RD_VAL(flags) != REG_NONE);
2436 2453
2437 2454 if (r1 == NULL || r1[0] == '\0')
2438 2455 p1 = 0;
2439 2456
↓ open down ↓ |
6 lines elided |
↑ open up ↑ |
2440 2457 if (f->f3a.i == 0 && (r2 == NULL || r2[0] == '\0'))
2441 2458 p2 = 0;
2442 2459
2443 2460 if (r3 == NULL || r3[0] == '\0')
2444 2461 p3 = 0;
2445 2462
2446 2463 if ((f->fcmp.op == 2) && (f->fcmp.op3 == 0x36) && (f->fcmp.cc != 0))
2447 2464 opf = f->fcmp.opf;
2448 2465
2449 2466 if ((opf == 0x151) || (opf == 0x152)) {
2450 - (void) strlcat(dhp->dh_buf, r3, dhp->dh_buflen);
2451 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
2467 + (void) strlcat(dhx->dhx_buf, r3, dhx->dhx_buflen);
2468 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
2452 2469 p3 = 0;
2453 2470 }
2454 2471
2455 2472 if (p1 != 0) {
2456 - (void) strlcat(dhp->dh_buf, r1, dhp->dh_buflen);
2473 + (void) strlcat(dhx->dhx_buf, r1, dhx->dhx_buflen);
2457 2474 if (p2 != 0 || p3 != 0)
2458 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
2475 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
2459 2476 }
2460 2477
2461 2478 if (p2 != 0) {
2462 2479 if (f->f3.i == 0 || ((flags & FLG_NOIMM) != 0))
2463 - (void) strlcat(dhp->dh_buf, r2, dhp->dh_buflen);
2480 + (void) strlcat(dhx->dhx_buf, r2, dhx->dhx_buflen);
2464 2481 else
2465 2482 prt_imm(dhp, sign_extend(f->f3a.simm13, 13),
2466 2483 IMM_SIGNED);
2467 2484
2468 2485 if (p3 != 0)
2469 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
2486 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
2470 2487 }
2471 2488
2472 2489 if (p3 != 0)
2473 - (void) strlcat(dhp->dh_buf, r3, dhp->dh_buflen);
2490 + (void) strlcat(dhx->dhx_buf, r3, dhx->dhx_buflen);
2474 2491 }
2475 2492
2476 2493 static const char *
2477 2494 get_asi_name(uint8_t asi)
2478 2495 {
2479 2496 switch (asi) {
2480 2497 case 0x04:
2481 2498 return ("ASI_N");
2482 2499
2483 2500 case 0x0c:
2484 2501 return ("ASI_NL");
2485 2502
2486 2503 case 0x10:
2487 2504 return ("ASI_AIUP");
2488 2505
2489 2506 case 0x11:
2490 2507 return ("ASI_AIUS");
2491 2508
2492 2509 case 0x14:
2493 2510 return ("ASI_REAL");
2494 2511
2495 2512 case 0x15:
2496 2513 return ("ASI_REAL_IO");
2497 2514
2498 2515 case 0x16:
2499 2516 return ("ASI_BLK_AIUP");
2500 2517
2501 2518 case 0x17:
2502 2519 return ("ASI_BLK_AIUS");
2503 2520
2504 2521 case 0x18:
2505 2522 return ("ASI_AIUPL");
2506 2523
2507 2524 case 0x19:
2508 2525 return ("ASI_AIUSL");
2509 2526
2510 2527 case 0x1c:
2511 2528 return ("ASI_REAL_L");
2512 2529
2513 2530 case 0x1d:
2514 2531 return ("ASI_REAL_IO_L");
2515 2532
2516 2533 case 0x1e:
2517 2534 return ("ASI_BLK_AIUPL");
2518 2535
2519 2536 case 0x1f:
2520 2537 return ("ASI_BLK_AIUS_L");
2521 2538
2522 2539 case 0x20:
2523 2540 return ("ASI_SCRATCHPAD");
2524 2541
2525 2542 case 0x21:
2526 2543 return ("ASI_MMU_CONTEXTID");
2527 2544
2528 2545 case 0x22:
2529 2546 return ("ASI_TWINX_AIUP");
2530 2547
2531 2548 case 0x23:
2532 2549 return ("ASI_TWINX_AIUS");
2533 2550
2534 2551 case 0x25:
2535 2552 return ("ASI_QUEUE");
2536 2553
2537 2554 case 0x26:
2538 2555 return ("ASI_TWINX_R");
2539 2556
2540 2557 case 0x27:
2541 2558 return ("ASI_TWINX_N");
2542 2559
2543 2560 case 0x2a:
2544 2561 return ("ASI_LDTX_AIUPL");
2545 2562
2546 2563 case 0x2b:
2547 2564 return ("ASI_TWINX_AIUS_L");
2548 2565
2549 2566 case 0x2e:
2550 2567 return ("ASI_TWINX_REAL_L");
2551 2568
2552 2569 case 0x2f:
2553 2570 return ("ASI_TWINX_NL");
2554 2571
2555 2572 case 0x30:
2556 2573 return ("ASI_AIPP");
2557 2574
2558 2575 case 0x31:
2559 2576 return ("ASI_AIPS");
2560 2577
2561 2578 case 0x36:
2562 2579 return ("ASI_AIPN");
2563 2580
2564 2581 case 0x38:
2565 2582 return ("ASI_AIPP_L");
2566 2583
2567 2584 case 0x39:
2568 2585 return ("ASI_AIPS_L");
2569 2586
2570 2587 case 0x3e:
2571 2588 return ("ASI_AIPN_L");
2572 2589
2573 2590 case 0x41:
2574 2591 return ("ASI_CMT_SHARED");
2575 2592
2576 2593 case 0x4f:
2577 2594 return ("ASI_HYP_SCRATCHPAD");
2578 2595
2579 2596 case 0x50:
2580 2597 return ("ASI_IMMU");
2581 2598
2582 2599 case 0x52:
2583 2600 return ("ASI_MMU_REAL");
2584 2601
2585 2602 case 0x54:
2586 2603 return ("ASI_MMU");
2587 2604
2588 2605 case 0x55:
2589 2606 return ("ASI_ITLB_DATA_ACCESS_REG");
2590 2607
2591 2608 case 0x56:
2592 2609 return ("ASI_ITLB_TAG_READ_REG");
2593 2610
2594 2611 case 0x57:
2595 2612 return ("ASI_IMMU_DEMAP");
2596 2613
2597 2614 case 0x58:
2598 2615 return ("ASI_DMMU / ASI_UMMU");
2599 2616
2600 2617 case 0x5c:
2601 2618 return ("ASI_DTLB_DATA_IN_REG");
2602 2619
2603 2620 case 0x5d:
2604 2621 return ("ASI_DTLB_DATA_ACCESS_REG");
2605 2622
2606 2623 case 0x5e:
2607 2624 return ("ASI_DTLB_TAG_READ_REG");
2608 2625
2609 2626 case 0x5f:
2610 2627 return ("ASI_DMMU_DEMAP");
2611 2628
2612 2629 case 0x63:
2613 2630 return ("ASI_CMT_PER_STRAND / ASI_CMT_PER_CORE");
2614 2631
2615 2632 case 0x80:
2616 2633 return ("ASI_P");
2617 2634
2618 2635 case 0x81:
2619 2636 return ("ASI_S");
2620 2637
2621 2638 case 0x82:
2622 2639 return ("ASI_PNF");
2623 2640
2624 2641 case 0x83:
2625 2642 return ("ASI_SNF");
2626 2643
2627 2644 case 0x88:
2628 2645 return ("ASI_PL");
2629 2646
2630 2647 case 0x89:
2631 2648 return ("ASI_SL");
2632 2649
2633 2650 case 0x8a:
2634 2651 return ("ASI_PNFL");
2635 2652
2636 2653 case 0x8b:
2637 2654 return ("ASI_SNFL");
2638 2655
2639 2656 case 0xc0:
2640 2657 return ("ASI_PST8_P");
2641 2658
2642 2659 case 0xc1:
2643 2660 return ("ASI_PST8_S");
2644 2661
2645 2662 case 0xc2:
2646 2663 return ("ASI_PST16_P");
2647 2664
2648 2665 case 0xc3:
2649 2666 return ("ASI_PST16_S");
2650 2667
2651 2668 case 0xc4:
2652 2669 return ("ASI_PST32_P");
2653 2670
2654 2671 case 0xc5:
2655 2672 return ("ASI_PST32_S");
2656 2673
2657 2674 case 0xc8:
2658 2675 return ("ASI_PST8_PL");
2659 2676
2660 2677 case 0xc9:
2661 2678 return ("ASI_PST8_SL");
2662 2679
2663 2680 case 0xca:
2664 2681 return ("ASI_PST16_PL");
2665 2682
2666 2683 case 0xcb:
2667 2684 return ("ASI_PST16_SL");
2668 2685
2669 2686 case 0xcc:
2670 2687 return ("ASI_PST32_PL");
2671 2688
2672 2689 case 0xcd:
2673 2690 return ("ASI_PST32_SL");
2674 2691
2675 2692 case 0xd0:
2676 2693 return ("ASI_FL8_P");
2677 2694
2678 2695 case 0xd1:
2679 2696 return ("ASI_FL8_S");
2680 2697
2681 2698 case 0xd2:
2682 2699 return ("ASI_FL16_P");
2683 2700
2684 2701 case 0xd3:
2685 2702 return ("ASI_FL16_S");
2686 2703
2687 2704 case 0xd8:
2688 2705 return ("ASI_FL8_PL");
2689 2706
2690 2707 case 0xd9:
2691 2708 return ("ASI_FL8_SL");
2692 2709
2693 2710 case 0xda:
2694 2711 return ("ASI_FL16_PL");
2695 2712
2696 2713 case 0xdb:
2697 2714 return ("ASI_FL16_SL");
2698 2715
2699 2716 case 0xe0:
2700 2717 return ("ASI_BLK_COMMIT_P");
2701 2718
2702 2719 case 0xe1:
2703 2720 return ("ASI_BLK_SOMMIT_S");
2704 2721
2705 2722 case 0xe2:
2706 2723 return ("ASI_TWINX_P");
2707 2724
2708 2725 case 0xe3:
2709 2726 return ("ASI_TWINX_S");
2710 2727
2711 2728 case 0xea:
2712 2729 return ("ASI_TWINX_PL");
2713 2730
2714 2731 case 0xeb:
2715 2732 return ("ASI_TWINX_SL");
2716 2733
2717 2734 case 0xf0:
2718 2735 return ("ASI_BLK_P");
2719 2736
2720 2737 case 0xf1:
2721 2738 return ("ASI_BLK_S");
2722 2739
2723 2740 case 0xf8:
2724 2741 return ("ASI_BLK_PL");
2725 2742
2726 2743 case 0xf9:
2727 2744 return ("ASI_BLK_SL");
2728 2745
2729 2746 default:
2730 2747 return (NULL);
2731 2748 }
2732 2749 }
2733 2750
2734 2751 /*
↓ open down ↓ |
251 lines elided |
↑ open up ↑ |
2735 2752 * just a handy function that takes care of managing the buffer length
2736 2753 * w/ printf
2737 2754 */
2738 2755
2739 2756 /*
2740 2757 * PRINTF LIKE 1
2741 2758 */
2742 2759 static void
2743 2760 bprintf(dis_handle_t *dhp, const char *fmt, ...)
2744 2761 {
2762 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2745 2763 size_t curlen;
2746 2764 va_list ap;
2747 2765
2748 - curlen = strlen(dhp->dh_buf);
2766 + curlen = strlen(dhx->dhx_buf);
2749 2767
2750 2768 va_start(ap, fmt);
2751 - (void) vsnprintf(dhp->dh_buf + curlen, dhp->dh_buflen - curlen, fmt,
2752 - ap);
2769 + (void) dis_vsnprintf(dhx->dhx_buf + curlen, dhx->dhx_buflen -
2770 + curlen, fmt, ap);
2753 2771 va_end(ap);
2754 2772 }
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX