330 {
331 int cpuid = CPU->cpu_id;
332
333 return (bsrw_insn(apixs[cpuid]->x_intr_pending));
334 }
335
336 static uintptr_t
337 apix_get_intr_handler(int cpu, short vec)
338 {
339 apix_vector_t *apix_vector;
340
341 ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
342 if (cpu >= apic_nproc)
343 return (NULL);
344
345 apix_vector = apixs[cpu]->x_vectbl[vec];
346
347 return ((uintptr_t)(apix_vector->v_autovect));
348 }
349
350 #if defined(__amd64)
351 static unsigned char dummy_cpu_pri[MAXIPL + 1] = {
352 0, 0, 0, 0, 0, 0, 0, 0,
353 0, 0, 0, 0, 0, 0, 0, 0, 0
354 };
355 #endif
356
357 static void
358 apix_init()
359 {
360 extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
361
362 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
363
364 do_interrupt_common = apix_do_interrupt;
365 addintr = apix_add_avintr;
366 remintr = apix_rem_avintr;
367 get_pending_spl = apix_get_pending_spl;
368 get_intr_handler = apix_get_intr_handler;
369 psm_get_localapicid = apic_get_localapicid;
370 psm_get_ioapicid = apic_get_ioapicid;
371
372 apix_softinit();
373 #if defined(__amd64)
374 CPU->cpu_pri_data = dummy_cpu_pri;
375 #else
376 if (cpuid_have_cr8access(CPU))
377 apic_have_32bit_cr8 = 1;
378 #endif /* __amd64 */
379
380 /*
381 * Initialize IRM pool parameters
382 */
383 if (irm_enable) {
384 int i;
385 int lowest_irq;
386 int highest_irq;
387
388 /* number of CPUs present */
389 apix_irminfo.apix_ncpus = apic_nproc;
390 /* total number of entries in all of the IOAPICs present */
391 lowest_irq = apic_io_vectbase[0];
392 highest_irq = apic_io_vectend[0];
393 for (i = 1; i < apic_io_max; i++) {
394 if (apic_io_vectbase[i] < lowest_irq)
395 lowest_irq = apic_io_vectbase[i];
396 if (apic_io_vectend[i] > highest_irq)
397 highest_irq = apic_io_vectend[i];
398 }
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330 {
331 int cpuid = CPU->cpu_id;
332
333 return (bsrw_insn(apixs[cpuid]->x_intr_pending));
334 }
335
336 static uintptr_t
337 apix_get_intr_handler(int cpu, short vec)
338 {
339 apix_vector_t *apix_vector;
340
341 ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
342 if (cpu >= apic_nproc)
343 return (NULL);
344
345 apix_vector = apixs[cpu]->x_vectbl[vec];
346
347 return ((uintptr_t)(apix_vector->v_autovect));
348 }
349
350 static void
351 apix_init()
352 {
353 extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
354
355 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
356
357 do_interrupt_common = apix_do_interrupt;
358 addintr = apix_add_avintr;
359 remintr = apix_rem_avintr;
360 get_pending_spl = apix_get_pending_spl;
361 get_intr_handler = apix_get_intr_handler;
362 psm_get_localapicid = apic_get_localapicid;
363 psm_get_ioapicid = apic_get_ioapicid;
364
365 apix_softinit();
366
367 #if !defined(__amd64)
368 if (cpuid_have_cr8access(CPU))
369 apic_have_32bit_cr8 = 1;
370 #endif
371
372 /*
373 * Initialize IRM pool parameters
374 */
375 if (irm_enable) {
376 int i;
377 int lowest_irq;
378 int highest_irq;
379
380 /* number of CPUs present */
381 apix_irminfo.apix_ncpus = apic_nproc;
382 /* total number of entries in all of the IOAPICs present */
383 lowest_irq = apic_io_vectbase[0];
384 highest_irq = apic_io_vectend[0];
385 for (i = 1; i < apic_io_max; i++) {
386 if (apic_io_vectbase[i] < lowest_irq)
387 lowest_irq = apic_io_vectbase[i];
388 if (apic_io_vectend[i] > highest_irq)
389 highest_irq = apic_io_vectend[i];
390 }
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