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4664 CPU->cpu_pri_data hasn't been used for years
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--- old/usr/src/uts/i86pc/os/mlsetup.c
+++ new/usr/src/uts/i86pc/os/mlsetup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2012 Gary Mills
23 23 *
24 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 26 */
27 27 /*
28 28 * Copyright (c) 2010, Intel Corporation.
29 29 * All rights reserved.
30 30 */
31 31
32 32 #include <sys/types.h>
33 33 #include <sys/sysmacros.h>
34 34 #include <sys/disp.h>
35 35 #include <sys/promif.h>
36 36 #include <sys/clock.h>
37 37 #include <sys/cpuvar.h>
38 38 #include <sys/stack.h>
39 39 #include <vm/as.h>
40 40 #include <vm/hat.h>
41 41 #include <sys/reboot.h>
42 42 #include <sys/avintr.h>
43 43 #include <sys/vtrace.h>
44 44 #include <sys/proc.h>
45 45 #include <sys/thread.h>
46 46 #include <sys/cpupart.h>
47 47 #include <sys/pset.h>
48 48 #include <sys/copyops.h>
49 49 #include <sys/pg.h>
50 50 #include <sys/disp.h>
51 51 #include <sys/debug.h>
52 52 #include <sys/sunddi.h>
53 53 #include <sys/x86_archext.h>
54 54 #include <sys/privregs.h>
55 55 #include <sys/machsystm.h>
56 56 #include <sys/ontrap.h>
57 57 #include <sys/bootconf.h>
58 58 #include <sys/boot_console.h>
59 59 #include <sys/kdi_machimpl.h>
60 60 #include <sys/archsystm.h>
61 61 #include <sys/promif.h>
62 62 #include <sys/pci_cfgspace.h>
63 63 #ifdef __xpv
64 64 #include <sys/hypervisor.h>
65 65 #else
66 66 #include <sys/xpv_support.h>
67 67 #endif
68 68
69 69 /*
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70 70 * some globals for patching the result of cpuid
71 71 * to solve problems w/ creative cpu vendors
72 72 */
73 73
74 74 extern uint32_t cpuid_feature_ecx_include;
75 75 extern uint32_t cpuid_feature_ecx_exclude;
76 76 extern uint32_t cpuid_feature_edx_include;
77 77 extern uint32_t cpuid_feature_edx_exclude;
78 78
79 79 /*
80 - * Dummy spl priority masks
81 - */
82 -static unsigned char dummy_cpu_pri[MAXIPL + 1] = {
83 - 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
84 - 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf
85 -};
86 -
87 -/*
88 80 * Set console mode
89 81 */
90 82 static void
91 83 set_console_mode(uint8_t val)
92 84 {
93 85 struct bop_regs rp = {0};
94 86
95 87 rp.eax.byte.ah = 0x0;
96 88 rp.eax.byte.al = val;
97 89 rp.ebx.word.bx = 0x0;
98 90
99 91 BOP_DOINT(bootops, 0x10, &rp);
100 92 }
101 93
102 94
103 95 /*
104 96 * Setup routine called right before main(). Interposing this function
105 97 * before main() allows us to call it in a machine-independent fashion.
106 98 */
107 99 void
108 100 mlsetup(struct regs *rp)
109 101 {
110 102 u_longlong_t prop_value;
111 103 extern struct classfuncs sys_classfuncs;
112 104 extern disp_t cpu0_disp;
113 105 extern char t0stack[];
114 106 extern int post_fastreboot;
115 107 extern uint64_t plat_dr_options;
116 108
117 109 ASSERT_STACK_ALIGNED();
118 110
119 111 /*
120 112 * initialize cpu_self
121 113 */
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122 114 cpu[0]->cpu_self = cpu[0];
123 115
124 116 #if defined(__xpv)
125 117 /*
126 118 * Point at the hypervisor's virtual cpu structure
127 119 */
128 120 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
129 121 #endif
130 122
131 123 /*
132 - * Set up dummy cpu_pri_data values till psm spl code is
133 - * installed. This allows splx() to work on amd64.
134 - */
135 -
136 - cpu[0]->cpu_pri_data = dummy_cpu_pri;
137 -
138 - /*
139 124 * check if we've got special bits to clear or set
140 125 * when checking cpu features
141 126 */
142 127
143 128 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
144 129 cpuid_feature_ecx_include = 0;
145 130 else
146 131 cpuid_feature_ecx_include = (uint32_t)prop_value;
147 132
148 133 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
149 134 cpuid_feature_ecx_exclude = 0;
150 135 else
151 136 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
152 137
153 138 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
154 139 cpuid_feature_edx_include = 0;
155 140 else
156 141 cpuid_feature_edx_include = (uint32_t)prop_value;
157 142
158 143 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
159 144 cpuid_feature_edx_exclude = 0;
160 145 else
161 146 cpuid_feature_edx_exclude = (uint32_t)prop_value;
162 147
163 148 /*
164 149 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
165 150 */
166 151 init_desctbls();
167 152
168 153 /*
169 154 * lgrp_init() and possibly cpuid_pass1() need PCI config
170 155 * space access
171 156 */
172 157 #if defined(__xpv)
173 158 if (DOMAIN_IS_INITDOMAIN(xen_info))
174 159 pci_cfgspace_init();
175 160 #else
176 161 pci_cfgspace_init();
177 162 /*
178 163 * Initialize the platform type from CPU 0 to ensure that
179 164 * determine_platform() is only ever called once.
180 165 */
181 166 determine_platform();
182 167 #endif
183 168
184 169 /*
185 170 * The first lightweight pass (pass0) through the cpuid data
186 171 * was done in locore before mlsetup was called. Do the next
187 172 * pass in C code.
188 173 *
189 174 * The x86_featureset is initialized here based on the capabilities
190 175 * of the boot CPU. Note that if we choose to support CPUs that have
191 176 * different feature sets (at which point we would almost certainly
192 177 * want to set the feature bits to correspond to the feature
193 178 * minimum) this value may be altered.
194 179 */
195 180 cpuid_pass1(cpu[0], x86_featureset);
196 181
197 182 #if !defined(__xpv)
198 183 if ((get_hwenv() & HW_XEN_HVM) != 0)
199 184 xen_hvm_init();
200 185
201 186 /*
202 187 * Patch the tsc_read routine with appropriate set of instructions,
203 188 * depending on the processor family and architecure, to read the
204 189 * time-stamp counter while ensuring no out-of-order execution.
205 190 * Patch it while the kernel text is still writable.
206 191 *
207 192 * Note: tsc_read is not patched for intel processors whose family
208 193 * is >6 and for amd whose family >f (in case they don't support rdtscp
209 194 * instruction, unlikely). By default tsc_read will use cpuid for
210 195 * serialization in such cases. The following code needs to be
211 196 * revisited if intel processors of family >= f retains the
212 197 * instruction serialization nature of mfence instruction.
213 198 * Note: tsc_read is not patched for x86 processors which do
214 199 * not support "mfence". By default tsc_read will use cpuid for
215 200 * serialization in such cases.
216 201 *
217 202 * The Xen hypervisor does not correctly report whether rdtscp is
218 203 * supported or not, so we must assume that it is not.
219 204 */
220 205 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
221 206 is_x86_feature(x86_featureset, X86FSET_TSCP))
222 207 patch_tsc_read(X86_HAVE_TSCP);
223 208 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
224 209 cpuid_getfamily(CPU) <= 0xf &&
225 210 is_x86_feature(x86_featureset, X86FSET_SSE2))
226 211 patch_tsc_read(X86_TSC_MFENCE);
227 212 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
228 213 cpuid_getfamily(CPU) <= 6 &&
229 214 is_x86_feature(x86_featureset, X86FSET_SSE2))
230 215 patch_tsc_read(X86_TSC_LFENCE);
231 216
232 217 #endif /* !__xpv */
233 218
234 219 #if defined(__i386) && !defined(__xpv)
235 220 /*
236 221 * Some i386 processors do not implement the rdtsc instruction,
237 222 * or at least they do not implement it correctly. Patch them to
238 223 * return 0.
239 224 */
240 225 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
241 226 patch_tsc_read(X86_NO_TSC);
242 227 #endif /* __i386 && !__xpv */
243 228
244 229 #if defined(__amd64) && !defined(__xpv)
245 230 patch_memops(cpuid_getvendor(CPU));
246 231 #endif /* __amd64 && !__xpv */
247 232
248 233 #if !defined(__xpv)
249 234 /* XXPV what, if anything, should be dorked with here under xen? */
250 235
251 236 /*
252 237 * While we're thinking about the TSC, let's set up %cr4 so that
253 238 * userland can issue rdtsc, and initialize the TSC_AUX value
254 239 * (the cpuid) for the rdtscp instruction on appropriately
255 240 * capable hardware.
256 241 */
257 242 if (is_x86_feature(x86_featureset, X86FSET_TSC))
258 243 setcr4(getcr4() & ~CR4_TSD);
259 244
260 245 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
261 246 (void) wrmsr(MSR_AMD_TSCAUX, 0);
262 247
263 248 if (is_x86_feature(x86_featureset, X86FSET_DE))
264 249 setcr4(getcr4() | CR4_DE);
265 250 #endif /* __xpv */
266 251
267 252 /*
268 253 * initialize t0
269 254 */
270 255 t0.t_stk = (caddr_t)rp - MINFRAME;
271 256 t0.t_stkbase = t0stack;
272 257 t0.t_pri = maxclsyspri - 3;
273 258 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
274 259 t0.t_procp = &p0;
275 260 t0.t_plockp = &p0lock.pl_lock;
276 261 t0.t_lwp = &lwp0;
277 262 t0.t_forw = &t0;
278 263 t0.t_back = &t0;
279 264 t0.t_next = &t0;
280 265 t0.t_prev = &t0;
281 266 t0.t_cpu = cpu[0];
282 267 t0.t_disp_queue = &cpu0_disp;
283 268 t0.t_bind_cpu = PBIND_NONE;
284 269 t0.t_bind_pset = PS_NONE;
285 270 t0.t_bindflag = (uchar_t)default_binding_mode;
286 271 t0.t_cpupart = &cp_default;
287 272 t0.t_clfuncs = &sys_classfuncs.thread;
288 273 t0.t_copyops = NULL;
289 274 THREAD_ONPROC(&t0, CPU);
290 275
291 276 lwp0.lwp_thread = &t0;
292 277 lwp0.lwp_regs = (void *)rp;
293 278 lwp0.lwp_procp = &p0;
294 279 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
295 280
296 281 p0.p_exec = NULL;
297 282 p0.p_stat = SRUN;
298 283 p0.p_flag = SSYS;
299 284 p0.p_tlist = &t0;
300 285 p0.p_stksize = 2*PAGESIZE;
301 286 p0.p_stkpageszc = 0;
302 287 p0.p_as = &kas;
303 288 p0.p_lockp = &p0lock;
304 289 p0.p_brkpageszc = 0;
305 290 p0.p_t1_lgrpid = LGRP_NONE;
306 291 p0.p_tr_lgrpid = LGRP_NONE;
307 292 sigorset(&p0.p_ignore, &ignoredefault);
308 293
309 294 CPU->cpu_thread = &t0;
310 295 bzero(&cpu0_disp, sizeof (disp_t));
311 296 CPU->cpu_disp = &cpu0_disp;
312 297 CPU->cpu_disp->disp_cpu = CPU;
313 298 CPU->cpu_dispthread = &t0;
314 299 CPU->cpu_idle_thread = &t0;
315 300 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
316 301 CPU->cpu_dispatch_pri = t0.t_pri;
317 302
318 303 CPU->cpu_id = 0;
319 304
320 305 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
321 306
322 307 /*
323 308 * The kernel doesn't use LDTs unless a process explicitly requests one.
324 309 */
325 310 p0.p_ldt_desc = null_sdesc;
326 311
327 312 /*
328 313 * Initialize thread/cpu microstate accounting
329 314 */
330 315 init_mstate(&t0, LMS_SYSTEM);
331 316 init_cpu_mstate(CPU, CMS_SYSTEM);
332 317
333 318 /*
334 319 * Initialize lists of available and active CPUs.
335 320 */
336 321 cpu_list_init(CPU);
337 322
338 323 pg_cpu_bootstrap(CPU);
339 324
340 325 /*
341 326 * Now that we have taken over the GDT, IDT and have initialized
342 327 * active CPU list it's time to inform kmdb if present.
343 328 */
344 329 if (boothowto & RB_DEBUG)
345 330 kdi_idt_sync();
346 331
347 332 /*
348 333 * Explicitly set console to text mode (0x3) if this is a boot
349 334 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT.
350 335 */
351 336 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT)
352 337 set_console_mode(0x3);
353 338
354 339 /*
355 340 * If requested (boot -d) drop into kmdb.
356 341 *
357 342 * This must be done after cpu_list_init() on the 64-bit kernel
358 343 * since taking a trap requires that we re-compute gsbase based
359 344 * on the cpu list.
360 345 */
361 346 if (boothowto & RB_DEBUGENTER)
362 347 kmdb_enter();
363 348
364 349 cpu_vm_data_init(CPU);
365 350
366 351 rp->r_fp = 0; /* terminate kernel stack traces! */
367 352
368 353 prom_init("kernel", (void *)NULL);
369 354
370 355 /* User-set option overrides firmware value. */
371 356 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
372 357 plat_dr_options = (uint64_t)prop_value;
373 358 }
374 359 #if defined(__xpv)
375 360 /* No support of DR operations on xpv */
376 361 plat_dr_options = 0;
377 362 #else /* __xpv */
378 363 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
379 364 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
380 365 #ifndef __amd64
381 366 /* Only enable CPU/memory DR on 64 bits kernel. */
382 367 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
383 368 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
384 369 #endif /* __amd64 */
385 370 #endif /* __xpv */
386 371
387 372 /*
388 373 * Get value of "plat_dr_physmax" boot option.
389 374 * It overrides values calculated from MSCT or SRAT table.
390 375 */
391 376 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
392 377 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
393 378 }
394 379
395 380 /* Get value of boot_ncpus. */
396 381 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
397 382 boot_ncpus = NCPU;
398 383 } else {
399 384 boot_ncpus = (int)prop_value;
400 385 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
401 386 boot_ncpus = NCPU;
402 387 }
403 388
404 389 /*
405 390 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
406 391 * support CPU DR operations.
407 392 */
408 393 if (plat_dr_support_cpu() == 0) {
409 394 max_ncpus = boot_max_ncpus = boot_ncpus;
410 395 } else {
411 396 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
412 397 max_ncpus = NCPU;
413 398 } else {
414 399 max_ncpus = (int)prop_value;
415 400 if (max_ncpus <= 0 || max_ncpus > NCPU) {
416 401 max_ncpus = NCPU;
417 402 }
418 403 if (boot_ncpus > max_ncpus) {
419 404 boot_ncpus = max_ncpus;
420 405 }
421 406 }
422 407
423 408 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
424 409 boot_max_ncpus = boot_ncpus;
425 410 } else {
426 411 boot_max_ncpus = (int)prop_value;
427 412 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
428 413 boot_max_ncpus = boot_ncpus;
429 414 } else if (boot_max_ncpus > max_ncpus) {
430 415 boot_max_ncpus = max_ncpus;
431 416 }
432 417 }
433 418 }
434 419
435 420 /*
436 421 * Initialize the lgrp framework
437 422 */
438 423 lgrp_init(LGRP_INIT_STAGE1);
439 424
440 425 if (boothowto & RB_HALT) {
441 426 prom_printf("unix: kernel halted by -h flag\n");
442 427 prom_enter_mon();
443 428 }
444 429
445 430 ASSERT_STACK_ALIGNED();
446 431
447 432 /*
448 433 * Fill out cpu_ucode_info. Update microcode if necessary.
449 434 */
450 435 ucode_check(CPU);
451 436
452 437 if (workaround_errata(CPU) != 0)
453 438 panic("critical workaround(s) missing for boot cpu");
454 439 }
455 440
456 441
457 442 void
458 443 mach_modpath(char *path, const char *filename)
459 444 {
460 445 /*
461 446 * Construct the directory path from the filename.
462 447 */
463 448
464 449 int len;
465 450 char *p;
466 451 const char isastr[] = "/amd64";
467 452 size_t isalen = strlen(isastr);
468 453
469 454 if ((p = strrchr(filename, '/')) == NULL)
470 455 return;
471 456
472 457 while (p > filename && *(p - 1) == '/')
473 458 p--; /* remove trailing '/' characters */
474 459 if (p == filename)
475 460 p++; /* so "/" -is- the modpath in this case */
476 461
477 462 /*
478 463 * Remove optional isa-dependent directory name - the module
479 464 * subsystem will put this back again (!)
480 465 */
481 466 len = p - filename;
482 467 if (len > isalen &&
483 468 strncmp(&filename[len - isalen], isastr, isalen) == 0)
484 469 p -= isalen;
485 470
486 471 /*
487 472 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
488 473 */
489 474 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
490 475 (void) strncpy(path, filename, p - filename);
491 476 }
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