Print this page
XXXX introduce drv_sectohz
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/common/io/pciex/hotplug/pciehpc.c
+++ new/usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * This file contains Standard PCI Express HotPlug functionality that is
28 28 * compatible with the PCI Express ver 1.1 specification.
29 29 *
30 30 * NOTE: This file is compiled and delivered through misc/pcie module.
31 31 */
32 32
33 33 #include <sys/types.h>
34 34 #include <sys/note.h>
35 35 #include <sys/conf.h>
36 36 #include <sys/kmem.h>
37 37 #include <sys/debug.h>
38 38 #include <sys/vtrace.h>
39 39 #include <sys/autoconf.h>
40 40 #include <sys/varargs.h>
41 41 #include <sys/ddi_impldefs.h>
42 42 #include <sys/time.h>
43 43 #include <sys/callb.h>
44 44 #include <sys/ddi.h>
45 45 #include <sys/sunddi.h>
46 46 #include <sys/sunndi.h>
47 47 #include <sys/sysevent/dr.h>
48 48 #include <sys/pci_impl.h>
49 49 #include <sys/hotplug/pci/pcie_hp.h>
50 50 #include <sys/hotplug/pci/pciehpc.h>
51 51
52 52 typedef struct pciehpc_prop {
53 53 char *prop_name;
54 54 char *prop_value;
55 55 } pciehpc_prop_t;
56 56
57 57 static pciehpc_prop_t pciehpc_props[] = {
58 58 { PCIEHPC_PROP_LED_FAULT, PCIEHPC_PROP_VALUE_LED },
59 59 { PCIEHPC_PROP_LED_POWER, PCIEHPC_PROP_VALUE_LED },
60 60 { PCIEHPC_PROP_LED_ATTN, PCIEHPC_PROP_VALUE_LED },
61 61 { PCIEHPC_PROP_LED_ACTIVE, PCIEHPC_PROP_VALUE_LED },
62 62 { PCIEHPC_PROP_CARD_TYPE, PCIEHPC_PROP_VALUE_TYPE },
63 63 { PCIEHPC_PROP_BOARD_TYPE, PCIEHPC_PROP_VALUE_TYPE },
64 64 { PCIEHPC_PROP_SLOT_CONDITION, PCIEHPC_PROP_VALUE_TYPE }
65 65 };
66 66
67 67 /* Local functions prototype */
68 68 static int pciehpc_hpc_init(pcie_hp_ctrl_t *ctrl_p);
69 69 static int pciehpc_hpc_uninit(pcie_hp_ctrl_t *ctrl_p);
70 70 static int pciehpc_slotinfo_init(pcie_hp_ctrl_t *ctrl_p);
71 71 static int pciehpc_slotinfo_uninit(pcie_hp_ctrl_t *ctrl_p);
72 72 static int pciehpc_enable_intr(pcie_hp_ctrl_t *ctrl_p);
73 73 static int pciehpc_disable_intr(pcie_hp_ctrl_t *ctrl_p);
74 74 static pcie_hp_ctrl_t *pciehpc_create_controller(dev_info_t *dip);
75 75 static void pciehpc_destroy_controller(dev_info_t *dip);
76 76 static int pciehpc_register_slot(pcie_hp_ctrl_t *ctrl_p);
77 77 static int pciehpc_unregister_slot(pcie_hp_ctrl_t *ctrl_p);
78 78 static int pciehpc_slot_get_property(pcie_hp_slot_t *slot_p,
79 79 ddi_hp_property_t *arg, ddi_hp_property_t *rval);
80 80 static int pciehpc_slot_set_property(pcie_hp_slot_t *slot_p,
81 81 ddi_hp_property_t *arg, ddi_hp_property_t *rval);
82 82 static void pciehpc_issue_hpc_command(pcie_hp_ctrl_t *ctrl_p, uint16_t control);
83 83 static void pciehpc_attn_btn_handler(pcie_hp_ctrl_t *ctrl_p);
84 84 static pcie_hp_led_state_t pciehpc_led_state_to_hpc(uint16_t state);
85 85 static pcie_hp_led_state_t pciehpc_get_led_state(pcie_hp_ctrl_t *ctrl_p,
86 86 pcie_hp_led_t led);
87 87 static void pciehpc_set_led_state(pcie_hp_ctrl_t *ctrl_p, pcie_hp_led_t led,
88 88 pcie_hp_led_state_t state);
89 89
90 90 static int pciehpc_upgrade_slot_state(pcie_hp_slot_t *slot_p,
91 91 ddi_hp_cn_state_t target_state);
92 92 static int pciehpc_downgrade_slot_state(pcie_hp_slot_t *slot_p,
93 93 ddi_hp_cn_state_t target_state);
94 94 static int pciehpc_change_slot_state(pcie_hp_slot_t *slot_p,
95 95 ddi_hp_cn_state_t target_state);
96 96 static int
97 97 pciehpc_slot_poweron(pcie_hp_slot_t *slot_p, ddi_hp_cn_state_t *result);
98 98 static int
99 99 pciehpc_slot_poweroff(pcie_hp_slot_t *slot_p, ddi_hp_cn_state_t *result);
100 100 static int pciehpc_slot_probe(pcie_hp_slot_t *slot_p);
101 101 static int pciehpc_slot_unprobe(pcie_hp_slot_t *slot_p);
102 102 static void pciehpc_handle_power_fault(dev_info_t *dip);
103 103 static void pciehpc_power_fault_handler(void *arg);
104 104
105 105 #ifdef DEBUG
106 106 static void pciehpc_dump_hpregs(pcie_hp_ctrl_t *ctrl_p);
107 107 #endif /* DEBUG */
108 108
109 109 /*
110 110 * Global functions (called by other drivers/modules)
111 111 */
112 112
113 113 /*
114 114 * Initialize Hot Plug Controller if present. The arguments are:
115 115 * dip - Devinfo node pointer to the hot plug bus node
116 116 * regops - register ops to access HPC registers for non-standard
117 117 * HPC hw implementations (e.g: HPC in host PCI-E brdiges)
118 118 * This is NULL for standard HPC in PCIe bridges.
119 119 * Returns:
120 120 * DDI_SUCCESS for successful HPC initialization
121 121 * DDI_FAILURE for errors or if HPC hw not found
122 122 */
123 123 int
124 124 pciehpc_init(dev_info_t *dip, caddr_t arg)
125 125 {
126 126 pcie_hp_regops_t *regops = (pcie_hp_regops_t *)(void *)arg;
127 127 pcie_hp_ctrl_t *ctrl_p;
128 128
129 129 PCIE_DBG("pciehpc_init() called (dip=%p)\n", (void *)dip);
130 130
131 131 /* Make sure that it is not already initialized */
132 132 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) != NULL) {
133 133 PCIE_DBG("%s%d: pciehpc instance already initialized!\n",
134 134 ddi_driver_name(dip), ddi_get_instance(dip));
135 135 return (DDI_SUCCESS);
136 136 }
137 137
138 138 /* Allocate a new hotplug controller and slot structures */
139 139 ctrl_p = pciehpc_create_controller(dip);
140 140
141 141 /* setup access handle for HPC regs */
142 142 if (regops != NULL) {
143 143 /* HPC access is non-standard; use the supplied reg ops */
144 144 ctrl_p->hc_regops = *regops;
145 145 }
146 146
147 147 /*
148 148 * Setup resource maps for this bus node.
149 149 */
150 150 (void) pci_resource_setup(dip);
151 151
152 152 PCIE_DISABLE_ERRORS(dip);
153 153
154 154 /*
155 155 * Set the platform specific hot plug mode.
156 156 */
157 157 ctrl_p->hc_ops.init_hpc_hw = pciehpc_hpc_init;
158 158 ctrl_p->hc_ops.uninit_hpc_hw = pciehpc_hpc_uninit;
159 159 ctrl_p->hc_ops.init_hpc_slotinfo = pciehpc_slotinfo_init;
160 160 ctrl_p->hc_ops.uninit_hpc_slotinfo = pciehpc_slotinfo_uninit;
161 161 ctrl_p->hc_ops.poweron_hpc_slot = pciehpc_slot_poweron;
162 162 ctrl_p->hc_ops.poweroff_hpc_slot = pciehpc_slot_poweroff;
163 163
164 164 ctrl_p->hc_ops.enable_hpc_intr = pciehpc_enable_intr;
165 165 ctrl_p->hc_ops.disable_hpc_intr = pciehpc_disable_intr;
166 166
167 167 #if defined(__i386) || defined(__amd64)
168 168 pciehpc_update_ops(ctrl_p);
169 169 #endif
170 170
171 171 /* initialize hot plug controller hw */
172 172 if ((ctrl_p->hc_ops.init_hpc_hw)(ctrl_p) != DDI_SUCCESS)
173 173 goto cleanup1;
174 174
175 175 /* initialize slot information soft state structure */
176 176 if ((ctrl_p->hc_ops.init_hpc_slotinfo)(ctrl_p) != DDI_SUCCESS)
177 177 goto cleanup2;
178 178
179 179 /* register the hot plug slot with DDI HP framework */
180 180 if (pciehpc_register_slot(ctrl_p) != DDI_SUCCESS)
181 181 goto cleanup3;
182 182
183 183 /* create minor node for this slot */
184 184 if (pcie_create_minor_node(ctrl_p, 0) != DDI_SUCCESS)
185 185 goto cleanup4;
186 186
187 187 /* HPC initialization is complete now */
188 188 ctrl_p->hc_flags = PCIE_HP_INITIALIZED_FLAG;
189 189
190 190 #ifdef DEBUG
191 191 /* For debug, dump the HPC registers */
192 192 pciehpc_dump_hpregs(ctrl_p);
193 193 #endif /* DEBUG */
194 194
195 195 return (DDI_SUCCESS);
196 196 cleanup4:
197 197 (void) pciehpc_unregister_slot(ctrl_p);
198 198 cleanup3:
199 199 (void) (ctrl_p->hc_ops.uninit_hpc_slotinfo)(ctrl_p);
200 200
201 201 cleanup2:
202 202 (void) (ctrl_p->hc_ops.uninit_hpc_hw)(ctrl_p);
203 203
204 204 cleanup1:
205 205 PCIE_ENABLE_ERRORS(dip);
206 206 (void) pci_resource_destroy(dip);
207 207
208 208 pciehpc_destroy_controller(dip);
209 209 return (DDI_FAILURE);
210 210 }
211 211
212 212 /*
213 213 * Uninitialize HPC soft state structure and free up any resources
214 214 * used for the HPC instance.
215 215 */
216 216 int
217 217 pciehpc_uninit(dev_info_t *dip)
218 218 {
219 219 pcie_hp_ctrl_t *ctrl_p;
220 220
221 221 PCIE_DBG("pciehpc_uninit() called (dip=%p)\n", (void *)dip);
222 222
223 223 /* get the soft state structure for this dip */
224 224 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL) {
225 225 return (DDI_FAILURE);
226 226 }
227 227
228 228 pcie_remove_minor_node(ctrl_p, 0);
229 229
230 230 /* unregister the slot */
231 231 (void) pciehpc_unregister_slot(ctrl_p);
232 232
233 233 /* uninit any slot info data structures */
234 234 (void) (ctrl_p->hc_ops.uninit_hpc_slotinfo)(ctrl_p);
235 235
236 236 /* uninitialize hpc, remove interrupt handler, etc. */
237 237 (void) (ctrl_p->hc_ops.uninit_hpc_hw)(ctrl_p);
238 238
239 239 PCIE_ENABLE_ERRORS(dip);
240 240
241 241 /*
242 242 * Destroy resource maps for this bus node.
243 243 */
244 244 (void) pci_resource_destroy(dip);
245 245
246 246 /* destroy the soft state structure */
247 247 pciehpc_destroy_controller(dip);
248 248
249 249 return (DDI_SUCCESS);
250 250 }
251 251
252 252 /*
253 253 * pciehpc_intr()
254 254 *
255 255 * Interrupt handler for PCI-E Hot plug controller interrupts.
256 256 *
257 257 * Note: This is only for native mode hot plug. This is called
258 258 * by the nexus driver at interrupt context. Interrupt Service Routine
259 259 * registration is done by the nexus driver for both hot plug and
260 260 * non-hot plug interrupts. This function is called from the ISR
261 261 * of the nexus driver to handle hot-plug interrupts.
262 262 */
263 263 int
264 264 pciehpc_intr(dev_info_t *dip)
265 265 {
266 266 pcie_hp_ctrl_t *ctrl_p;
267 267 pcie_hp_slot_t *slot_p;
268 268 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
269 269 uint16_t status, control;
270 270
271 271 /* get the soft state structure for this dip */
272 272 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
273 273 return (DDI_INTR_UNCLAIMED);
274 274
275 275 mutex_enter(&ctrl_p->hc_mutex);
276 276
277 277 /* make sure the controller soft state is initialized */
278 278 if (!(ctrl_p->hc_flags & PCIE_HP_INITIALIZED_FLAG)) {
279 279 mutex_exit(&ctrl_p->hc_mutex);
280 280 return (DDI_INTR_UNCLAIMED);
281 281 }
282 282
283 283 /* if it is not NATIVE hot plug mode then return */
284 284 if (bus_p->bus_hp_curr_mode != PCIE_NATIVE_HP_MODE) {
285 285 mutex_exit(&ctrl_p->hc_mutex);
286 286 return (DDI_INTR_UNCLAIMED);
287 287 }
288 288
289 289 slot_p = ctrl_p->hc_slots[0];
290 290
291 291 /* read the current slot status register */
292 292 status = pciehpc_reg_get16(ctrl_p,
293 293 bus_p->bus_pcie_off + PCIE_SLOTSTS);
294 294
295 295 /* check if there are any hot plug interrupts occurred */
296 296 if (!(status & PCIE_SLOTSTS_STATUS_EVENTS)) {
297 297 /* no hot plug events occurred */
298 298 mutex_exit(&ctrl_p->hc_mutex);
299 299 return (DDI_INTR_UNCLAIMED);
300 300 }
301 301
302 302 /* clear the interrupt status bits */
303 303 pciehpc_reg_put16(ctrl_p,
304 304 bus_p->bus_pcie_off + PCIE_SLOTSTS, status);
305 305
306 306 /* check for CMD COMPLETE interrupt */
307 307 if (status & PCIE_SLOTSTS_COMMAND_COMPLETED) {
308 308 PCIE_DBG("pciehpc_intr(): CMD COMPLETED interrupt received\n");
309 309 /* wake up any one waiting for Command Completion event */
310 310 cv_signal(&ctrl_p->hc_cmd_comp_cv);
311 311 }
312 312
313 313 /* check for ATTN button interrupt */
314 314 if (status & PCIE_SLOTSTS_ATTN_BTN_PRESSED) {
315 315 PCIE_DBG("pciehpc_intr(): ATTN BUTTON interrupt received\n");
316 316
317 317 /* if ATTN button event is still pending then cancel it */
318 318 if (slot_p->hs_attn_btn_pending == B_TRUE)
319 319 slot_p->hs_attn_btn_pending = B_FALSE;
320 320 else
321 321 slot_p->hs_attn_btn_pending = B_TRUE;
322 322
323 323 /* wake up the ATTN event handler */
324 324 cv_signal(&slot_p->hs_attn_btn_cv);
325 325 }
326 326
327 327 /* check for power fault interrupt */
328 328 if (status & PCIE_SLOTSTS_PWR_FAULT_DETECTED) {
329 329
330 330 PCIE_DBG("pciehpc_intr(): POWER FAULT interrupt received"
331 331 " on slot %d\n", slot_p->hs_phy_slot_num);
332 332 control = pciehpc_reg_get16(ctrl_p,
333 333 bus_p->bus_pcie_off + PCIE_SLOTCTL);
334 334
335 335 if (control & PCIE_SLOTCTL_PWR_FAULT_EN) {
336 336 slot_p->hs_condition = AP_COND_FAILED;
337 337
338 338 /* disable power fault detction interrupt */
339 339 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
340 340 PCIE_SLOTCTL, control & ~PCIE_SLOTCTL_PWR_FAULT_EN);
341 341
342 342 pciehpc_handle_power_fault(dip);
343 343 }
344 344 }
345 345
346 346 /* check for MRL SENSOR CHANGED interrupt */
347 347 if (status & PCIE_SLOTSTS_MRL_SENSOR_CHANGED) {
348 348 /* For now (phase-I), no action is taken on this event */
349 349 PCIE_DBG("pciehpc_intr(): MRL SENSOR CHANGED interrupt received"
350 350 " on slot %d\n", slot_p->hs_phy_slot_num);
351 351 }
352 352
353 353 /* check for PRESENCE CHANGED interrupt */
354 354 if (status & PCIE_SLOTSTS_PRESENCE_CHANGED) {
355 355
356 356 PCIE_DBG("pciehpc_intr(): PRESENCE CHANGED interrupt received"
357 357 " on slot %d\n", slot_p->hs_phy_slot_num);
358 358
359 359 if (status & PCIE_SLOTSTS_PRESENCE_DETECTED) {
360 360 /*
361 361 * card is inserted into the slot, ask DDI Hotplug
362 362 * framework to change state to Present.
363 363 */
364 364 cmn_err(CE_NOTE, "pciehpc (%s%d): card is inserted"
365 365 " in the slot %s",
366 366 ddi_driver_name(dip),
367 367 ddi_get_instance(dip),
368 368 slot_p->hs_info.cn_name);
369 369
370 370 (void) ndi_hp_state_change_req(dip,
371 371 slot_p->hs_info.cn_name,
372 372 DDI_HP_CN_STATE_PRESENT,
373 373 DDI_HP_REQ_ASYNC);
374 374 } else { /* card is removed from the slot */
375 375 cmn_err(CE_NOTE, "pciehpc (%s%d): card is removed"
376 376 " from the slot %s",
377 377 ddi_driver_name(dip),
378 378 ddi_get_instance(dip),
379 379 slot_p->hs_info.cn_name);
380 380
381 381 if (slot_p->hs_info.cn_state ==
382 382 DDI_HP_CN_STATE_ENABLED) {
383 383 /* Card is removed when slot is enabled */
384 384 slot_p->hs_condition = AP_COND_FAILED;
385 385 } else {
386 386 slot_p->hs_condition = AP_COND_UNKNOWN;
387 387 }
388 388 /* make sure to disable power fault detction intr */
389 389 control = pciehpc_reg_get16(ctrl_p,
390 390 bus_p->bus_pcie_off + PCIE_SLOTCTL);
391 391
392 392 if (control & PCIE_SLOTCTL_PWR_FAULT_EN)
393 393 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
394 394 PCIE_SLOTCTL,
395 395 control & ~PCIE_SLOTCTL_PWR_FAULT_EN);
396 396
397 397 /*
398 398 * Ask DDI Hotplug framework to change state to Empty
399 399 */
400 400 (void) ndi_hp_state_change_req(dip,
401 401 slot_p->hs_info.cn_name,
402 402 DDI_HP_CN_STATE_EMPTY,
403 403 DDI_HP_REQ_ASYNC);
404 404 }
405 405 }
406 406
407 407 /* check for DLL state changed interrupt */
408 408 if (ctrl_p->hc_dll_active_rep &&
409 409 (status & PCIE_SLOTSTS_DLL_STATE_CHANGED)) {
410 410 PCIE_DBG("pciehpc_intr(): DLL STATE CHANGED interrupt received"
411 411 " on slot %d\n", slot_p->hs_phy_slot_num);
412 412
413 413 cv_signal(&slot_p->hs_dll_active_cv);
414 414 }
415 415
416 416 mutex_exit(&ctrl_p->hc_mutex);
417 417
418 418 return (DDI_INTR_CLAIMED);
419 419 }
420 420
421 421 /*
422 422 * Handle hotplug commands
423 423 *
424 424 * Note: This function is called by DDI HP framework at kernel context only
425 425 */
426 426 /* ARGSUSED */
427 427 int
428 428 pciehpc_hp_ops(dev_info_t *dip, char *cn_name, ddi_hp_op_t op,
429 429 void *arg, void *result)
430 430 {
431 431 pcie_hp_ctrl_t *ctrl_p;
432 432 pcie_hp_slot_t *slot_p;
433 433 int ret = DDI_SUCCESS;
434 434
435 435 PCIE_DBG("pciehpc_hp_ops: dip=%p cn_name=%s op=%x arg=%p\n",
436 436 dip, cn_name, op, arg);
437 437
438 438 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
439 439 return (DDI_FAILURE);
440 440
441 441 slot_p = ctrl_p->hc_slots[0];
442 442
443 443 if (strcmp(cn_name, slot_p->hs_info.cn_name) != 0)
444 444 return (DDI_EINVAL);
445 445
446 446 switch (op) {
447 447 case DDI_HPOP_CN_GET_STATE:
448 448 {
449 449 mutex_enter(&slot_p->hs_ctrl->hc_mutex);
450 450
451 451 /* get the current slot state */
452 452 pciehpc_get_slot_state(slot_p);
453 453
454 454 *((ddi_hp_cn_state_t *)result) = slot_p->hs_info.cn_state;
455 455
456 456 mutex_exit(&slot_p->hs_ctrl->hc_mutex);
457 457 break;
458 458 }
459 459 case DDI_HPOP_CN_CHANGE_STATE:
460 460 {
461 461 ddi_hp_cn_state_t target_state = *(ddi_hp_cn_state_t *)arg;
462 462
463 463 mutex_enter(&slot_p->hs_ctrl->hc_mutex);
464 464
465 465 ret = pciehpc_change_slot_state(slot_p, target_state);
466 466 *(ddi_hp_cn_state_t *)result = slot_p->hs_info.cn_state;
467 467
468 468 mutex_exit(&slot_p->hs_ctrl->hc_mutex);
469 469 break;
470 470 }
471 471 case DDI_HPOP_CN_PROBE:
472 472
473 473 ret = pciehpc_slot_probe(slot_p);
474 474
475 475 break;
476 476 case DDI_HPOP_CN_UNPROBE:
477 477 ret = pciehpc_slot_unprobe(slot_p);
478 478
479 479 break;
480 480 case DDI_HPOP_CN_GET_PROPERTY:
481 481 ret = pciehpc_slot_get_property(slot_p,
482 482 (ddi_hp_property_t *)arg, (ddi_hp_property_t *)result);
483 483 break;
484 484 case DDI_HPOP_CN_SET_PROPERTY:
485 485 ret = pciehpc_slot_set_property(slot_p,
486 486 (ddi_hp_property_t *)arg, (ddi_hp_property_t *)result);
487 487 break;
488 488 default:
489 489 ret = DDI_ENOTSUP;
490 490 break;
491 491 }
492 492
493 493 return (ret);
494 494 }
495 495
496 496 /*
497 497 * Get the current state of the slot from the hw.
498 498 *
499 499 * The slot state should have been initialized before this function gets called.
500 500 */
501 501 void
502 502 pciehpc_get_slot_state(pcie_hp_slot_t *slot_p)
503 503 {
504 504 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
505 505 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
506 506 uint16_t control, status;
507 507 ddi_hp_cn_state_t curr_state = slot_p->hs_info.cn_state;
508 508
509 509 /* read the Slot Control Register */
510 510 control = pciehpc_reg_get16(ctrl_p,
511 511 bus_p->bus_pcie_off + PCIE_SLOTCTL);
512 512
513 513 slot_p->hs_fault_led_state = PCIE_HP_LED_OFF; /* no fault led */
514 514 slot_p->hs_active_led_state = PCIE_HP_LED_OFF; /* no active led */
515 515
516 516 /* read the current Slot Status Register */
517 517 status = pciehpc_reg_get16(ctrl_p,
518 518 bus_p->bus_pcie_off + PCIE_SLOTSTS);
519 519
520 520 /* get POWER led state */
521 521 slot_p->hs_power_led_state =
522 522 pciehpc_led_state_to_hpc(pcie_slotctl_pwr_indicator_get(control));
523 523
524 524 /* get ATTN led state */
525 525 slot_p->hs_attn_led_state =
526 526 pciehpc_led_state_to_hpc(pcie_slotctl_attn_indicator_get(control));
527 527
528 528 if (!(status & PCIE_SLOTSTS_PRESENCE_DETECTED)) {
529 529 /* no device present; slot is empty */
530 530 slot_p->hs_info.cn_state = DDI_HP_CN_STATE_EMPTY;
531 531
532 532 return;
533 533 }
534 534
535 535 /* device is present */
536 536 slot_p->hs_info.cn_state = DDI_HP_CN_STATE_PRESENT;
537 537
538 538 if (!(control & PCIE_SLOTCTL_PWR_CONTROL)) {
539 539 /*
540 540 * Device is powered on. Set to "ENABLED" state (skip
541 541 * POWERED state) because there is not a explicit "enable"
542 542 * action exists for PCIe.
543 543 * If it is already in "POWERED" state, then keep it until
544 544 * user explicitly change it to other states.
545 545 */
546 546 if (curr_state == DDI_HP_CN_STATE_POWERED) {
547 547 slot_p->hs_info.cn_state = curr_state;
548 548 } else {
549 549 slot_p->hs_info.cn_state = DDI_HP_CN_STATE_ENABLED;
550 550 }
551 551 }
552 552 }
553 553
554 554 /*
555 555 * setup slot name/slot-number info.
556 556 */
557 557 void
558 558 pciehpc_set_slot_name(pcie_hp_ctrl_t *ctrl_p)
559 559 {
560 560 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
561 561 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
562 562 uchar_t *slotname_data;
563 563 int *slotnum;
564 564 uint_t count;
565 565 int len;
566 566 int invalid_slotnum = 0;
567 567 uint32_t slot_capabilities;
568 568
569 569 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, ctrl_p->hc_dip,
570 570 DDI_PROP_DONTPASS, "physical-slot#", &slotnum, &count) ==
571 571 DDI_PROP_SUCCESS) {
572 572 slot_p->hs_phy_slot_num = slotnum[0];
573 573 ddi_prop_free(slotnum);
574 574 } else {
575 575 slot_capabilities = pciehpc_reg_get32(ctrl_p,
576 576 bus_p->bus_pcie_off + PCIE_SLOTCAP);
577 577 slot_p->hs_phy_slot_num =
578 578 PCIE_SLOTCAP_PHY_SLOT_NUM(slot_capabilities);
579 579 }
580 580
581 581 /* platform may not have initialized it */
582 582 if (!slot_p->hs_phy_slot_num) {
583 583 PCIE_DBG("%s#%d: Invalid slot number!\n",
584 584 ddi_driver_name(ctrl_p->hc_dip),
585 585 ddi_get_instance(ctrl_p->hc_dip));
586 586 slot_p->hs_phy_slot_num = pciehpc_reg_get8(ctrl_p,
587 587 PCI_BCNF_SECBUS);
588 588 invalid_slotnum = 1;
589 589 }
590 590 slot_p->hs_info.cn_num = slot_p->hs_phy_slot_num;
591 591 slot_p->hs_info.cn_num_dpd_on = DDI_HP_CN_NUM_NONE;
592 592
593 593 /*
594 594 * construct the slot_name:
595 595 * if "slot-names" property exists then use that name
596 596 * else if valid slot number exists then it is "pcie<slot-num>".
597 597 * else it will be "pcie<sec-bus-number>dev0"
598 598 */
599 599 if (ddi_getlongprop(DDI_DEV_T_ANY, ctrl_p->hc_dip, DDI_PROP_DONTPASS,
600 600 "slot-names", (caddr_t)&slotname_data, &len) == DDI_PROP_SUCCESS) {
601 601 char tmp_name[256];
602 602
603 603 /*
604 604 * Note: for PCI-E slots, the device number is always 0 so the
605 605 * first (and only) string is the slot name for this slot.
606 606 */
607 607 (void) snprintf(tmp_name, sizeof (tmp_name),
608 608 (char *)slotname_data + 4);
609 609 slot_p->hs_info.cn_name = ddi_strdup(tmp_name, KM_SLEEP);
610 610 kmem_free(slotname_data, len);
611 611 } else {
612 612 if (invalid_slotnum) {
613 613 /* use device number ie. 0 */
614 614 slot_p->hs_info.cn_name = ddi_strdup("pcie0",
615 615 KM_SLEEP);
616 616 } else {
617 617 char tmp_name[256];
618 618
619 619 (void) snprintf(tmp_name, sizeof (tmp_name), "pcie%d",
620 620 slot_p->hs_phy_slot_num);
621 621 slot_p->hs_info.cn_name = ddi_strdup(tmp_name,
622 622 KM_SLEEP);
623 623 }
624 624 }
625 625 }
626 626
627 627 /*
628 628 * Read/Write access to HPC registers. If platform nexus has non-standard
629 629 * HPC access mechanism then regops functions are used to do reads/writes.
630 630 */
631 631 uint8_t
632 632 pciehpc_reg_get8(pcie_hp_ctrl_t *ctrl_p, uint_t off)
633 633 {
634 634 if (ctrl_p->hc_regops.get != NULL) {
635 635 return ((uint8_t)ctrl_p->hc_regops.get(
636 636 ctrl_p->hc_regops.cookie, (off_t)off));
637 637 } else {
638 638 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
639 639
640 640 return (pci_config_get8(bus_p->bus_cfg_hdl, off));
641 641 }
642 642 }
643 643
644 644 uint16_t
645 645 pciehpc_reg_get16(pcie_hp_ctrl_t *ctrl_p, uint_t off)
646 646 {
647 647 if (ctrl_p->hc_regops.get != NULL) {
648 648 return ((uint16_t)ctrl_p->hc_regops.get(
649 649 ctrl_p->hc_regops.cookie, (off_t)off));
650 650 } else {
651 651 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
652 652
653 653 return (pci_config_get16(bus_p->bus_cfg_hdl, off));
654 654 }
655 655 }
656 656
657 657 uint32_t
658 658 pciehpc_reg_get32(pcie_hp_ctrl_t *ctrl_p, uint_t off)
659 659 {
660 660 if (ctrl_p->hc_regops.get != NULL) {
661 661 return ((uint32_t)ctrl_p->hc_regops.get(
662 662 ctrl_p->hc_regops.cookie, (off_t)off));
663 663 } else {
664 664 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
665 665
666 666 return (pci_config_get32(bus_p->bus_cfg_hdl, off));
667 667 }
668 668 }
669 669
670 670 void
671 671 pciehpc_reg_put8(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint8_t val)
672 672 {
673 673 if (ctrl_p->hc_regops.put != NULL) {
674 674 ctrl_p->hc_regops.put(ctrl_p->hc_regops.cookie,
675 675 (off_t)off, (uint_t)val);
676 676 } else {
677 677 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
678 678
679 679 pci_config_put8(bus_p->bus_cfg_hdl, off, val);
680 680 }
681 681 }
682 682
683 683 void
684 684 pciehpc_reg_put16(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint16_t val)
685 685 {
686 686 if (ctrl_p->hc_regops.put != NULL) {
687 687 ctrl_p->hc_regops.put(ctrl_p->hc_regops.cookie,
688 688 (off_t)off, (uint_t)val);
689 689 } else {
690 690 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
691 691
692 692 pci_config_put16(bus_p->bus_cfg_hdl, off, val);
693 693 }
694 694 }
695 695
696 696 void
697 697 pciehpc_reg_put32(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint32_t val)
698 698 {
699 699 if (ctrl_p->hc_regops.put != NULL) {
700 700 ctrl_p->hc_regops.put(ctrl_p->hc_regops.cookie,
701 701 (off_t)off, (uint_t)val);
702 702 } else {
703 703 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
704 704
705 705 pci_config_put32(bus_p->bus_cfg_hdl, off, val);
706 706 }
707 707 }
708 708
709 709 /*
710 710 * ************************************************************************
711 711 * *** Local functions (called within this file)
712 712 * *** PCIe Native Hotplug mode specific functions
713 713 * ************************************************************************
714 714 */
715 715
716 716 /*
717 717 * Initialize HPC hardware, install interrupt handler, etc. It doesn't
718 718 * enable hot plug interrupts.
719 719 *
720 720 * (Note: It is called only from pciehpc_init().)
721 721 */
722 722 static int
723 723 pciehpc_hpc_init(pcie_hp_ctrl_t *ctrl_p)
724 724 {
725 725 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
726 726 uint16_t reg;
727 727
728 728 /* read the Slot Control Register */
729 729 reg = pciehpc_reg_get16(ctrl_p,
730 730 bus_p->bus_pcie_off + PCIE_SLOTCTL);
731 731
732 732 /* disable all interrupts */
733 733 reg &= ~(PCIE_SLOTCTL_INTR_MASK);
734 734 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
735 735 PCIE_SLOTCTL, reg);
736 736
737 737 /* clear any interrupt status bits */
738 738 reg = pciehpc_reg_get16(ctrl_p,
739 739 bus_p->bus_pcie_off + PCIE_SLOTSTS);
740 740 pciehpc_reg_put16(ctrl_p,
741 741 bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
742 742
743 743 return (DDI_SUCCESS);
744 744 }
745 745
746 746 /*
747 747 * Uninitialize HPC hardware, uninstall interrupt handler, etc.
748 748 *
749 749 * (Note: It is called only from pciehpc_uninit().)
750 750 */
751 751 static int
752 752 pciehpc_hpc_uninit(pcie_hp_ctrl_t *ctrl_p)
753 753 {
754 754 /* disable interrupts */
755 755 (void) pciehpc_disable_intr(ctrl_p);
756 756
757 757 return (DDI_SUCCESS);
758 758 }
759 759
760 760 /*
761 761 * Setup slot information for use with DDI HP framework.
762 762 */
763 763 static int
764 764 pciehpc_slotinfo_init(pcie_hp_ctrl_t *ctrl_p)
765 765 {
766 766 uint32_t slot_capabilities, link_capabilities;
767 767 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
768 768 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
769 769
770 770 mutex_enter(&ctrl_p->hc_mutex);
771 771 /*
772 772 * setup DDI HP framework slot information structure
773 773 */
774 774 slot_p->hs_device_num = 0;
775 775
776 776 slot_p->hs_info.cn_type = DDI_HP_CN_TYPE_PCIE;
777 777 slot_p->hs_info.cn_type_str = (ctrl_p->hc_regops.get == NULL) ?
778 778 PCIE_NATIVE_HP_TYPE : PCIE_PROP_HP_TYPE;
779 779 slot_p->hs_info.cn_child = NULL;
780 780
781 781 slot_p->hs_minor =
782 782 PCI_MINOR_NUM(ddi_get_instance(ctrl_p->hc_dip),
783 783 slot_p->hs_device_num);
784 784 slot_p->hs_condition = AP_COND_UNKNOWN;
785 785
786 786 /* read Slot Capabilities Register */
787 787 slot_capabilities = pciehpc_reg_get32(ctrl_p,
788 788 bus_p->bus_pcie_off + PCIE_SLOTCAP);
789 789
790 790 /* set slot-name/slot-number info */
791 791 pciehpc_set_slot_name(ctrl_p);
792 792
793 793 /* check if Attn Button present */
794 794 ctrl_p->hc_has_attn = (slot_capabilities & PCIE_SLOTCAP_ATTN_BUTTON) ?
795 795 B_TRUE : B_FALSE;
796 796
797 797 /* check if Manual Retention Latch sensor present */
798 798 ctrl_p->hc_has_mrl = (slot_capabilities & PCIE_SLOTCAP_MRL_SENSOR) ?
799 799 B_TRUE : B_FALSE;
800 800
801 801 /*
802 802 * PCI-E version 1.1 defines EMI Lock Present bit
803 803 * in Slot Capabilities register. Check for it.
804 804 */
805 805 ctrl_p->hc_has_emi_lock = (slot_capabilities &
806 806 PCIE_SLOTCAP_EMI_LOCK_PRESENT) ? B_TRUE : B_FALSE;
807 807
808 808 link_capabilities = pciehpc_reg_get32(ctrl_p,
809 809 bus_p->bus_pcie_off + PCIE_LINKCAP);
810 810 ctrl_p->hc_dll_active_rep = (link_capabilities &
811 811 PCIE_LINKCAP_DLL_ACTIVE_REP_CAPABLE) ? B_TRUE : B_FALSE;
812 812 if (ctrl_p->hc_dll_active_rep)
813 813 cv_init(&slot_p->hs_dll_active_cv, NULL, CV_DRIVER, NULL);
814 814
815 815 /* setup thread for handling ATTN button events */
816 816 if (ctrl_p->hc_has_attn) {
817 817 PCIE_DBG("pciehpc_slotinfo_init: setting up ATTN button event "
818 818 "handler thread for slot %d\n", slot_p->hs_phy_slot_num);
819 819
820 820 cv_init(&slot_p->hs_attn_btn_cv, NULL, CV_DRIVER, NULL);
821 821 slot_p->hs_attn_btn_pending = B_FALSE;
822 822 slot_p->hs_attn_btn_threadp = thread_create(NULL, 0,
823 823 pciehpc_attn_btn_handler,
824 824 (void *)ctrl_p, 0, &p0, TS_RUN, minclsyspri);
825 825 slot_p->hs_attn_btn_thread_exit = B_FALSE;
826 826 }
827 827
828 828 /* get current slot state from the hw */
829 829 slot_p->hs_info.cn_state = DDI_HP_CN_STATE_EMPTY;
830 830 pciehpc_get_slot_state(slot_p);
831 831 if (slot_p->hs_info.cn_state >= DDI_HP_CN_STATE_ENABLED)
832 832 slot_p->hs_condition = AP_COND_OK;
833 833
834 834 mutex_exit(&ctrl_p->hc_mutex);
835 835
836 836 return (DDI_SUCCESS);
837 837 }
838 838
839 839 /*ARGSUSED*/
840 840 static int
841 841 pciehpc_slotinfo_uninit(pcie_hp_ctrl_t *ctrl_p)
842 842 {
843 843 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
844 844
845 845 if (slot_p->hs_attn_btn_threadp != NULL) {
846 846 mutex_enter(&ctrl_p->hc_mutex);
847 847 slot_p->hs_attn_btn_thread_exit = B_TRUE;
848 848 cv_signal(&slot_p->hs_attn_btn_cv);
849 849 PCIE_DBG("pciehpc_slotinfo_uninit: "
850 850 "waiting for ATTN thread exit\n");
851 851 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
852 852 PCIE_DBG("pciehpc_slotinfo_uninit: ATTN thread exit\n");
853 853 cv_destroy(&slot_p->hs_attn_btn_cv);
854 854 slot_p->hs_attn_btn_threadp = NULL;
855 855 mutex_exit(&ctrl_p->hc_mutex);
856 856 }
857 857
858 858 if (ctrl_p->hc_dll_active_rep)
859 859 cv_destroy(&slot_p->hs_dll_active_cv);
860 860 if (slot_p->hs_info.cn_name)
861 861 kmem_free(slot_p->hs_info.cn_name,
862 862 strlen(slot_p->hs_info.cn_name) + 1);
863 863
864 864 return (DDI_SUCCESS);
865 865 }
866 866
867 867 /*
868 868 * Enable hot plug interrupts.
869 869 * Note: this is only for Native hot plug mode.
870 870 */
871 871 static int
872 872 pciehpc_enable_intr(pcie_hp_ctrl_t *ctrl_p)
873 873 {
874 874 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
875 875 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
876 876 uint16_t reg;
877 877
878 878 /* clear any interrupt status bits */
879 879 reg = pciehpc_reg_get16(ctrl_p,
880 880 bus_p->bus_pcie_off + PCIE_SLOTSTS);
881 881 pciehpc_reg_put16(ctrl_p,
882 882 bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
883 883
884 884 /* read the Slot Control Register */
885 885 reg = pciehpc_reg_get16(ctrl_p,
886 886 bus_p->bus_pcie_off + PCIE_SLOTCTL);
887 887
888 888 /*
889 889 * enable interrupts: power fault detection interrupt is enabled
890 890 * only when the slot is powered ON
891 891 */
892 892 if (slot_p->hs_info.cn_state >= DDI_HP_CN_STATE_POWERED)
893 893 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
894 894 PCIE_SLOTCTL, reg | PCIE_SLOTCTL_INTR_MASK);
895 895 else
896 896 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
897 897 PCIE_SLOTCTL, reg | (PCIE_SLOTCTL_INTR_MASK &
898 898 ~PCIE_SLOTCTL_PWR_FAULT_EN));
899 899
900 900 return (DDI_SUCCESS);
901 901 }
902 902
903 903 /*
904 904 * Disable hot plug interrupts.
905 905 * Note: this is only for Native hot plug mode.
906 906 */
907 907 static int
908 908 pciehpc_disable_intr(pcie_hp_ctrl_t *ctrl_p)
909 909 {
910 910 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
911 911 uint16_t reg;
912 912
913 913 /* read the Slot Control Register */
914 914 reg = pciehpc_reg_get16(ctrl_p,
915 915 bus_p->bus_pcie_off + PCIE_SLOTCTL);
916 916
917 917 /* disable all interrupts */
918 918 reg &= ~(PCIE_SLOTCTL_INTR_MASK);
919 919 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + PCIE_SLOTCTL, reg);
920 920
921 921 /* clear any interrupt status bits */
922 922 reg = pciehpc_reg_get16(ctrl_p,
923 923 bus_p->bus_pcie_off + PCIE_SLOTSTS);
924 924 pciehpc_reg_put16(ctrl_p,
925 925 bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
926 926
927 927 return (DDI_SUCCESS);
928 928 }
929 929
930 930 /*
931 931 * Allocate a new hotplug controller and slot structures for HPC
932 932 * associated with this dip.
933 933 */
934 934 static pcie_hp_ctrl_t *
935 935 pciehpc_create_controller(dev_info_t *dip)
936 936 {
937 937 pcie_hp_ctrl_t *ctrl_p;
938 938 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
939 939
940 940 ctrl_p = kmem_zalloc(sizeof (pcie_hp_ctrl_t), KM_SLEEP);
941 941 ctrl_p->hc_dip = dip;
942 942
943 943 /* Allocate a new slot structure. */
944 944 ctrl_p->hc_slots[0] = kmem_zalloc(sizeof (pcie_hp_slot_t), KM_SLEEP);
945 945 ctrl_p->hc_slots[0]->hs_num = 0;
946 946 ctrl_p->hc_slots[0]->hs_ctrl = ctrl_p;
947 947
948 948 /* Initialize the interrupt mutex */
949 949 mutex_init(&ctrl_p->hc_mutex, NULL, MUTEX_DRIVER,
950 950 (void *)PCIE_INTR_PRI);
951 951
952 952 /* Initialize synchronization conditional variable */
953 953 cv_init(&ctrl_p->hc_cmd_comp_cv, NULL, CV_DRIVER, NULL);
954 954 ctrl_p->hc_cmd_pending = B_FALSE;
955 955
956 956 bus_p->bus_hp_curr_mode = PCIE_NATIVE_HP_MODE;
957 957 PCIE_SET_HP_CTRL(dip, ctrl_p);
958 958
959 959 return (ctrl_p);
960 960 }
961 961
962 962 /*
963 963 * Remove the HPC controller and slot structures
964 964 */
965 965 static void
966 966 pciehpc_destroy_controller(dev_info_t *dip)
967 967 {
968 968 pcie_hp_ctrl_t *ctrl_p;
969 969 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
970 970
971 971 /* get the soft state structure for this dip */
972 972 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
973 973 return;
974 974
975 975 PCIE_SET_HP_CTRL(dip, NULL);
976 976 bus_p->bus_hp_curr_mode = PCIE_NONE_HP_MODE;
977 977
978 978 mutex_destroy(&ctrl_p->hc_mutex);
979 979 cv_destroy(&ctrl_p->hc_cmd_comp_cv);
980 980 kmem_free(ctrl_p->hc_slots[0], sizeof (pcie_hp_slot_t));
981 981 kmem_free(ctrl_p, sizeof (pcie_hp_ctrl_t));
982 982 }
983 983
984 984 /*
985 985 * Register the PCI-E hot plug slot with DDI HP framework.
986 986 */
987 987 static int
988 988 pciehpc_register_slot(pcie_hp_ctrl_t *ctrl_p)
989 989 {
990 990 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
991 991 dev_info_t *dip = ctrl_p->hc_dip;
992 992
993 993 /* register the slot with DDI HP framework */
994 994 if (ndi_hp_register(dip, &slot_p->hs_info) != NDI_SUCCESS) {
995 995 PCIE_DBG("pciehpc_register_slot() failed to register slot %d\n",
996 996 slot_p->hs_phy_slot_num);
997 997 return (DDI_FAILURE);
998 998 }
999 999
1000 1000 pcie_hp_create_occupant_props(dip, makedevice(ddi_driver_major(dip),
1001 1001 slot_p->hs_minor), slot_p->hs_device_num);
1002 1002
1003 1003 PCIE_DBG("pciehpc_register_slot(): registered slot %d\n",
1004 1004 slot_p->hs_phy_slot_num);
1005 1005
1006 1006 return (DDI_SUCCESS);
1007 1007 }
1008 1008
1009 1009 /*
1010 1010 * Unregister the PCI-E hot plug slot from DDI HP framework.
1011 1011 */
1012 1012 static int
1013 1013 pciehpc_unregister_slot(pcie_hp_ctrl_t *ctrl_p)
1014 1014 {
1015 1015 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
1016 1016 dev_info_t *dip = ctrl_p->hc_dip;
1017 1017
1018 1018 pcie_hp_delete_occupant_props(dip, makedevice(ddi_driver_major(dip),
1019 1019 slot_p->hs_minor));
1020 1020
1021 1021 /* unregister the slot with DDI HP framework */
1022 1022 if (ndi_hp_unregister(dip, slot_p->hs_info.cn_name) != NDI_SUCCESS) {
1023 1023 PCIE_DBG("pciehpc_unregister_slot() "
1024 1024 "failed to unregister slot %d\n", slot_p->hs_phy_slot_num);
1025 1025 return (DDI_FAILURE);
1026 1026 }
1027 1027
1028 1028 PCIE_DBG("pciehpc_unregister_slot(): unregistered slot %d\n",
1029 1029 slot_p->hs_phy_slot_num);
1030 1030
1031 1031 return (DDI_SUCCESS);
1032 1032 }
1033 1033
1034 1034 /*
1035 1035 * pciehpc_slot_poweron()
1036 1036 *
1037 1037 * Poweron/Enable the slot.
1038 1038 *
1039 1039 * Note: This function is called by DDI HP framework at kernel context only
1040 1040 */
1041 1041 /*ARGSUSED*/
1042 1042 static int
1043 1043 pciehpc_slot_poweron(pcie_hp_slot_t *slot_p, ddi_hp_cn_state_t *result)
1044 1044 {
1045 1045 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1046 1046 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1047 1047 uint16_t status, control;
1048 1048
1049 1049 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1050 1050
1051 1051 /* get the current state of the slot */
1052 1052 pciehpc_get_slot_state(slot_p);
1053 1053
1054 1054 /* check if the slot is already in the 'enabled' state */
1055 1055 if (slot_p->hs_info.cn_state >= DDI_HP_CN_STATE_POWERED) {
1056 1056 /* slot is already in the 'enabled' state */
1057 1057 PCIE_DBG("pciehpc_slot_poweron() slot %d already enabled\n",
1058 1058 slot_p->hs_phy_slot_num);
1059 1059
1060 1060 *result = slot_p->hs_info.cn_state;
1061 1061 return (DDI_SUCCESS);
1062 1062 }
1063 1063
1064 1064 /* read the Slot Status Register */
1065 1065 status = pciehpc_reg_get16(ctrl_p,
1066 1066 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1067 1067
1068 1068 /* make sure the MRL switch is closed if present */
1069 1069 if ((ctrl_p->hc_has_mrl) && (status & PCIE_SLOTSTS_MRL_SENSOR_OPEN)) {
1070 1070 /* MRL switch is open */
1071 1071 cmn_err(CE_WARN, "MRL switch is open on slot %d\n",
1072 1072 slot_p->hs_phy_slot_num);
1073 1073 goto cleanup;
1074 1074 }
1075 1075
1076 1076 /* make sure the slot has a device present */
1077 1077 if (!(status & PCIE_SLOTSTS_PRESENCE_DETECTED)) {
1078 1078 /* slot is empty */
1079 1079 PCIE_DBG("slot %d is empty\n", slot_p->hs_phy_slot_num);
1080 1080 goto cleanup;
1081 1081 }
1082 1082
1083 1083 /* get the current state of Slot Control Register */
1084 1084 control = pciehpc_reg_get16(ctrl_p,
1085 1085 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1086 1086
1087 1087 /*
1088 1088 * Enable power to the slot involves:
1089 1089 * 1. Set power LED to blink and ATTN led to OFF.
1090 1090 * 2. Set power control ON in Slot Control Reigster and
1091 1091 * wait for Command Completed Interrupt or 1 sec timeout.
1092 1092 * 3. If Data Link Layer State Changed events are supported
1093 1093 * then wait for the event to indicate Data Layer Link
1094 1094 * is active. The time out value for this event is 1 second.
1095 1095 * This is specified in PCI-E version 1.1.
1096 1096 * 4. Set power LED to be ON.
1097 1097 */
1098 1098
1099 1099 /* 1. set power LED to blink & ATTN led to OFF */
1100 1100 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_BLINK);
1101 1101 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED, PCIE_HP_LED_OFF);
1102 1102
1103 1103 /* 2. set power control to ON */
1104 1104 control = pciehpc_reg_get16(ctrl_p,
1105 1105 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1106 1106 control &= ~PCIE_SLOTCTL_PWR_CONTROL;
1107 1107 pciehpc_issue_hpc_command(ctrl_p, control);
1108 1108
1109 1109 /* 3. wait for DLL State Change event, if it's supported */
1110 1110 if (ctrl_p->hc_dll_active_rep) {
1111 1111 status = pciehpc_reg_get16(ctrl_p,
1112 1112 bus_p->bus_pcie_off + PCIE_LINKSTS);
1113 1113
1114 1114 if (!(status & PCIE_LINKSTS_DLL_LINK_ACTIVE)) {
1115 1115 /* wait 1 sec for the DLL State Changed event */
1116 1116 (void) cv_timedwait(&slot_p->hs_dll_active_cv,
1117 1117 &ctrl_p->hc_mutex,
1118 1118 ddi_get_lbolt() +
1119 1119 SEC_TO_TICK(PCIE_HP_DLL_STATE_CHANGE_TIMEOUT));
1120 1120
↓ open down ↓ |
1120 lines elided |
↑ open up ↑ |
1121 1121 /* check Link status */
1122 1122 status = pciehpc_reg_get16(ctrl_p,
1123 1123 bus_p->bus_pcie_off +
1124 1124 PCIE_LINKSTS);
1125 1125 if (!(status & PCIE_LINKSTS_DLL_LINK_ACTIVE))
1126 1126 goto cleanup2;
1127 1127 }
1128 1128 }
1129 1129
1130 1130 /* wait 1 sec for link to come up */
1131 - delay(drv_usectohz(1000000));
1131 + delay(drv_sectohz(1));
1132 1132
1133 1133 /* check power is really turned ON */
1134 1134 control = pciehpc_reg_get16(ctrl_p,
1135 1135 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1136 1136
1137 1137 if (control & PCIE_SLOTCTL_PWR_CONTROL) {
1138 1138 PCIE_DBG("slot %d fails to turn on power on connect\n",
1139 1139 slot_p->hs_phy_slot_num);
1140 1140
1141 1141 goto cleanup1;
1142 1142 }
1143 1143
1144 1144 /* clear power fault status */
1145 1145 status = pciehpc_reg_get16(ctrl_p,
1146 1146 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1147 1147 status |= PCIE_SLOTSTS_PWR_FAULT_DETECTED;
1148 1148 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + PCIE_SLOTSTS,
1149 1149 status);
1150 1150
1151 1151 /* enable power fault detection interrupt */
1152 1152 control |= PCIE_SLOTCTL_PWR_FAULT_EN;
1153 1153 pciehpc_issue_hpc_command(ctrl_p, control);
1154 1154
1155 1155 /* 4. Set power LED to be ON */
1156 1156 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_ON);
1157 1157
1158 1158 /* if EMI is present, turn it ON */
1159 1159 if (ctrl_p->hc_has_emi_lock) {
↓ open down ↓ |
18 lines elided |
↑ open up ↑ |
1160 1160 status = pciehpc_reg_get16(ctrl_p,
1161 1161 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1162 1162
1163 1163 if (!(status & PCIE_SLOTSTS_EMI_LOCK_SET)) {
1164 1164 control = pciehpc_reg_get16(ctrl_p,
1165 1165 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1166 1166 control |= PCIE_SLOTCTL_EMI_LOCK_CONTROL;
1167 1167 pciehpc_issue_hpc_command(ctrl_p, control);
1168 1168
1169 1169 /* wait 1 sec after toggling the state of EMI lock */
1170 - delay(drv_usectohz(1000000));
1170 + delay(drv_sectohz(1));
1171 1171 }
1172 1172 }
1173 1173
1174 1174 *result = slot_p->hs_info.cn_state =
1175 1175 DDI_HP_CN_STATE_POWERED;
1176 1176
1177 1177 return (DDI_SUCCESS);
1178 1178
1179 1179 cleanup2:
1180 1180 control = pciehpc_reg_get16(ctrl_p,
1181 1181 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1182 1182
1183 1183 /* if power is ON, set power control to OFF */
1184 1184 if (!(control & PCIE_SLOTCTL_PWR_CONTROL)) {
1185 1185 control |= PCIE_SLOTCTL_PWR_CONTROL;
1186 1186 pciehpc_issue_hpc_command(ctrl_p, control);
1187 1187 }
1188 1188
1189 1189 cleanup1:
1190 1190 /* set power led to OFF */
1191 1191 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_OFF);
1192 1192
1193 1193 cleanup:
1194 1194 return (DDI_FAILURE);
1195 1195 }
1196 1196
1197 1197 /*ARGSUSED*/
1198 1198 static int
1199 1199 pciehpc_slot_poweroff(pcie_hp_slot_t *slot_p, ddi_hp_cn_state_t *result)
1200 1200 {
1201 1201 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1202 1202 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1203 1203 uint16_t status, control;
1204 1204
1205 1205 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1206 1206
1207 1207 /* get the current state of the slot */
1208 1208 pciehpc_get_slot_state(slot_p);
1209 1209
1210 1210 /* check if the slot is not in the "enabled' state */
1211 1211 if (slot_p->hs_info.cn_state < DDI_HP_CN_STATE_POWERED) {
1212 1212 /* slot is in the 'disabled' state */
1213 1213 PCIE_DBG("pciehpc_slot_poweroff(): "
1214 1214 "slot %d already disabled\n", slot_p->hs_phy_slot_num);
1215 1215 ASSERT(slot_p->hs_power_led_state == PCIE_HP_LED_OFF);
1216 1216
1217 1217 *result = slot_p->hs_info.cn_state;
1218 1218 return (DDI_SUCCESS);
1219 1219 }
1220 1220
1221 1221 /* read the Slot Status Register */
1222 1222 status = pciehpc_reg_get16(ctrl_p,
1223 1223 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1224 1224
1225 1225 /* make sure the slot has a device present */
1226 1226 if (!(status & PCIE_SLOTSTS_PRESENCE_DETECTED)) {
1227 1227 /* slot is empty */
1228 1228 PCIE_DBG("pciehpc_slot_poweroff(): slot %d is empty\n",
1229 1229 slot_p->hs_phy_slot_num);
1230 1230 goto cleanup;
1231 1231 }
1232 1232
1233 1233 /*
1234 1234 * Disable power to the slot involves:
1235 1235 * 1. Set power LED to blink.
1236 1236 * 2. Set power control OFF in Slot Control Reigster and
1237 1237 * wait for Command Completed Interrupt or 1 sec timeout.
1238 1238 * 3. Set POWER led and ATTN led to be OFF.
1239 1239 */
1240 1240
1241 1241 /* 1. set power LED to blink */
1242 1242 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_BLINK);
1243 1243
1244 1244 /* disable power fault detection interrupt */
1245 1245 control = pciehpc_reg_get16(ctrl_p,
1246 1246 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1247 1247 control &= ~PCIE_SLOTCTL_PWR_FAULT_EN;
1248 1248 pciehpc_issue_hpc_command(ctrl_p, control);
1249 1249
1250 1250 /* 2. set power control to OFF */
1251 1251 control = pciehpc_reg_get16(ctrl_p,
1252 1252 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1253 1253 control |= PCIE_SLOTCTL_PWR_CONTROL;
1254 1254 pciehpc_issue_hpc_command(ctrl_p, control);
1255 1255
1256 1256 #ifdef DEBUG
1257 1257 /* check for power control bit to be OFF */
1258 1258 control = pciehpc_reg_get16(ctrl_p,
1259 1259 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1260 1260 ASSERT(control & PCIE_SLOTCTL_PWR_CONTROL);
1261 1261 #endif
1262 1262
1263 1263 /* 3. Set power LED to be OFF */
1264 1264 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_OFF);
1265 1265 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED, PCIE_HP_LED_OFF);
1266 1266
1267 1267 /* if EMI is present, turn it OFF */
1268 1268 if (ctrl_p->hc_has_emi_lock) {
↓ open down ↓ |
88 lines elided |
↑ open up ↑ |
1269 1269 status = pciehpc_reg_get16(ctrl_p,
1270 1270 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1271 1271
1272 1272 if (status & PCIE_SLOTSTS_EMI_LOCK_SET) {
1273 1273 control = pciehpc_reg_get16(ctrl_p,
1274 1274 bus_p->bus_pcie_off + PCIE_SLOTCTL);
1275 1275 control |= PCIE_SLOTCTL_EMI_LOCK_CONTROL;
1276 1276 pciehpc_issue_hpc_command(ctrl_p, control);
1277 1277
1278 1278 /* wait 1 sec after toggling the state of EMI lock */
1279 - delay(drv_usectohz(1000000));
1279 + delay(drv_sectohz(1));
1280 1280 }
1281 1281 }
1282 1282
1283 1283 /* get the current state of the slot */
1284 1284 pciehpc_get_slot_state(slot_p);
1285 1285
1286 1286 *result = slot_p->hs_info.cn_state;
1287 1287
1288 1288 return (DDI_SUCCESS);
1289 1289
1290 1290 cleanup:
1291 1291 return (DDI_FAILURE);
1292 1292 }
1293 1293
1294 1294 /*
1295 1295 * pciehpc_slot_probe()
1296 1296 *
1297 1297 * Probe the slot.
1298 1298 *
1299 1299 * Note: This function is called by DDI HP framework at kernel context only
1300 1300 */
1301 1301 /*ARGSUSED*/
1302 1302 static int
1303 1303 pciehpc_slot_probe(pcie_hp_slot_t *slot_p)
1304 1304 {
1305 1305 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1306 1306 int ret = DDI_SUCCESS;
1307 1307
1308 1308 mutex_enter(&ctrl_p->hc_mutex);
1309 1309
1310 1310 /* get the current state of the slot */
1311 1311 pciehpc_get_slot_state(slot_p);
1312 1312
1313 1313 /*
1314 1314 * Probe a given PCIe Hotplug Connection (CN).
1315 1315 */
1316 1316 PCIE_DISABLE_ERRORS(ctrl_p->hc_dip);
1317 1317 ret = pcie_hp_probe(slot_p);
1318 1318
1319 1319 if (ret != DDI_SUCCESS) {
1320 1320 PCIE_DBG("pciehpc_slot_probe() failed\n");
1321 1321
1322 1322 /* turn the ATTN led ON for configure failure */
1323 1323 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED, PCIE_HP_LED_ON);
1324 1324
1325 1325 /* if power to the slot is still on then set Power led to ON */
1326 1326 if (slot_p->hs_info.cn_state >= DDI_HP_CN_STATE_POWERED)
1327 1327 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
1328 1328 PCIE_HP_LED_ON);
1329 1329
1330 1330 mutex_exit(&ctrl_p->hc_mutex);
1331 1331 return (DDI_FAILURE);
1332 1332 }
1333 1333
1334 1334 PCIE_ENABLE_ERRORS(ctrl_p->hc_dip);
1335 1335
1336 1336 /* get the current state of the slot */
1337 1337 pciehpc_get_slot_state(slot_p);
1338 1338
1339 1339 mutex_exit(&ctrl_p->hc_mutex);
1340 1340 return (DDI_SUCCESS);
1341 1341 }
1342 1342
1343 1343 /*
1344 1344 * pciehpc_slot_unprobe()
1345 1345 *
1346 1346 * Unprobe the slot.
1347 1347 *
1348 1348 * Note: This function is called by DDI HP framework at kernel context only
1349 1349 */
1350 1350 /*ARGSUSED*/
1351 1351 static int
1352 1352 pciehpc_slot_unprobe(pcie_hp_slot_t *slot_p)
1353 1353 {
1354 1354 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1355 1355 int ret;
1356 1356
1357 1357 mutex_enter(&ctrl_p->hc_mutex);
1358 1358
1359 1359 /* get the current state of the slot */
1360 1360 pciehpc_get_slot_state(slot_p);
1361 1361
1362 1362 /*
1363 1363 * Unprobe a given PCIe Hotplug Connection (CN).
1364 1364 */
1365 1365 PCIE_DISABLE_ERRORS(ctrl_p->hc_dip);
1366 1366 ret = pcie_hp_unprobe(slot_p);
1367 1367
1368 1368 if (ret != DDI_SUCCESS) {
1369 1369 PCIE_DBG("pciehpc_slot_unprobe() failed\n");
1370 1370
1371 1371 /* if power to the slot is still on then set Power led to ON */
1372 1372 if (slot_p->hs_info.cn_state >= DDI_HP_CN_STATE_POWERED)
1373 1373 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
1374 1374 PCIE_HP_LED_ON);
1375 1375
1376 1376 PCIE_ENABLE_ERRORS(ctrl_p->hc_dip);
1377 1377
1378 1378 mutex_exit(&ctrl_p->hc_mutex);
1379 1379 return (DDI_FAILURE);
1380 1380 }
1381 1381
1382 1382 /* get the current state of the slot */
1383 1383 pciehpc_get_slot_state(slot_p);
1384 1384
1385 1385 mutex_exit(&ctrl_p->hc_mutex);
1386 1386 return (DDI_SUCCESS);
1387 1387 }
1388 1388
1389 1389 static int
1390 1390 pciehpc_upgrade_slot_state(pcie_hp_slot_t *slot_p,
1391 1391 ddi_hp_cn_state_t target_state)
1392 1392 {
1393 1393 ddi_hp_cn_state_t curr_state;
1394 1394 int rv = DDI_SUCCESS;
1395 1395
1396 1396 if (target_state > DDI_HP_CN_STATE_ENABLED) {
1397 1397 return (DDI_EINVAL);
1398 1398 }
1399 1399
1400 1400 curr_state = slot_p->hs_info.cn_state;
1401 1401 while ((curr_state < target_state) && (rv == DDI_SUCCESS)) {
1402 1402
1403 1403 switch (curr_state) {
1404 1404 case DDI_HP_CN_STATE_EMPTY:
1405 1405 /*
1406 1406 * From EMPTY to PRESENT, just check the hardware
1407 1407 * slot state.
1408 1408 */
1409 1409 pciehpc_get_slot_state(slot_p);
1410 1410 curr_state = slot_p->hs_info.cn_state;
1411 1411 if (curr_state < DDI_HP_CN_STATE_PRESENT)
1412 1412 rv = DDI_FAILURE;
1413 1413 break;
1414 1414 case DDI_HP_CN_STATE_PRESENT:
1415 1415 rv = (slot_p->hs_ctrl->hc_ops.poweron_hpc_slot)(slot_p,
1416 1416 &curr_state);
1417 1417
1418 1418 break;
1419 1419 case DDI_HP_CN_STATE_POWERED:
1420 1420 curr_state = slot_p->hs_info.cn_state =
1421 1421 DDI_HP_CN_STATE_ENABLED;
1422 1422 break;
1423 1423 default:
1424 1424 /* should never reach here */
1425 1425 ASSERT("unknown devinfo state");
1426 1426 }
1427 1427 }
1428 1428
1429 1429 return (rv);
1430 1430 }
1431 1431
1432 1432 static int
1433 1433 pciehpc_downgrade_slot_state(pcie_hp_slot_t *slot_p,
1434 1434 ddi_hp_cn_state_t target_state)
1435 1435 {
1436 1436 ddi_hp_cn_state_t curr_state;
1437 1437 int rv = DDI_SUCCESS;
1438 1438
1439 1439
1440 1440 curr_state = slot_p->hs_info.cn_state;
1441 1441 while ((curr_state > target_state) && (rv == DDI_SUCCESS)) {
1442 1442
1443 1443 switch (curr_state) {
1444 1444 case DDI_HP_CN_STATE_PRESENT:
1445 1445 /*
1446 1446 * From PRESENT to EMPTY, just check hardware slot
1447 1447 * state.
1448 1448 */
1449 1449 pciehpc_get_slot_state(slot_p);
1450 1450 curr_state = slot_p->hs_info.cn_state;
1451 1451 if (curr_state >= DDI_HP_CN_STATE_PRESENT)
1452 1452 rv = DDI_FAILURE;
1453 1453 break;
1454 1454 case DDI_HP_CN_STATE_POWERED:
1455 1455 rv = (slot_p->hs_ctrl->hc_ops.poweroff_hpc_slot)(
1456 1456 slot_p, &curr_state);
1457 1457
1458 1458 break;
1459 1459 case DDI_HP_CN_STATE_ENABLED:
1460 1460 curr_state = slot_p->hs_info.cn_state =
1461 1461 DDI_HP_CN_STATE_POWERED;
1462 1462
1463 1463 break;
1464 1464 default:
1465 1465 /* should never reach here */
1466 1466 ASSERT("unknown devinfo state");
1467 1467 }
1468 1468 }
1469 1469
1470 1470 return (rv);
1471 1471 }
1472 1472
1473 1473 /* Change slot state to a target state */
1474 1474 static int
1475 1475 pciehpc_change_slot_state(pcie_hp_slot_t *slot_p,
1476 1476 ddi_hp_cn_state_t target_state)
1477 1477 {
1478 1478 ddi_hp_cn_state_t curr_state;
1479 1479 int rv;
1480 1480
1481 1481 pciehpc_get_slot_state(slot_p);
1482 1482 curr_state = slot_p->hs_info.cn_state;
1483 1483
1484 1484 if (curr_state == target_state) {
1485 1485 return (DDI_SUCCESS);
1486 1486 }
1487 1487 if (curr_state < target_state) {
1488 1488
1489 1489 rv = pciehpc_upgrade_slot_state(slot_p, target_state);
1490 1490 } else {
1491 1491 rv = pciehpc_downgrade_slot_state(slot_p, target_state);
1492 1492 }
1493 1493
1494 1494 return (rv);
1495 1495 }
1496 1496
1497 1497 int
1498 1498 pciehpc_slot_get_property(pcie_hp_slot_t *slot_p, ddi_hp_property_t *arg,
1499 1499 ddi_hp_property_t *rval)
1500 1500 {
1501 1501 ddi_hp_property_t request, result;
1502 1502 #ifdef _SYSCALL32_IMPL
1503 1503 ddi_hp_property32_t request32, result32;
1504 1504 #endif
1505 1505 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1506 1506 nvlist_t *prop_list;
1507 1507 nvlist_t *prop_rlist; /* nvlist for return values */
1508 1508 nvpair_t *prop_pair;
1509 1509 char *name, *value;
1510 1510 int ret = DDI_SUCCESS;
1511 1511 int i, n;
1512 1512 boolean_t get_all_prop = B_FALSE;
1513 1513
1514 1514 if (get_udatamodel() == DATAMODEL_NATIVE) {
1515 1515 if (copyin(arg, &request, sizeof (ddi_hp_property_t)) ||
1516 1516 copyin(rval, &result, sizeof (ddi_hp_property_t)))
1517 1517 return (DDI_FAILURE);
1518 1518 }
1519 1519 #ifdef _SYSCALL32_IMPL
1520 1520 else {
1521 1521 bzero(&request, sizeof (request));
1522 1522 bzero(&result, sizeof (result));
1523 1523 if (copyin(arg, &request32, sizeof (ddi_hp_property32_t)) ||
1524 1524 copyin(rval, &result32, sizeof (ddi_hp_property32_t)))
1525 1525 return (DDI_FAILURE);
1526 1526 request.nvlist_buf = (char *)(uintptr_t)request32.nvlist_buf;
1527 1527 request.buf_size = request32.buf_size;
1528 1528 result.nvlist_buf = (char *)(uintptr_t)result32.nvlist_buf;
1529 1529 result.buf_size = result32.buf_size;
1530 1530 }
1531 1531 #endif
1532 1532
1533 1533 if ((ret = pcie_copyin_nvlist(request.nvlist_buf, request.buf_size,
1534 1534 &prop_list)) != DDI_SUCCESS)
1535 1535 return (ret);
1536 1536
1537 1537 if (nvlist_alloc(&prop_rlist, NV_UNIQUE_NAME, 0)) {
1538 1538 ret = DDI_ENOMEM;
1539 1539 goto get_prop_cleanup;
1540 1540 }
1541 1541
1542 1542 /* check whether the requested property is "all" or "help" */
1543 1543 prop_pair = nvlist_next_nvpair(prop_list, NULL);
1544 1544 if (prop_pair && !nvlist_next_nvpair(prop_list, prop_pair)) {
1545 1545 name = nvpair_name(prop_pair);
1546 1546 n = sizeof (pciehpc_props) / sizeof (pciehpc_prop_t);
1547 1547
1548 1548 if (strcmp(name, PCIEHPC_PROP_ALL) == 0) {
1549 1549 (void) nvlist_remove_all(prop_list, PCIEHPC_PROP_ALL);
1550 1550
1551 1551 /*
1552 1552 * Add all properties into the request list, so that we
1553 1553 * will get the values in the following for loop.
1554 1554 */
1555 1555 for (i = 0; i < n; i++) {
1556 1556 if (nvlist_add_string(prop_list,
1557 1557 pciehpc_props[i].prop_name, "") != 0) {
1558 1558 ret = DDI_FAILURE;
1559 1559 goto get_prop_cleanup1;
1560 1560 }
1561 1561 }
1562 1562 get_all_prop = B_TRUE;
1563 1563 } else if (strcmp(name, PCIEHPC_PROP_HELP) == 0) {
1564 1564 /*
1565 1565 * Empty the request list, and add help strings into the
1566 1566 * return list. We will pass the following for loop.
1567 1567 */
1568 1568 (void) nvlist_remove_all(prop_list, PCIEHPC_PROP_HELP);
1569 1569
1570 1570 for (i = 0; i < n; i++) {
1571 1571 if (nvlist_add_string(prop_rlist,
1572 1572 pciehpc_props[i].prop_name,
1573 1573 pciehpc_props[i].prop_value) != 0) {
1574 1574 ret = DDI_FAILURE;
1575 1575 goto get_prop_cleanup1;
1576 1576 }
1577 1577 }
1578 1578 }
1579 1579 }
1580 1580
1581 1581 mutex_enter(&ctrl_p->hc_mutex);
1582 1582
1583 1583 /* get the current slot state */
1584 1584 pciehpc_get_slot_state(slot_p);
1585 1585
1586 1586 /* for each requested property, get the value and add it to nvlist */
1587 1587 prop_pair = NULL;
1588 1588 while (prop_pair = nvlist_next_nvpair(prop_list, prop_pair)) {
1589 1589 name = nvpair_name(prop_pair);
1590 1590
1591 1591 if (strcmp(name, PCIEHPC_PROP_LED_FAULT) == 0) {
1592 1592 value = pcie_led_state_text(
1593 1593 slot_p->hs_fault_led_state);
1594 1594 } else if (strcmp(name, PCIEHPC_PROP_LED_POWER) == 0) {
1595 1595 value = pcie_led_state_text(
1596 1596 slot_p->hs_power_led_state);
1597 1597 } else if (strcmp(name, PCIEHPC_PROP_LED_ATTN) == 0) {
1598 1598 value = pcie_led_state_text(
1599 1599 slot_p->hs_attn_led_state);
1600 1600 } else if (strcmp(name, PCIEHPC_PROP_LED_ACTIVE) == 0) {
1601 1601 value = pcie_led_state_text(
1602 1602 slot_p->hs_active_led_state);
1603 1603 } else if (strcmp(name, PCIEHPC_PROP_CARD_TYPE) == 0) {
1604 1604 ddi_acc_handle_t handle;
1605 1605 dev_info_t *cdip;
1606 1606 uint8_t prog_class, base_class, sub_class;
1607 1607 int i;
1608 1608
1609 1609 mutex_exit(&ctrl_p->hc_mutex);
1610 1610 cdip = pcie_hp_devi_find(
1611 1611 ctrl_p->hc_dip, slot_p->hs_device_num, 0);
1612 1612 mutex_enter(&ctrl_p->hc_mutex);
1613 1613
1614 1614 if ((slot_p->hs_info.cn_state
1615 1615 != DDI_HP_CN_STATE_ENABLED) || (cdip == NULL)) {
1616 1616 /*
1617 1617 * When getting all properties, just ignore the
1618 1618 * one that's not available under certain state.
1619 1619 */
1620 1620 if (get_all_prop)
1621 1621 continue;
1622 1622
1623 1623 ret = DDI_ENOTSUP;
1624 1624 goto get_prop_cleanup2;
1625 1625 }
1626 1626
1627 1627 if (pci_config_setup(cdip, &handle) != DDI_SUCCESS) {
1628 1628 ret = DDI_FAILURE;
1629 1629 goto get_prop_cleanup2;
1630 1630 }
1631 1631
1632 1632 prog_class = pci_config_get8(handle,
1633 1633 PCI_CONF_PROGCLASS);
1634 1634 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS);
1635 1635 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS);
1636 1636 pci_config_teardown(&handle);
1637 1637
1638 1638 for (i = 0; i < class_pci_items; i++) {
1639 1639 if ((base_class == class_pci[i].base_class) &&
1640 1640 (sub_class == class_pci[i].sub_class) &&
1641 1641 (prog_class == class_pci[i].prog_class)) {
1642 1642 value = class_pci[i].short_desc;
1643 1643 break;
1644 1644 }
1645 1645 }
1646 1646 if (i == class_pci_items)
1647 1647 value = PCIEHPC_PROP_VALUE_UNKNOWN;
1648 1648 } else if (strcmp(name, PCIEHPC_PROP_BOARD_TYPE) == 0) {
1649 1649 if (slot_p->hs_info.cn_state <= DDI_HP_CN_STATE_EMPTY)
1650 1650 value = PCIEHPC_PROP_VALUE_UNKNOWN;
1651 1651 else
1652 1652 value = PCIEHPC_PROP_VALUE_PCIHOTPLUG;
1653 1653 } else if (strcmp(name, PCIEHPC_PROP_SLOT_CONDITION) == 0) {
1654 1654 value = pcie_slot_condition_text(slot_p->hs_condition);
1655 1655 } else {
1656 1656 /* unsupported property */
1657 1657 PCIE_DBG("Unsupported property: %s\n", name);
1658 1658
1659 1659 ret = DDI_ENOTSUP;
1660 1660 goto get_prop_cleanup2;
1661 1661 }
1662 1662 if (nvlist_add_string(prop_rlist, name, value) != 0) {
1663 1663 ret = DDI_FAILURE;
1664 1664 goto get_prop_cleanup2;
1665 1665 }
1666 1666 }
1667 1667
1668 1668 /* pack nvlist and copyout */
1669 1669 if ((ret = pcie_copyout_nvlist(prop_rlist, result.nvlist_buf,
1670 1670 &result.buf_size)) != DDI_SUCCESS) {
1671 1671 goto get_prop_cleanup2;
1672 1672 }
1673 1673 if (get_udatamodel() == DATAMODEL_NATIVE) {
1674 1674 if (copyout(&result, rval, sizeof (ddi_hp_property_t)))
1675 1675 ret = DDI_FAILURE;
1676 1676 }
1677 1677 #ifdef _SYSCALL32_IMPL
1678 1678 else {
1679 1679 if (result.buf_size > UINT32_MAX) {
1680 1680 ret = DDI_FAILURE;
1681 1681 } else {
1682 1682 result32.buf_size = (uint32_t)result.buf_size;
1683 1683 if (copyout(&result32, rval,
1684 1684 sizeof (ddi_hp_property32_t)))
1685 1685 ret = DDI_FAILURE;
1686 1686 }
1687 1687 }
1688 1688 #endif
1689 1689
1690 1690 get_prop_cleanup2:
1691 1691 mutex_exit(&ctrl_p->hc_mutex);
1692 1692 get_prop_cleanup1:
1693 1693 nvlist_free(prop_rlist);
1694 1694 get_prop_cleanup:
1695 1695 nvlist_free(prop_list);
1696 1696 return (ret);
1697 1697 }
1698 1698
1699 1699 int
1700 1700 pciehpc_slot_set_property(pcie_hp_slot_t *slot_p, ddi_hp_property_t *arg,
1701 1701 ddi_hp_property_t *rval)
1702 1702 {
1703 1703 ddi_hp_property_t request, result;
1704 1704 #ifdef _SYSCALL32_IMPL
1705 1705 ddi_hp_property32_t request32, result32;
1706 1706 #endif
1707 1707 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1708 1708 nvlist_t *prop_list;
1709 1709 nvlist_t *prop_rlist;
1710 1710 nvpair_t *prop_pair;
1711 1711 char *name, *value;
1712 1712 pcie_hp_led_state_t led_state;
1713 1713 int ret = DDI_SUCCESS;
1714 1714
1715 1715 if (get_udatamodel() == DATAMODEL_NATIVE) {
1716 1716 if (copyin(arg, &request, sizeof (ddi_hp_property_t)))
1717 1717 return (DDI_FAILURE);
1718 1718 if (rval &&
1719 1719 copyin(rval, &result, sizeof (ddi_hp_property_t)))
1720 1720 return (DDI_FAILURE);
1721 1721 }
1722 1722 #ifdef _SYSCALL32_IMPL
1723 1723 else {
1724 1724 bzero(&request, sizeof (request));
1725 1725 bzero(&result, sizeof (result));
1726 1726 if (copyin(arg, &request32, sizeof (ddi_hp_property32_t)))
1727 1727 return (DDI_FAILURE);
1728 1728 if (rval &&
1729 1729 copyin(rval, &result32, sizeof (ddi_hp_property32_t)))
1730 1730 return (DDI_FAILURE);
1731 1731 request.nvlist_buf = (char *)(uintptr_t)request32.nvlist_buf;
1732 1732 request.buf_size = request32.buf_size;
1733 1733 if (rval) {
1734 1734 result.nvlist_buf =
1735 1735 (char *)(uintptr_t)result32.nvlist_buf;
1736 1736 result.buf_size = result32.buf_size;
1737 1737 }
1738 1738 }
1739 1739 #endif
1740 1740
1741 1741 if ((ret = pcie_copyin_nvlist(request.nvlist_buf, request.buf_size,
1742 1742 &prop_list)) != DDI_SUCCESS)
1743 1743 return (ret);
1744 1744
1745 1745 /* check whether the requested property is "help" */
1746 1746 prop_pair = nvlist_next_nvpair(prop_list, NULL);
1747 1747 if (prop_pair && !nvlist_next_nvpair(prop_list, prop_pair) &&
1748 1748 (strcmp(nvpair_name(prop_pair), PCIEHPC_PROP_HELP) == 0)) {
1749 1749 if (!rval) {
1750 1750 ret = DDI_ENOTSUP;
1751 1751 goto set_prop_cleanup;
1752 1752 }
1753 1753
1754 1754 if (nvlist_alloc(&prop_rlist, NV_UNIQUE_NAME, 0)) {
1755 1755 ret = DDI_ENOMEM;
1756 1756 goto set_prop_cleanup;
1757 1757 }
1758 1758 if (nvlist_add_string(prop_rlist, PCIEHPC_PROP_LED_ATTN,
1759 1759 PCIEHPC_PROP_VALUE_LED) != 0) {
1760 1760 ret = DDI_FAILURE;
1761 1761 goto set_prop_cleanup1;
1762 1762 }
1763 1763
1764 1764 if ((ret = pcie_copyout_nvlist(prop_rlist, result.nvlist_buf,
1765 1765 &result.buf_size)) != DDI_SUCCESS) {
1766 1766 goto set_prop_cleanup1;
1767 1767 }
1768 1768 if (get_udatamodel() == DATAMODEL_NATIVE) {
1769 1769 if (copyout(&result, rval,
1770 1770 sizeof (ddi_hp_property_t))) {
1771 1771 ret = DDI_FAILURE;
1772 1772 goto set_prop_cleanup1;
1773 1773 }
1774 1774 }
1775 1775 #ifdef _SYSCALL32_IMPL
1776 1776 else {
1777 1777 if (result.buf_size > UINT32_MAX) {
1778 1778 ret = DDI_FAILURE;
1779 1779 goto set_prop_cleanup1;
1780 1780 } else {
1781 1781 result32.buf_size = (uint32_t)result.buf_size;
1782 1782 if (copyout(&result32, rval,
1783 1783 sizeof (ddi_hp_property32_t))) {
1784 1784 ret = DDI_FAILURE;
1785 1785 goto set_prop_cleanup1;
1786 1786 }
1787 1787 }
1788 1788 }
1789 1789 #endif
1790 1790 set_prop_cleanup1:
1791 1791 nvlist_free(prop_rlist);
1792 1792 nvlist_free(prop_list);
1793 1793 return (ret);
1794 1794 }
1795 1795
1796 1796 /* Validate the request */
1797 1797 prop_pair = NULL;
1798 1798 while (prop_pair = nvlist_next_nvpair(prop_list, prop_pair)) {
1799 1799 name = nvpair_name(prop_pair);
1800 1800 if (nvpair_type(prop_pair) != DATA_TYPE_STRING) {
1801 1801 PCIE_DBG("Unexpected data type of setting "
1802 1802 "property %s.\n", name);
1803 1803 ret = DDI_EINVAL;
1804 1804 goto set_prop_cleanup;
1805 1805 }
1806 1806 if (nvpair_value_string(prop_pair, &value)) {
1807 1807 PCIE_DBG("Get string value failed for property %s.\n",
1808 1808 name);
1809 1809 ret = DDI_FAILURE;
1810 1810 goto set_prop_cleanup;
1811 1811 }
1812 1812
1813 1813 if (strcmp(name, PCIEHPC_PROP_LED_ATTN) == 0) {
1814 1814 if ((strcmp(value, PCIEHPC_PROP_VALUE_ON) != 0) &&
1815 1815 (strcmp(value, PCIEHPC_PROP_VALUE_OFF) != 0) &&
1816 1816 (strcmp(value, PCIEHPC_PROP_VALUE_BLINK) != 0)) {
1817 1817 PCIE_DBG("Unsupported value of setting "
1818 1818 "property %s\n", name);
1819 1819 ret = DDI_ENOTSUP;
1820 1820 goto set_prop_cleanup;
1821 1821 }
1822 1822 } else {
1823 1823 PCIE_DBG("Unsupported property: %s\n", name);
1824 1824 ret = DDI_ENOTSUP;
1825 1825 goto set_prop_cleanup;
1826 1826 }
1827 1827 }
1828 1828 mutex_enter(&ctrl_p->hc_mutex);
1829 1829
1830 1830 /* get the current slot state */
1831 1831 pciehpc_get_slot_state(slot_p);
1832 1832
1833 1833 /* set each property */
1834 1834 prop_pair = NULL;
1835 1835 while (prop_pair = nvlist_next_nvpair(prop_list, prop_pair)) {
1836 1836 name = nvpair_name(prop_pair);
1837 1837
1838 1838 if (strcmp(name, PCIEHPC_PROP_LED_ATTN) == 0) {
1839 1839 if (strcmp(value, PCIEHPC_PROP_VALUE_ON) == 0)
1840 1840 led_state = PCIE_HP_LED_ON;
1841 1841 else if (strcmp(value, PCIEHPC_PROP_VALUE_OFF) == 0)
1842 1842 led_state = PCIE_HP_LED_OFF;
1843 1843 else if (strcmp(value, PCIEHPC_PROP_VALUE_BLINK) == 0)
1844 1844 led_state = PCIE_HP_LED_BLINK;
1845 1845
1846 1846 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED,
1847 1847 led_state);
1848 1848 }
1849 1849 }
1850 1850 if (rval) {
1851 1851 if (get_udatamodel() == DATAMODEL_NATIVE) {
1852 1852 result.buf_size = 0;
1853 1853 if (copyout(&result, rval, sizeof (ddi_hp_property_t)))
1854 1854 ret = DDI_FAILURE;
1855 1855 }
1856 1856 #ifdef _SYSCALL32_IMPL
1857 1857 else {
1858 1858 result32.buf_size = 0;
1859 1859 if (copyout(&result32, rval,
1860 1860 sizeof (ddi_hp_property32_t)))
1861 1861 ret = DDI_FAILURE;
1862 1862 }
1863 1863 #endif
1864 1864 }
1865 1865
1866 1866 mutex_exit(&ctrl_p->hc_mutex);
1867 1867 set_prop_cleanup:
1868 1868 nvlist_free(prop_list);
1869 1869 return (ret);
1870 1870 }
1871 1871
1872 1872 /*
1873 1873 * Send a command to the PCI-E Hot Plug Controller.
1874 1874 *
1875 1875 * NOTES: The PCI-E spec defines the following semantics for issuing hot plug
1876 1876 * commands.
1877 1877 * 1) If Command Complete events/interrupts are supported then software
1878 1878 * waits for Command Complete event after issuing a command (i.e writing
1879 1879 * to the Slot Control register). The command completion could take as
1880 1880 * long as 1 second so software should be prepared to wait for 1 second
1881 1881 * before issuing another command.
1882 1882 *
1883 1883 * 2) If Command Complete events/interrupts are not supported then
1884 1884 * software could issue multiple Slot Control writes without any delay
1885 1885 * between writes.
1886 1886 */
1887 1887 static void
1888 1888 pciehpc_issue_hpc_command(pcie_hp_ctrl_t *ctrl_p, uint16_t control)
1889 1889 {
1890 1890 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
1891 1891 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1892 1892 uint16_t status;
1893 1893 uint32_t slot_cap;
1894 1894
1895 1895 /*
1896 1896 * PCI-E version 1.1 spec defines No Command Completed
1897 1897 * Support bit (bit#18) in Slot Capabilities register. If this
1898 1898 * bit is set then slot doesn't support notification of command
1899 1899 * completion events.
1900 1900 */
1901 1901 slot_cap = pciehpc_reg_get32(ctrl_p,
1902 1902 bus_p->bus_pcie_off + PCIE_SLOTCAP);
1903 1903
1904 1904 /*
1905 1905 * If no Command Completion event is supported or it is ACPI
1906 1906 * hot plug mode then just issue the command and return.
1907 1907 */
1908 1908 if ((slot_cap & PCIE_SLOTCAP_NO_CMD_COMP_SUPP) ||
1909 1909 (bus_p->bus_hp_curr_mode == PCIE_ACPI_HP_MODE)) {
1910 1910 pciehpc_reg_put16(ctrl_p,
1911 1911 bus_p->bus_pcie_off + PCIE_SLOTCTL, control);
1912 1912 return;
1913 1913 }
1914 1914
1915 1915 /*
1916 1916 * **************************************
1917 1917 * Command Complete events are supported.
1918 1918 * **************************************
1919 1919 */
1920 1920
1921 1921 /*
1922 1922 * If HPC is not yet initialized then just poll for the Command
1923 1923 * Completion interrupt.
1924 1924 */
1925 1925 if (!(ctrl_p->hc_flags & PCIE_HP_INITIALIZED_FLAG)) {
1926 1926 int retry = PCIE_HP_CMD_WAIT_RETRY;
1927 1927
1928 1928 /* write the command to the HPC */
1929 1929 pciehpc_reg_put16(ctrl_p,
1930 1930 bus_p->bus_pcie_off + PCIE_SLOTCTL, control);
1931 1931
1932 1932 /* poll for status completion */
1933 1933 while (retry--) {
1934 1934 /* wait for 10 msec before checking the status */
1935 1935 delay(drv_usectohz(PCIE_HP_CMD_WAIT_TIME));
1936 1936
1937 1937 status = pciehpc_reg_get16(ctrl_p,
1938 1938 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1939 1939
1940 1940 if (status & PCIE_SLOTSTS_COMMAND_COMPLETED) {
1941 1941 /* clear the status bits */
1942 1942 pciehpc_reg_put16(ctrl_p,
1943 1943 bus_p->bus_pcie_off + PCIE_SLOTSTS, status);
1944 1944 break;
1945 1945 }
1946 1946 }
1947 1947 return;
1948 1948 }
1949 1949
1950 1950 /* HPC is already initialized */
1951 1951
1952 1952 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1953 1953
1954 1954 /*
1955 1955 * If previous command is still pending then wait for its
1956 1956 * completion. i.e cv_wait()
1957 1957 */
1958 1958
1959 1959 while (ctrl_p->hc_cmd_pending == B_TRUE)
1960 1960 cv_wait(&ctrl_p->hc_cmd_comp_cv, &ctrl_p->hc_mutex);
1961 1961
1962 1962 /*
1963 1963 * Issue the command and wait for Command Completion or
1964 1964 * the 1 sec timeout.
1965 1965 */
1966 1966 pciehpc_reg_put16(ctrl_p,
1967 1967 bus_p->bus_pcie_off + PCIE_SLOTCTL, control);
1968 1968
1969 1969 ctrl_p->hc_cmd_pending = B_TRUE;
1970 1970
1971 1971 if (cv_timedwait(&ctrl_p->hc_cmd_comp_cv, &ctrl_p->hc_mutex,
1972 1972 ddi_get_lbolt() + SEC_TO_TICK(1)) == -1) {
1973 1973
1974 1974 /* it is a timeout */
1975 1975 PCIE_DBG("pciehpc_issue_hpc_command: Command Complete"
1976 1976 " interrupt is not received for slot %d\n",
1977 1977 slot_p->hs_phy_slot_num);
1978 1978
1979 1979 /* clear the status info in case interrupts are disabled? */
1980 1980 status = pciehpc_reg_get16(ctrl_p,
1981 1981 bus_p->bus_pcie_off + PCIE_SLOTSTS);
1982 1982
1983 1983 if (status & PCIE_SLOTSTS_COMMAND_COMPLETED) {
1984 1984 /* clear the status bits */
1985 1985 pciehpc_reg_put16(ctrl_p,
1986 1986 bus_p->bus_pcie_off + PCIE_SLOTSTS, status);
1987 1987 }
1988 1988 }
1989 1989
1990 1990 ctrl_p->hc_cmd_pending = B_FALSE;
1991 1991
1992 1992 /* wake up any one waiting for issuing another command to HPC */
1993 1993 cv_signal(&ctrl_p->hc_cmd_comp_cv);
1994 1994 }
1995 1995
1996 1996 /*
1997 1997 * pciehcp_attn_btn_handler()
1998 1998 *
1999 1999 * This handles ATTN button pressed event as per the PCI-E 1.1 spec.
2000 2000 */
2001 2001 static void
2002 2002 pciehpc_attn_btn_handler(pcie_hp_ctrl_t *ctrl_p)
2003 2003 {
2004 2004 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
2005 2005 pcie_hp_led_state_t power_led_state;
2006 2006 callb_cpr_t cprinfo;
2007 2007
2008 2008 PCIE_DBG("pciehpc_attn_btn_handler: thread started\n");
2009 2009
2010 2010 CALLB_CPR_INIT(&cprinfo, &ctrl_p->hc_mutex, callb_generic_cpr,
2011 2011 "pciehpc_attn_btn_handler");
2012 2012
2013 2013 mutex_enter(&ctrl_p->hc_mutex);
2014 2014
2015 2015 /* wait for ATTN button event */
2016 2016 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
2017 2017
2018 2018 while (slot_p->hs_attn_btn_thread_exit == B_FALSE) {
2019 2019 if (slot_p->hs_attn_btn_pending == B_TRUE) {
2020 2020 /* get the current state of power LED */
2021 2021 power_led_state = pciehpc_get_led_state(ctrl_p,
2022 2022 PCIE_HP_POWER_LED);
2023 2023
2024 2024 /* Blink the Power LED while we wait for 5 seconds */
2025 2025 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
2026 2026 PCIE_HP_LED_BLINK);
2027 2027
2028 2028 /* wait for 5 seconds before taking any action */
2029 2029 if (cv_timedwait(&slot_p->hs_attn_btn_cv,
2030 2030 &ctrl_p->hc_mutex,
2031 2031 ddi_get_lbolt() + SEC_TO_TICK(5)) == -1) {
2032 2032 /*
2033 2033 * It is a time out; make sure the ATTN pending
2034 2034 * flag is still ON before sending the event to
2035 2035 * DDI HP framework.
2036 2036 */
2037 2037 if (slot_p->hs_attn_btn_pending == B_TRUE) {
2038 2038 int hint;
2039 2039
2040 2040 slot_p->hs_attn_btn_pending = B_FALSE;
2041 2041 pciehpc_get_slot_state(slot_p);
2042 2042
2043 2043 if (slot_p->hs_info.cn_state <=
2044 2044 DDI_HP_CN_STATE_PRESENT) {
2045 2045 /*
2046 2046 * Insertion.
2047 2047 */
2048 2048 hint = SE_INCOMING_RES;
2049 2049 } else {
2050 2050 /*
2051 2051 * Want to remove;
2052 2052 */
2053 2053 hint = SE_OUTGOING_RES;
2054 2054 }
2055 2055
2056 2056 /*
2057 2057 * We can't call ddihp_cn_gen_sysevent
2058 2058 * here since it's not a DDI interface.
2059 2059 */
2060 2060 pcie_hp_gen_sysevent_req(
2061 2061 slot_p->hs_info.cn_name,
2062 2062 hint,
2063 2063 ctrl_p->hc_dip,
2064 2064 KM_SLEEP);
2065 2065 }
2066 2066 }
2067 2067
2068 2068 /* restore the power LED state */
2069 2069 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
2070 2070 power_led_state);
2071 2071 continue;
2072 2072 }
2073 2073
2074 2074 /* wait for another ATTN button event */
2075 2075 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
2076 2076 }
2077 2077
2078 2078 PCIE_DBG("pciehpc_attn_btn_handler: thread exit\n");
2079 2079 cv_signal(&slot_p->hs_attn_btn_cv);
2080 2080 CALLB_CPR_EXIT(&cprinfo);
2081 2081 thread_exit();
2082 2082 }
2083 2083
2084 2084 /*
2085 2085 * convert LED state from PCIE HPC definition to pcie_hp_led_state_t
2086 2086 * definition.
2087 2087 */
2088 2088 static pcie_hp_led_state_t
2089 2089 pciehpc_led_state_to_hpc(uint16_t state)
2090 2090 {
2091 2091 switch (state) {
2092 2092 case PCIE_SLOTCTL_INDICATOR_STATE_ON:
2093 2093 return (PCIE_HP_LED_ON);
2094 2094 case PCIE_SLOTCTL_INDICATOR_STATE_BLINK:
2095 2095 return (PCIE_HP_LED_BLINK);
2096 2096 case PCIE_SLOTCTL_INDICATOR_STATE_OFF:
2097 2097 default:
2098 2098 return (PCIE_HP_LED_OFF);
2099 2099 }
2100 2100 }
2101 2101
2102 2102 /*
2103 2103 * Get the state of an LED.
2104 2104 */
2105 2105 static pcie_hp_led_state_t
2106 2106 pciehpc_get_led_state(pcie_hp_ctrl_t *ctrl_p, pcie_hp_led_t led)
2107 2107 {
2108 2108 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2109 2109 uint16_t control, state;
2110 2110
2111 2111 /* get the current state of Slot Control register */
2112 2112 control = pciehpc_reg_get16(ctrl_p,
2113 2113 bus_p->bus_pcie_off + PCIE_SLOTCTL);
2114 2114
2115 2115 switch (led) {
2116 2116 case PCIE_HP_POWER_LED:
2117 2117 state = pcie_slotctl_pwr_indicator_get(control);
2118 2118 break;
2119 2119 case PCIE_HP_ATTN_LED:
2120 2120 state = pcie_slotctl_attn_indicator_get(control);
2121 2121 break;
2122 2122 default:
2123 2123 PCIE_DBG("pciehpc_get_led_state() invalid LED %d\n", led);
2124 2124 return (PCIE_HP_LED_OFF);
2125 2125 }
2126 2126
2127 2127 switch (state) {
2128 2128 case PCIE_SLOTCTL_INDICATOR_STATE_ON:
2129 2129 return (PCIE_HP_LED_ON);
2130 2130
2131 2131 case PCIE_SLOTCTL_INDICATOR_STATE_BLINK:
2132 2132 return (PCIE_HP_LED_BLINK);
2133 2133
2134 2134 case PCIE_SLOTCTL_INDICATOR_STATE_OFF:
2135 2135 default:
2136 2136 return (PCIE_HP_LED_OFF);
2137 2137 }
2138 2138 }
2139 2139
2140 2140 /*
2141 2141 * Set the state of an LED. It updates both hw and sw state.
2142 2142 */
2143 2143 static void
2144 2144 pciehpc_set_led_state(pcie_hp_ctrl_t *ctrl_p, pcie_hp_led_t led,
2145 2145 pcie_hp_led_state_t state)
2146 2146 {
2147 2147 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
2148 2148 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2149 2149 uint16_t control;
2150 2150
2151 2151 /* get the current state of Slot Control register */
2152 2152 control = pciehpc_reg_get16(ctrl_p,
2153 2153 bus_p->bus_pcie_off + PCIE_SLOTCTL);
2154 2154
2155 2155 switch (led) {
2156 2156 case PCIE_HP_POWER_LED:
2157 2157 /* clear led mask */
2158 2158 control &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
2159 2159 slot_p->hs_power_led_state = state;
2160 2160 break;
2161 2161 case PCIE_HP_ATTN_LED:
2162 2162 /* clear led mask */
2163 2163 control &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
2164 2164 slot_p->hs_attn_led_state = state;
2165 2165 break;
2166 2166 default:
2167 2167 PCIE_DBG("pciehpc_set_led_state() invalid LED %d\n", led);
2168 2168 return;
2169 2169 }
2170 2170
2171 2171 switch (state) {
2172 2172 case PCIE_HP_LED_ON:
2173 2173 if (led == PCIE_HP_POWER_LED)
2174 2174 control = pcie_slotctl_pwr_indicator_set(control,
2175 2175 PCIE_SLOTCTL_INDICATOR_STATE_ON);
2176 2176 else if (led == PCIE_HP_ATTN_LED)
2177 2177 control = pcie_slotctl_attn_indicator_set(control,
2178 2178 PCIE_SLOTCTL_INDICATOR_STATE_ON);
2179 2179 break;
2180 2180 case PCIE_HP_LED_OFF:
2181 2181 if (led == PCIE_HP_POWER_LED)
2182 2182 control = pcie_slotctl_pwr_indicator_set(control,
2183 2183 PCIE_SLOTCTL_INDICATOR_STATE_OFF);
2184 2184 else if (led == PCIE_HP_ATTN_LED)
2185 2185 control = pcie_slotctl_attn_indicator_set(control,
2186 2186 PCIE_SLOTCTL_INDICATOR_STATE_OFF);
2187 2187 break;
2188 2188 case PCIE_HP_LED_BLINK:
2189 2189 if (led == PCIE_HP_POWER_LED)
2190 2190 control = pcie_slotctl_pwr_indicator_set(control,
2191 2191 PCIE_SLOTCTL_INDICATOR_STATE_BLINK);
2192 2192 else if (led == PCIE_HP_ATTN_LED)
2193 2193 control = pcie_slotctl_attn_indicator_set(control,
2194 2194 PCIE_SLOTCTL_INDICATOR_STATE_BLINK);
2195 2195 break;
2196 2196
2197 2197 default:
2198 2198 PCIE_DBG("pciehpc_set_led_state() invalid LED state %d\n",
2199 2199 state);
2200 2200 return;
2201 2201 }
2202 2202
2203 2203 /* update the Slot Control Register */
2204 2204 pciehpc_issue_hpc_command(ctrl_p, control);
2205 2205
2206 2206 #ifdef DEBUG
2207 2207 /* get the current state of Slot Control register */
2208 2208 control = pciehpc_reg_get16(ctrl_p,
2209 2209 bus_p->bus_pcie_off + PCIE_SLOTCTL);
2210 2210
2211 2211 PCIE_DBG("pciehpc_set_led_state: slot %d power-led %s attn-led %s\n",
2212 2212 slot_p->hs_phy_slot_num, pcie_led_state_text(
2213 2213 pciehpc_led_state_to_hpc(pcie_slotctl_pwr_indicator_get(control))),
2214 2214 pcie_led_state_text(pciehpc_led_state_to_hpc(
2215 2215 pcie_slotctl_attn_indicator_get(control))));
2216 2216 #endif
2217 2217 }
2218 2218
2219 2219 static void
2220 2220 pciehpc_handle_power_fault(dev_info_t *dip)
2221 2221 {
2222 2222 /*
2223 2223 * Hold the parent's ref so that it won't disappear when the taskq is
2224 2224 * scheduled to run.
2225 2225 */
2226 2226 ndi_hold_devi(dip);
2227 2227
2228 2228 if (!taskq_dispatch(system_taskq, pciehpc_power_fault_handler, dip,
2229 2229 TQ_NOSLEEP)) {
2230 2230 ndi_rele_devi(dip);
2231 2231 PCIE_DBG("pciehpc_intr(): "
2232 2232 "Failed to dispatch power fault handler, dip %p\n", dip);
2233 2233 }
2234 2234 }
2235 2235
2236 2236 static void
2237 2237 pciehpc_power_fault_handler(void *arg)
2238 2238 {
2239 2239 dev_info_t *dip = (dev_info_t *)arg;
2240 2240 pcie_hp_ctrl_t *ctrl_p;
2241 2241 pcie_hp_slot_t *slot_p;
2242 2242
2243 2243 /* get the soft state structure for this dip */
2244 2244 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL) {
2245 2245 ndi_rele_devi(dip);
2246 2246 return;
2247 2247 }
2248 2248 slot_p = ctrl_p->hc_slots[0];
2249 2249
2250 2250 /*
2251 2251 * Send the event to DDI Hotplug framework, power off
2252 2252 * the slot
2253 2253 */
2254 2254 (void) ndi_hp_state_change_req(dip,
2255 2255 slot_p->hs_info.cn_name,
2256 2256 DDI_HP_CN_STATE_EMPTY, DDI_HP_REQ_SYNC);
2257 2257
2258 2258 mutex_enter(&ctrl_p->hc_mutex);
2259 2259 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED,
2260 2260 PCIE_HP_LED_ON);
2261 2261 mutex_exit(&ctrl_p->hc_mutex);
2262 2262 ndi_rele_devi(dip);
2263 2263 }
2264 2264
2265 2265 #ifdef DEBUG
2266 2266 /*
2267 2267 * Dump PCI-E Hot Plug registers.
2268 2268 */
2269 2269 static void
2270 2270 pciehpc_dump_hpregs(pcie_hp_ctrl_t *ctrl_p)
2271 2271 {
2272 2272 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
2273 2273 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2274 2274 uint16_t control;
2275 2275 uint32_t capabilities;
2276 2276
2277 2277 if (!pcie_debug_flags)
2278 2278 return;
2279 2279
2280 2280 capabilities = pciehpc_reg_get32(ctrl_p,
2281 2281 bus_p->bus_pcie_off + PCIE_SLOTCAP);
2282 2282
2283 2283 control = pciehpc_reg_get16(ctrl_p,
2284 2284 bus_p->bus_pcie_off + PCIE_SLOTCTL);
2285 2285
2286 2286 PCIE_DBG("pciehpc_dump_hpregs: Found PCI-E hot plug slot %d\n",
2287 2287 slot_p->hs_phy_slot_num);
2288 2288
2289 2289 PCIE_DBG("Attention Button Present = %s\n",
2290 2290 capabilities & PCIE_SLOTCAP_ATTN_BUTTON ? "Yes":"No");
2291 2291
2292 2292 PCIE_DBG("Power controller Present = %s\n",
2293 2293 capabilities & PCIE_SLOTCAP_POWER_CONTROLLER ? "Yes":"No");
2294 2294
2295 2295 PCIE_DBG("MRL Sensor Present = %s\n",
2296 2296 capabilities & PCIE_SLOTCAP_MRL_SENSOR ? "Yes":"No");
2297 2297
2298 2298 PCIE_DBG("Attn Indicator Present = %s\n",
2299 2299 capabilities & PCIE_SLOTCAP_ATTN_INDICATOR ? "Yes":"No");
2300 2300
2301 2301 PCIE_DBG("Power Indicator Present = %s\n",
2302 2302 capabilities & PCIE_SLOTCAP_PWR_INDICATOR ? "Yes":"No");
2303 2303
2304 2304 PCIE_DBG("HotPlug Surprise = %s\n",
2305 2305 capabilities & PCIE_SLOTCAP_HP_SURPRISE ? "Yes":"No");
2306 2306
2307 2307 PCIE_DBG("HotPlug Capable = %s\n",
2308 2308 capabilities & PCIE_SLOTCAP_HP_CAPABLE ? "Yes":"No");
2309 2309
2310 2310 PCIE_DBG("Physical Slot Number = %d\n",
2311 2311 PCIE_SLOTCAP_PHY_SLOT_NUM(capabilities));
2312 2312
2313 2313 PCIE_DBG("Attn Button interrupt Enabled = %s\n",
2314 2314 control & PCIE_SLOTCTL_ATTN_BTN_EN ? "Yes":"No");
2315 2315
2316 2316 PCIE_DBG("Power Fault interrupt Enabled = %s\n",
2317 2317 control & PCIE_SLOTCTL_PWR_FAULT_EN ? "Yes":"No");
2318 2318
2319 2319 PCIE_DBG("MRL Sensor INTR Enabled = %s\n",
2320 2320 control & PCIE_SLOTCTL_MRL_SENSOR_EN ? "Yes":"No");
2321 2321
2322 2322 PCIE_DBG("Presence interrupt Enabled = %s\n",
2323 2323 control & PCIE_SLOTCTL_PRESENCE_CHANGE_EN ? "Yes":"No");
2324 2324
2325 2325 PCIE_DBG("Cmd Complete interrupt Enabled = %s\n",
2326 2326 control & PCIE_SLOTCTL_CMD_INTR_EN ? "Yes":"No");
2327 2327
2328 2328 PCIE_DBG("HotPlug interrupt Enabled = %s\n",
2329 2329 control & PCIE_SLOTCTL_HP_INTR_EN ? "Yes":"No");
2330 2330
2331 2331 PCIE_DBG("Power Indicator LED = %s", pcie_led_state_text(
2332 2332 pciehpc_led_state_to_hpc(pcie_slotctl_pwr_indicator_get(control))));
2333 2333
2334 2334 PCIE_DBG("Attn Indicator LED = %s\n",
2335 2335 pcie_led_state_text(pciehpc_led_state_to_hpc(
2336 2336 pcie_slotctl_attn_indicator_get(control))));
2337 2337 }
2338 2338 #endif /* DEBUG */
↓ open down ↓ |
1049 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX