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--- old/usr/src/uts/common/sys/fibre-channel/fca/qlge/qlge.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/qlge/qlge.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2010 QLogic Corporation. All rights reserved.
24 24 */
25 25
26 26 #ifndef _QLGE_H
27 27 #define _QLGE_H
28 28
29 29 #ifdef __cplusplus
30 30 extern "C" {
31 31 #endif
32 32
33 33 #include <sys/ddi.h>
34 34 #include <sys/sunddi.h>
35 35 #include <sys/sunmdi.h>
36 36 #include <sys/modctl.h>
37 37 #include <sys/pci.h>
38 38 #include <sys/dlpi.h>
39 39 #include <sys/sdt.h>
40 40 #include <sys/mac_provider.h>
41 41 #include <sys/mac.h>
42 42 #include <sys/mac_flow.h>
43 43 #include <sys/mac_ether.h>
44 44 #include <sys/vlan.h>
45 45 #include <sys/netlb.h>
46 46 #include <sys/kmem.h>
47 47 #include <sys/file.h>
48 48 #include <sys/proc.h>
49 49 #include <sys/callb.h>
50 50 #include <sys/disp.h>
51 51 #include <sys/strsun.h>
52 52 #include <sys/ethernet.h>
53 53 #include <sys/miiregs.h>
54 54 #include <sys/kstat.h>
55 55 #include <sys/byteorder.h>
56 56 #include <sys/ddifm.h>
57 57 #include <sys/fm/protocol.h>
58 58 #include <sys/fm/util.h>
59 59 #include <sys/fm/io/ddi.h>
60 60
61 61 #include <qlge_hw.h>
62 62 #include <qlge_dbg.h>
63 63 #include <qlge_open.h>
64 64
65 65 #define ADAPTER_NAME "qlge"
66 66
67 67 /*
68 68 * Local Macro Definitions.
69 69 */
70 70 #ifdef TRUE
71 71 #undef TRUE
72 72 #endif
73 73 #define TRUE 1
74 74
75 75 #ifdef FALSE
76 76 #undef FALSE
77 77 #endif
78 78 #define FALSE 0
79 79
80 80 /* #define QLGE_TRACK_BUFFER_USAGE */
81 81 /*
82 82 * byte order, sparc is big endian, x86 is little endian,
83 83 * but PCI is little endian only
84 84 */
85 85 #ifdef sparc
86 86 #define cpu_to_le64(x) BSWAP_64(x)
87 87 #define cpu_to_le32(x) BSWAP_32(x)
88 88 #define cpu_to_le16(x) BSWAP_16(x)
89 89 #define le64_to_cpu(x) cpu_to_le64(x)
90 90 #define le32_to_cpu(x) cpu_to_le32(x)
91 91 #define le16_to_cpu(x) cpu_to_le16(x)
92 92 #else
93 93 #define cpu_to_le64(x) (x)
94 94 #define cpu_to_le32(x) (x)
95 95 #define cpu_to_le16(x) (x)
96 96 #define le64_to_cpu(x) (x)
97 97 #define le32_to_cpu(x) (x)
98 98 #define le16_to_cpu(x) (x)
99 99 #endif
100 100
101 101 /*
102 102 * Macros to help code, maintain, etc.
103 103 */
104 104
105 105 #define LSB(x) (uint8_t)(x)
106 106 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8)
107 107
108 108 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16)
109 109 #define LSW(x) (uint16_t)(x)
110 110
111 111 #define MS32(x) (uint32_t)((uint32_t)(x) >> 32)
112 112 #define LS32(x) (uint32_t)(x)
113 113
114 114 #define MSW_LSB(x) (uint8_t)(LSB(MSW(x)))
115 115 #define MSW_MSB(x) (uint8_t)(MSB(MSW(x)))
116 116
117 117 #define LSD(x) (uint32_t)(x)
118 118 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32)
119 119
120 120 #define SHORT_TO_LONG(a, b) (uint32_t)((uint16_t)b << 16 | (uint16_t)a)
121 121 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
122 122
123 123 #define SWAP_ENDIAN_16(x) ((LSB(x) << 8) | MSB(x))
124 124
125 125 #define SWAP_ENDIAN_32(x) ((SWAP_ENDIAN_16(LSW(x)) << 16) | \
126 126 SWAP_ENDIAN_16(MSW(x)))
127 127
128 128 #define SWAP_ENDIAN_64(x) ((SWAP_ENDIAN_32(LS32(x)) << 32) | \
129 129 SWAP_ENDIAN_32(MS32(x)))
130 130
131 131 #define QL_MIN(x, y) ((x < y) ? x : y)
132 132
133 133 #define CARRIER_ON(qlge) mac_link_update((qlge)->mh, LINK_STATE_UP)
134 134 #define CARRIER_OFF(qlge) mac_link_update((qlge)->mh, LINK_STATE_DOWN)
135 135
136 136 /*
137 137 * qlge local function return status codes
138 138 */
139 139 #define QL_ERROR 1
140 140 #define QL_SUCCESS 0
141 141 /*
142 142 * Solaris version compatibility definitions.
143 143 */
144 144 #define QL_GET_LBOLT(timer) timer = ddi_get_lbolt()
145 145 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff
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146 146 #define QL_DRIVER_NAME(dip) ddi_driver_name(ddi_get_parent(dip))
147 147
148 148 #define MINOR_NODE_FLAG 8
149 149
150 150 /*
151 151 * Host adapter default definitions.
152 152 */
153 153
154 154 /* Timeout timer counts in seconds (must greater than 1 second). */
155 155 #define USEC_PER_TICK drv_hztousec(1)
156 -#define TICKS_PER_SEC drv_usectohz(1000000)
156 +#define TICKS_PER_SEC drv_sectohz(1)
157 157 #define QL_ONE_SEC_DELAY 1000000
158 158 #define QL_ONE_MSEC_DELAY 1000
159 159 #define TX_TIMEOUT 3*TICKS_PER_SEC
160 160 /*
161 161 * DMA attributes definitions.
162 162 */
163 163 #define QL_DMA_LOW_ADDRESS (uint64_t)0
164 164 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffffull
165 165 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff
166 166 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8
167 167 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3
168 168 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64
169 169 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6
170 170 #define QL_DMA_BURSTSIZES 0xfff
171 171 #define QL_DMA_MIN_XFER_SIZE 1
172 172 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff
173 173 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff
174 174 #define QL_DMA_GRANULARITY 1
175 175 #define QL_DMA_XFER_FLAGS 0
176 176 #define QL_MAX_COOKIES 16
177 177
178 178 /*
179 179 * ISP PCI Configuration.
180 180 */
181 181 #define QL_INTR_INTERVAL 128 /* default interrupt interval 128us */
182 182 #define QL_INTR_PKTS 8 /* default packet count threshold 8us */
183 183
184 184 /* GLD */
185 185 #define QL_STREAM_OPS(dev_ops, attach, detach) \
186 186 DDI_DEFINE_STREAM_OPS(dev_ops, nulldev, nulldev, attach, detach, \
187 187 nodev, NULL, D_MP, NULL, ql_quiesce)
188 188
189 189 #define QL_GET_DEV(dip) ((qlge_t *)(ddi_get_driver_private(dip)))
190 190 #define RESUME_TX(tx_ring) mac_tx_update(tx_ring->qlge->mh);
191 191 #define RX_UPSTREAM(rx_ring, mp) mac_rx(rx_ring->qlge->mh, \
192 192 rx_ring->qlge->handle, mp);
193 193
194 194 /* GLD DMA */
195 195 extern ddi_device_acc_attr_t ql_dev_acc_attr;
196 196 extern ddi_device_acc_attr_t ql_desc_acc_attr;
197 197 extern ddi_device_acc_attr_t ql_buf_acc_attr;
198 198
199 199 struct dma_info {
200 200 void *vaddr;
201 201 ddi_dma_handle_t dma_handle;
202 202 ddi_acc_handle_t acc_handle;
203 203 uint64_t dma_addr;
204 204 size_t mem_len; /* allocated size */
205 205 offset_t offset; /* relative to handle */
206 206 };
207 207
208 208 /*
209 209 * Sync a DMA area described by a dma_info
210 210 */
211 211 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle, \
212 212 (area).offset, (area).mem_len, (flag)))
213 213
214 214 /*
215 215 * Find the (kernel virtual) address of block of memory
216 216 * described by a dma_info
217 217 */
218 218 #define DMA_VPTR(area) ((area).vaddr)
219 219
220 220 /*
221 221 * Zero a block of memory described by a dma_info
222 222 */
223 223 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).mem_len)
224 224
225 225 #define MAX_SG_ELEMENTS 16
226 226 #define QL_MAX_TX_DMA_HANDLES MAX_SG_ELEMENTS
227 227 #define TOTAL_SG_ELEMENTS (MAX_SG_ELEMENTS + TX_DESC_PER_IOCB)
228 228
229 229 /*
230 230 * ISP PCI Configuration.
231 231 */
232 232
233 233 /* Initialize steps */
234 234 #define INIT_SOFTSTATE_ALLOC BIT_0
235 235 #define INIT_REGS_SETUP BIT_1
236 236 #define INIT_DOORBELL_REGS_SETUP BIT_2
237 237 #define INIT_MAC_ALLOC BIT_3
238 238 #define INIT_PCI_CONFIG_SETUP BIT_4
239 239 #define INIT_SETUP_RINGS BIT_5
240 240 #define INIT_MEMORY_ALLOC BIT_6
241 241 #define INIT_INTR_ALLOC BIT_7
242 242 #define INIT_ADD_INTERRUPT BIT_8
243 243 #define INIT_LOCKS_CREATED BIT_9
244 244 #define INIT_ADD_SOFT_INTERRUPT BIT_10
245 245 #define INIT_MUTEX BIT_11
246 246 #define ADAPTER_INIT BIT_12
247 247 #define INIT_MAC_REGISTERED BIT_13
248 248 #define INIT_KSTATS BIT_14
249 249 #define INIT_FM BIT_15
250 250 #define INIT_ADAPTER_UP BIT_16
251 251 #define INIT_ALLOC_RX_BUF BIT_17
252 252 #define INIT_INTR_ENABLED BIT_18
253 253
254 254
255 255 #define LS_64BITS(x) (uint32_t)(0xffffffff & ((uint64_t)x))
256 256 #define MS_64BITS(x) (uint32_t)(0xffffffff & (((uint64_t)x)>>16>>16))
257 257
258 258 typedef uint64_t dma_addr_t;
259 259 extern int ql_quiesce(dev_info_t *dip);
260 260
261 261 /*
262 262 * LSO can support up to 65535 bytes of data, but can not be sent in one IOCB
263 263 * which only has 8 TX OALs, additional OALs must be applied separately.
264 264 */
265 265 #define QL_LSO_MAX 65535 /* Maximum supported LSO data Length */
266 266
267 267 enum tx_mode_t {
268 268 USE_DMA,
269 269 USE_COPY
270 270 };
271 271
272 272 #define QL_MAX_COPY_LENGTH 256
273 273
274 274 #define MAX_FRAGMENTS_IN_IOCB 7
275 275
276 276 #ifndef VLAN_ID_MASK
277 277 #define VLAN_ID_MASK 0x0fffu
278 278 #endif
279 279 #ifndef VLAN_TAGSZ
280 280 #define VLAN_TAGSZ 4
281 281 #endif
282 282
283 283 #ifndef ETHERTYPE_VLAN
284 284 #define ETHERTYPE_VLAN 0x8100
285 285 #endif
286 286
287 287 #ifndef MBLKL
288 288 #define MBLKL(mp) ((uintptr_t)(mp)->b_wptr - (uintptr_t)(mp)->b_rptr)
289 289 #endif
290 290 /*
291 291 * Checksum Offload
292 292 */
293 293 #define TCP_CKSUM_OFFSET 16
294 294 #define UDP_CKSUM_OFFSET 6
295 295 #define IPPROTO_IPv6OVERv4 41
296 296
297 297 /*
298 298 * Driver must be in one of these states
299 299 */
300 300 enum mac_state {
301 301 QL_MAC_INIT, /* in the initialization stage */
302 302 QL_MAC_ATTACHED, /* driver attached */
303 303 QL_MAC_STARTED, /* interrupt enabled, driver is ready */
304 304 QL_MAC_BRINGDOWN, /* in the bring down process */
305 305 QL_MAC_STOPPED, /* stoped, no more interrupts */
306 306 QL_MAC_DETACH, /* to be detached */
307 307 QL_MAC_SUSPENDED
308 308 };
309 309
310 310 /*
311 311 * Soft Request Flag
312 312 */
313 313 #define NEED_HW_RESET BIT_0 /* need hardware reset */
314 314 #define NEED_MPI_RESET BIT_1 /* need MPI RISC reset */
315 315
316 316 /*
317 317 * (Internal) return values from ioctl subroutines
318 318 */
319 319 enum ioc_reply {
320 320 IOC_INVAL = -1, /* bad, NAK with EINVAL */
321 321 IOC_DONE, /* OK, reply sent */
322 322 IOC_ACK, /* OK, just send ACK */
323 323 IOC_REPLY, /* OK, just send reply */
324 324 IOC_RESTART_ACK, /* OK, restart & ACK */
325 325 IOC_RESTART_REPLY /* OK, restart & reply */
326 326 };
327 327
328 328 /*
329 329 * Link Speed,in Mbps
330 330 */
331 331 #define SPEED_10 10
332 332 #define SPEED_100 100
333 333 #define SPEED_1000 1000
334 334 #define SPEED_10G 10000
335 335
336 336 /*
337 337 * Multicast List
338 338 */
339 339 typedef struct {
340 340 struct ether_addr addr;
341 341 unsigned char reserved[2];
342 342 } ql_multicast_addr;
343 343
344 344 #define MAX_MULTICAST_LIST_SIZE 128
345 345
346 346 typedef struct {
347 347 struct ether_addr addr; /* in canonical form */
348 348 boolean_t set; /* B_TRUE => valid */
349 349 } qlge_mac_addr_t;
350 350
351 351 #define MAX_UNICAST_LIST_SIZE 128
352 352
353 353 /*
354 354 * Device kstate structure.
355 355 */
356 356 enum {
357 357 QL_KSTAT_CHIP = 0,
358 358 QL_KSTAT_LINK,
359 359 QL_KSTAT_REG,
360 360 QL_KSTAT_COUNT
361 361 };
362 362
363 363 /*
364 364 * Register Bit Set/Reset
365 365 */
366 366 enum {
367 367 BIT_SET = 0,
368 368 BIT_RESET
369 369 };
370 370
371 371 /*
372 372 * Flash Image Search State
373 373 */
374 374 enum { STOP_SEARCH, /* Image address bad, no more search */
375 375 CONTINUE_SEARCH, /* Image address ok, continue search */
376 376 LAST_IMAGE_FOUND /* Found last image and FLTDS address */
377 377 };
378 378
379 379 /*
380 380 * Loop Back Modes
381 381 */
382 382 enum { QLGE_LOOP_NONE,
383 383 QLGE_LOOP_INTERNAL_PARALLEL,
384 384 QLGE_LOOP_INTERNAL_SERIAL,
385 385 QLGE_LOOP_EXTERNAL_PHY
386 386 };
387 387
388 388 /* for soft state routine */
389 389 typedef struct {
390 390 offset_t index;
391 391 char *name;
392 392 } ql_ksindex_t;
393 393
394 394 struct bq_desc {
395 395 struct dma_info bd_dma;
396 396 struct bq_desc *next;
397 397 struct rx_ring *rx_ring;
398 398 mblk_t *mp;
399 399 frtn_t rx_recycle; /* recycle function - called after mp */
400 400 /* is to be freed by OS */
401 401 uint16_t index;
402 402 uint16_t free_buf; /* Set to indicate the buffer is */
403 403 /* being freed, new one should not */
404 404 /* be allocated */
405 405 uint32_t upl_inuse; /* buffer in use by upper layers */
406 406 };
407 407
408 408 #define VM_PAGE_SIZE 4096
409 409
410 410 #define QLGE_POLL_ALL -1
411 411
412 412 #define SMALL_BUFFER_SIZE 512
413 413 #define LARGE_BUFFER_SIZE 4096
414 414
415 415 #define MAX_TX_WAIT_COUNT 1000
416 416 #define MAX_RX_WAIT_COUNT 25 /* 25 second */
417 417
418 418 #define MIN_BUFFERS_ARM_COUNT 16
419 419 #define MIN_BUFFERS_FREE_COUNT 32 /* If free buffer count go over this */
420 420 /* value, arm the chip */
421 421 /* if less than 16 free lrg buf nodes in the free list, then */
422 422 /* rx has to use copy method to send packets upstream */
423 423 #define RX_COPY_MODE_THRESHOLD (MIN_BUFFERS_ARM_COUNT/4)
424 424 /* if there are more than TX_STOP_THRESHOLD free tx buffers, try to send it */
425 425 #define TX_STOP_THRESHOLD 16
426 426 #define TX_RESUME_THRESHOLD 8
427 427
428 428 struct tx_ring_desc {
429 429 struct ob_mac_iocb_req *queue_entry; /* tx descriptor of this */
430 430 struct dma_info dma_mem_area; /* tx buffer */
431 431 ddi_dma_handle_t tx_dma_handle[QL_MAX_TX_DMA_HANDLES];
432 432 int tx_dma_handle_used;
433 433 enum tx_mode_t tx_type; /* map mode or copy mode */
434 434 mblk_t *mp; /* requested sending packet */
435 435 uint32_t index;
436 436 caddr_t copy_buffer;
437 437 uint64_t copy_buffer_dma_addr;
438 438 struct dma_info oal_dma; /* oal is premapped */
439 439 uint64_t oal_dma_addr; /* oal dma address premapped */
440 440 uint32_t tx_bytes;
441 441 void *oal;
442 442 };
443 443
444 444 struct tx_ring {
445 445 struct qlge *qlge;
446 446 struct dma_info wqicb_dma;
447 447 uint16_t cq_id; /* completion (rx) queue for */
448 448 /* tx completions */
449 449 uint8_t wq_id;
450 450 uint32_t wq_size;
451 451 uint32_t wq_len;
452 452 kmutex_t tx_lock;
453 453 struct dma_info wq_dma;
454 454 volatile uint32_t tx_free_count;
455 455 uint32_t tx_mode;
456 456 boolean_t queue_stopped; /* Tx no resource */
457 457 uint32_t *prod_idx_db_reg;
458 458 uint16_t prod_idx;
459 459 uint32_t *valid_db_reg; /* PCI doorbell mem area + 4 */
460 460 struct tx_ring_desc *wq_desc;
461 461 /* shadow copy of consumer idx */
462 462 uint32_t *cnsmr_idx_sh_reg;
463 463 /* dma-shadow copy consumer */
464 464 uint64_t cnsmr_idx_sh_reg_dma;
465 465 uint32_t defer; /* tx no resource */
466 466 uint64_t obytes;
467 467 uint64_t opackets;
468 468 uint32_t errxmt;
469 469 uint64_t brdcstxmt;
470 470 uint64_t multixmt;
471 471 uint64_t tx_fail_dma_bind;
472 472 uint64_t tx_no_dma_handle;
473 473 uint64_t tx_no_dma_cookie;
474 474
475 475 enum mac_state mac_flags;
476 476 };
477 477
478 478 struct bq_element {
479 479 uint32_t addr_lo;
480 480 uint32_t addr_hi;
481 481 };
482 482
483 483 /*
484 484 * Type of inbound queue.
485 485 */
486 486 enum {
487 487 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
488 488 TX_Q = 3, /* Handles outbound completions. */
489 489 RX_Q = 4, /* Handles inbound completions. */
490 490 };
491 491
492 492 struct rx_ring {
493 493 struct dma_info cqicb_dma;
494 494
495 495 /* GLD required flags */
496 496 uint64_t ring_gen_num;
497 497 /* statistics */
498 498 uint64_t rx_packets;
499 499 uint64_t rx_bytes;
500 500 uint32_t frame_too_long;
501 501 uint32_t frame_too_short;
502 502 uint32_t fcs_err;
503 503 uint32_t rx_packets_dropped_no_buffer;
504 504 uint32_t rx_pkt_dropped_mac_unenabled;
505 505 volatile uint32_t rx_indicate;
506 506
507 507 /* miscellaneous */
508 508 int type; /* DEFAULT_Q, TX_Q, RX_Q */
509 509 kmutex_t rx_lock;
510 510 uint32_t irq;
511 511 struct qlge *qlge;
512 512 uint32_t cpu; /* Which CPU this should run on. */
513 513 enum mac_state mac_flags;
514 514 /* completion queue */
515 515 struct dma_info cq_dma; /* virtual addr and phy addr */
516 516 uint32_t cq_size;
517 517 uint32_t cq_len;
518 518 uint16_t cq_id;
519 519 off_t prod_idx_sh_reg_offset;
520 520 volatile uint32_t *prod_idx_sh_reg; /* Shadowed prod reg */
521 521 uint64_t prod_idx_sh_reg_dma; /* Physical address */
522 522 uint32_t *cnsmr_idx_db_reg; /* PCI db mem area 0 */
523 523 uint32_t cnsmr_idx; /* current sw idx */
524 524 struct net_rsp_iocb *curr_entry; /* next entry on queue */
525 525 uint32_t *valid_db_reg; /* PCI doorbell mem area + 4 */
526 526
527 527 /* large buffer queue */
528 528 uint32_t lbq_len; /* entry count */
529 529 uint32_t lbq_size; /* size in bytes */
530 530 uint32_t lbq_buf_size;
531 531 struct dma_info lbq_dma; /* lbq dma info */
532 532 uint64_t *lbq_base_indirect;
533 533 uint64_t lbq_base_indirect_dma;
534 534 kmutex_t lbq_lock;
535 535 struct bq_desc **lbuf_in_use;
536 536 volatile uint32_t lbuf_in_use_count;
537 537 struct bq_desc **lbuf_free;
538 538 volatile uint32_t lbuf_free_count; /* free lbuf desc cnt */
539 539 uint32_t *lbq_prod_idx_db_reg; /* PCI db mem area+0x18 */
540 540 uint32_t lbq_prod_idx; /* current sw prod idx */
541 541 uint32_t lbq_curr_idx; /* next entry we expect */
542 542 uint32_t lbq_free_tail; /* free tail */
543 543 uint32_t lbq_free_head; /* free head */
544 544 uint32_t lbq_use_tail; /* inuse tail */
545 545 uint32_t lbq_use_head; /* inuse head */
546 546
547 547 struct bq_desc *lbq_desc;
548 548
549 549 /* small buffer queue */
550 550 uint32_t sbq_len; /* entry count */
551 551 uint32_t sbq_size; /* size in bytes of queue */
552 552 uint32_t sbq_buf_size;
553 553 struct dma_info sbq_dma; /* sbq dma info */
554 554 uint64_t *sbq_base_indirect;
555 555 uint64_t sbq_base_indirect_dma;
556 556 kmutex_t sbq_lock;
557 557 struct bq_desc **sbuf_in_use;
558 558 volatile uint32_t sbuf_in_use_count;
559 559 struct bq_desc **sbuf_free;
560 560 volatile uint32_t sbuf_free_count; /* free buffer desc cnt */
561 561 uint32_t *sbq_prod_idx_db_reg; /* PCI db mem area+0x1c */
562 562 uint32_t sbq_prod_idx; /* current sw prod idx */
563 563 uint32_t sbq_curr_idx; /* next entry we expect */
564 564 uint32_t sbq_free_tail; /* free tail */
565 565 uint32_t sbq_free_head; /* free head */
566 566 uint32_t sbq_use_tail; /* inuse tail */
567 567 uint32_t sbq_use_head; /* inuse head */
568 568 struct bq_desc *sbq_desc;
569 569 /* for test purpose */
570 570 uint32_t rx_failed_sbq_allocs;
571 571 uint32_t rx_failed_lbq_allocs;
572 572 uint32_t sbuf_copy_count;
573 573 uint32_t lbuf_copy_count;
574 574
575 575 #ifdef QLGE_PERFORMANCE
576 576 uint32_t hist[8];
577 577 #endif
578 578 };
579 579
580 580 struct intr_ctx {
581 581 struct qlge *qlge;
582 582 uint32_t intr;
583 583 uint32_t hooked;
584 584 uint32_t intr_en_mask;
585 585 uint32_t intr_dis_mask;
586 586 uint32_t intr_read_mask;
587 587 /*
588 588 * It's incremented for
589 589 * each irq handler that is scheduled.
590 590 * When each handler finishes it
591 591 * decrements irq_cnt and enables
592 592 * interrupts if it's zero.
593 593 */
594 594 uint32_t irq_cnt;
595 595 uint_t (*handler)(caddr_t, caddr_t);
596 596 };
597 597
598 598 struct tx_buf_desc {
599 599 uint64_t addr;
600 600 uint32_t len;
601 601 #define TX_DESC_LEN_MASK 0x000fffff
602 602 #define TX_DESC_C 0x40000000
603 603 #define TX_DESC_E 0x80000000
604 604 };
605 605
606 606 typedef struct qlge {
607 607 /*
608 608 * Solaris adapter configuration data
609 609 */
610 610 dev_info_t *dip;
611 611 int instance;
612 612 ddi_acc_handle_t dev_handle;
613 613 caddr_t iobase;
614 614 ddi_acc_handle_t dev_doorbell_reg_handle;
615 615 caddr_t doorbell_reg_iobase;
616 616 pci_cfg_t pci_cfg;
617 617 ddi_acc_handle_t pci_handle;
618 618 uint32_t page_size;
619 619 uint32_t sequence;
620 620 struct intr_ctx intr_ctx[MAX_RX_RINGS];
621 621 struct dma_info ricb_dma;
622 622 /* fault management capabilities */
623 623 int fm_capabilities;
624 624 boolean_t fm_enable;
625 625 enum mac_state mac_flags;
626 626
627 627 volatile uint32_t cfg_flags;
628 628
629 629 #define CFG_JUMBLE_PACKET BIT_1
630 630 #define CFG_RX_COPY_MODE BIT_2
631 631 #define CFG_SUPPORT_MULTICAST BIT_3
632 632 #define CFG_HW_UNABLE_PSEUDO_HDR_CKSUM BIT_4
633 633 #define CFG_CKSUM_HEADER_IPv4 BIT_5
634 634 #define CFG_CKSUM_PARTIAL BIT_6
635 635 #define CFG_CKSUM_FULL_IPv4 BIT_7
636 636 #define CFG_CKSUM_FULL_IPv6 BIT_8
637 637 #define CFG_LSO BIT_9
638 638 #define CFG_SUPPORT_SCATTER_GATHER BIT_10
639 639 #define CFG_ENABLE_SPLIT_HEADER BIT_11
640 640 #define CFG_ENABLE_EXTENDED_LOGGING BIT_15
641 641 uint32_t chksum_cap;
642 642 volatile uint32_t flags;
643 643 #define CFG_CHIP_8100 BIT_16
644 644
645 645 #define CFG_IST(qlge, cfgflags) (qlge->cfg_flags & cfgflags)
646 646
647 647 /* For Shadow Registers, used by adapter to write to host memory */
648 648 struct dma_info host_copy_shadow_dma_attr;
649 649 /*
650 650 * Extra 2x8 bytes memory saving large/small buf queue base address
651 651 * for each CQICB and read by chip, new request since 8100
652 652 */
653 653 struct dma_info buf_q_ptr_base_addr_dma_attr;
654 654 /*
655 655 * Debugging
656 656 */
657 657 uint32_t ql_dbgprnt;
658 658 /*
659 659 * GLD
660 660 */
661 661 mac_handle_t mh;
662 662 mac_resource_handle_t handle;
663 663 ql_stats_t stats;
664 664 kstat_t *ql_kstats[QL_KSTAT_COUNT];
665 665 /*
666 666 * mutex
667 667 */
668 668 kmutex_t gen_mutex; /* general adapter mutex */
669 669 kmutex_t hw_mutex; /* common hw(nvram)access */
670 670
671 671 /*
672 672 * Generic timer
673 673 */
674 674 timeout_id_t ql_timer_timeout_id;
675 675 clock_t ql_timer_ticks;
676 676
677 677 /*
678 678 * Interrupt
679 679 */
680 680 int intr_type;
681 681 /* for legacy interrupt */
682 682 ddi_iblock_cookie_t iblock_cookie;
683 683 /* for MSI and Fixed interrupts */
684 684 ddi_intr_handle_t *htable; /* For array of interrupts */
685 685 int intr_cnt; /* # of intrs actually allocated */
686 686 uint_t intr_pri; /* Interrupt priority */
687 687 int intr_cap; /* Interrupt capabilities */
688 688 size_t intr_size; /* size of the allocated */
689 689 /* interrupt handlers */
690 690 /* Power management context. */
691 691 uint8_t power_level;
692 692 #define LOW_POWER_LEVEL (BIT_1 | BIT_0)
693 693 #define MAX_POWER_LEVEL 0
694 694
695 695 /*
696 696 * General NIC
697 697 */
698 698 uint32_t xgmac_sem_mask;
699 699 uint32_t xgmac_sem_bits;
700 700 uint32_t func_number;
701 701 uint32_t fn0_net; /* network function 0 port */
702 702 uint32_t fn1_net; /* network function 1 port */
703 703
704 704 uint32_t mtu;
705 705 uint32_t max_frame_size;
706 706 uint32_t port_link_state;
707 707 uint32_t speed;
708 708 uint16_t link_type;
709 709 uint32_t duplex;
710 710 uint32_t pause; /* flow-control mode */
711 711 uint32_t loop_back_mode;
712 712 uint32_t lso_enable;
713 713 uint32_t dcbx_enable; /* dcbx mode */
714 714 /*
715 715 * PCI status
716 716 */
717 717 uint16_t vendor_id;
718 718 uint16_t device_id;
719 719
720 720 /*
721 721 * Multicast list
722 722 */
723 723 uint32_t multicast_list_count;
724 724 ql_multicast_addr multicast_list[MAX_MULTICAST_LIST_SIZE];
725 725 boolean_t multicast_promisc;
726 726 /*
727 727 * MAC address information
728 728 */
729 729 struct ether_addr dev_addr; /* ethernet address read from nvram */
730 730 qlge_mac_addr_t unicst_addr[MAX_UNICAST_LIST_SIZE];
731 731 uint32_t unicst_total; /* total unicst addresses */
732 732 uint32_t unicst_avail;
733 733 /*
734 734 * Soft Interrupt handlers
735 735 */
736 736 /* soft interrupt handle for MPI interrupt */
737 737 ddi_softint_handle_t mpi_event_intr_hdl;
738 738 /* soft interrupt handle for asic reset */
739 739 ddi_softint_handle_t asic_reset_intr_hdl;
740 740 /* soft interrupt handle for mpi reset */
741 741 ddi_softint_handle_t mpi_reset_intr_hdl;
742 742 /*
743 743 * IOCTL
744 744 */
745 745 /* new ioctl admin flags to work around the 1024 max data copy in&out */
746 746 caddr_t ioctl_buf_ptr;
747 747 uint32_t ioctl_buf_lenth;
748 748 uint16_t expected_trans_times;
749 749 uint32_t ioctl_total_length;
750 750 uint32_t ioctl_transferred_bytes;
751 751 ql_mpi_coredump_t ql_mpi_coredump;
752 752 /*
753 753 * Mailbox lock and flags
754 754 */
755 755 boolean_t fw_init_complete;
756 756 kmutex_t mbx_mutex;
757 757 boolean_t mbx_wait_completion;
758 758 kcondvar_t cv_mbx_intr;
759 759 mbx_data_t received_mbx_cmds;
760 760 uint_t max_read_mbx;
761 761 firmware_version_info_t fw_version_info;
762 762 phy_firmware_version_info_t phy_version_info;
763 763 port_cfg_info_t port_cfg_info;
764 764 struct dma_info ioctl_buf_dma_attr;
765 765
766 766 /*
767 767 * Flash
768 768 */
769 769 uint32_t flash_fltds_addr;
770 770 uint32_t flash_flt_fdt_index;
771 771 uint32_t flash_fdt_addr;
772 772 uint32_t flash_fdt_size;
773 773 uint32_t flash_flt_nic_config_table_index;
774 774 uint32_t flash_nic_config_table_addr;
775 775 uint32_t flash_nic_config_table_size;
776 776 uint32_t flash_vpd_addr;
777 777 ql_flash_info_t flash_info;
778 778 ql_fltds_t fltds;
779 779 ql_flt_t flt;
780 780 uint16_t flash_len; /* size of Flash memory */
781 781 ql_nic_config_t nic_config;
782 782 flash_desc_t fdesc;
783 783 /*
784 784 * TX / RX
785 785 */
786 786 clock_t last_tx_time;
787 787 boolean_t rx_copy;
788 788 uint16_t rx_coalesce_usecs;
789 789 uint16_t rx_max_coalesced_frames;
790 790 uint16_t tx_coalesce_usecs;
791 791 uint16_t tx_max_coalesced_frames;
792 792 uint32_t payload_copy_thresh;
793 793
794 794 uint32_t xg_sem_mask;
795 795
796 796 uint32_t ip_hdr_offset;
797 797 uint32_t selected_tx_ring;
798 798
799 799 struct rx_ring rx_ring[MAX_RX_RINGS];
800 800 struct tx_ring tx_ring[MAX_TX_RINGS];
801 801 uint32_t rx_polls[MAX_RX_RINGS];
802 802 uint32_t rx_interrupts[MAX_RX_RINGS];
803 803
804 804 int tx_ring_size;
805 805 int rx_ring_size;
806 806 uint32_t rx_copy_threshold;
807 807 uint32_t rx_ring_count;
808 808 uint32_t rss_ring_count;
809 809 uint32_t tx_ring_first_cq_id;
810 810 uint32_t tx_ring_count;
811 811 uint32_t isr_stride;
812 812 #ifdef QLGE_TRACK_BUFFER_USAGE
813 813 /* Count no of times the buffers fell below 32 */
814 814 uint32_t rx_sb_low_count[MAX_RX_RINGS];
815 815 uint32_t rx_lb_low_count[MAX_RX_RINGS];
816 816 uint32_t cq_low_count[MAX_RX_RINGS];
817 817 #endif
818 818 } qlge_t;
819 819
820 820
821 821 /*
822 822 * Reconfiguring the network devices requires the net_config privilege
823 823 * in Solaris 10+.
824 824 */
825 825 extern int secpolicy_net_config(const cred_t *, boolean_t);
826 826
827 827 /*
828 828 * Global Function Prototypes in qlge_dbg.c source file.
829 829 */
830 830 extern int ql_fw_dump(qlge_t *);
831 831 extern uint8_t ql_get8(qlge_t *, uint32_t);
832 832 extern uint16_t ql_get16(qlge_t *, uint32_t);
833 833 extern uint32_t ql_get32(qlge_t *, uint32_t);
834 834 extern void ql_put8(qlge_t *, uint32_t, uint8_t);
835 835 extern void ql_put16(qlge_t *, uint32_t, uint16_t);
836 836 extern void ql_put32(qlge_t *, uint32_t, uint32_t);
837 837 extern uint32_t ql_read_reg(qlge_t *, uint32_t);
838 838 extern void ql_write_reg(qlge_t *, uint32_t, uint32_t);
839 839 extern void ql_dump_all_contrl_regs(qlge_t *);
840 840 extern int ql_wait_reg_bit(qlge_t *, uint32_t, uint32_t, int, uint32_t);
841 841 extern void ql_dump_pci_config(qlge_t *);
842 842 extern void ql_dump_host_pci_regs(qlge_t *);
843 843 extern void ql_dump_req_pkt(qlge_t *, struct ob_mac_iocb_req *, void *, int);
844 844 extern void ql_dump_cqicb(qlge_t *, struct cqicb_t *);
845 845 extern void ql_dump_wqicb(qlge_t *, struct wqicb_t *);
846 846 extern void ql_gld3_init(qlge_t *, mac_register_t *);
847 847 enum ioc_reply ql_chip_ioctl(qlge_t *, queue_t *, mblk_t *);
848 848 enum ioc_reply ql_loop_ioctl(qlge_t *, queue_t *, mblk_t *, struct iocblk *);
849 849 extern int ql_8xxx_binary_core_dump(qlge_t *, ql_mpi_coredump_t *);
850 850 /*
851 851 * Global Data in qlge.c source file.
852 852 */
853 853 extern void qlge_delay(clock_t usecs);
854 854 extern int ql_sem_spinlock(qlge_t *, uint32_t);
855 855 extern void ql_sem_unlock(qlge_t *, uint32_t);
856 856 extern int ql_sem_lock(qlge_t *, uint32_t, uint32_t);
857 857 extern int ql_init_misc_registers(qlge_t *);
858 858 extern int ql_init_mem_resources(qlge_t *);
859 859 extern int ql_do_start(qlge_t *);
860 860 extern int ql_do_stop(qlge_t *);
861 861 extern int ql_add_to_multicast_list(qlge_t *, uint8_t *ep);
862 862 extern int ql_remove_from_multicast_list(qlge_t *, uint8_t *);
863 863 extern void ql_set_promiscuous(qlge_t *, int);
864 864 extern void ql_get_hw_stats(qlge_t *);
865 865 extern int ql_send_common(struct tx_ring *, mblk_t *);
866 866 extern void ql_wake_asic_reset_soft_intr(qlge_t *);
867 867 extern void ql_write_doorbell_reg(qlge_t *, uint32_t *, uint32_t);
868 868 extern uint32_t ql_read_doorbell_reg(qlge_t *, uint32_t *);
869 869 extern int ql_set_mac_addr_reg(qlge_t *, uint8_t *, uint32_t, uint16_t);
870 870 extern int ql_read_xgmac_reg(qlge_t *, uint32_t, uint32_t *);
871 871 extern void ql_enable_completion_interrupt(qlge_t *, uint32_t);
872 872 extern mblk_t *ql_ring_rx_poll(void *, int);
873 873 extern void ql_disable_completion_interrupt(qlge_t *qlge, uint32_t intr);
874 874 extern mblk_t *ql_ring_tx(void *arg, mblk_t *mp);
875 875 extern uint8_t ql_tx_hashing(qlge_t *qlge, caddr_t bp);
876 876 extern void ql_atomic_set_32(volatile uint32_t *target, uint32_t newval);
877 877 extern uint32_t ql_atomic_read_32(volatile uint32_t *target);
878 878 extern void ql_restart_timer(qlge_t *qlge);
879 879 extern int ql_route_initialize(qlge_t *);
880 880 /*
881 881 * Global Function Prototypes in qlge_flash.c source file.
882 882 */
883 883 extern int ql_sem_flash_lock(qlge_t *);
884 884 extern void ql_sem_flash_unlock(qlge_t *);
885 885 extern int qlge_load_flash(qlge_t *, uint8_t *, uint32_t, uint32_t);
886 886 extern int qlge_dump_fcode(qlge_t *, uint8_t *, uint32_t, uint32_t);
887 887 extern int ql_flash_vpd(qlge_t *qlge, uint8_t *buf);
888 888 extern int ql_get_flash_params(qlge_t *qlge);
889 889 /*
890 890 * Global Function Prototypes in qlge_mpi.c source file.
891 891 */
892 892 extern void ql_do_mpi_intr(qlge_t *qlge);
893 893 extern int ql_reset_mpi_risc(qlge_t *);
894 894 extern int ql_get_fw_state(qlge_t *, uint32_t *);
895 895 extern int qlge_get_link_status(qlge_t *, struct qlnic_link_status_info *);
896 896 extern int ql_mbx_test(qlge_t *qlge);
897 897 extern int ql_mbx_test2(qlge_t *qlge);
898 898 extern int ql_get_port_cfg(qlge_t *qlge);
899 899 extern int ql_set_mpi_port_config(qlge_t *qlge, port_cfg_info_t new_cfg);
900 900 extern int ql_set_loop_back_mode(qlge_t *qlge);
901 901 extern int ql_set_pause_mode(qlge_t *qlge);
902 902 extern int ql_get_LED_config(qlge_t *);
903 903 extern int ql_dump_sfp(qlge_t *, void *bp, int mode);
904 904 extern int ql_set_IDC_Req(qlge_t *, uint8_t dest_functions, uint8_t timeout);
905 905 extern void ql_write_flash_test(qlge_t *qlge, uint32_t testAddr);
906 906 extern void ql_write_flash_test2(qlge_t *qlge, uint32_t testAddr);
907 907 extern int ql_get_firmware_version(qlge_t *,
908 908 struct qlnic_mpi_version_info *);
909 909 extern int ql_read_processor_data(qlge_t *, uint32_t, uint32_t *);
910 910 extern int ql_write_processor_data(qlge_t *, uint32_t, uint32_t);
911 911 extern int ql_read_risc_ram(qlge_t *, uint32_t, uint64_t, uint32_t);
912 912 extern int ql_trigger_system_error_event(qlge_t *qlge);
913 913
914 914 extern void ql_core_dump(qlge_t *);
915 915 extern void ql_dump_crash_record(qlge_t *);
916 916 extern void ql_dump_buf(char *, uint8_t *, uint8_t, uint32_t);
917 917 extern void ql_printf(const char *, ...);
918 918
919 919 /*
920 920 * Global Function Prototypes in qlge_gld.c source file.
921 921 */
922 922 extern int ql_unicst_set(qlge_t *qlge, const uint8_t *macaddr, int slot);
923 923
924 924 /*
925 925 * Global Function Prototypes in qlge_fm.c source file.
926 926 */
927 927 extern void ql_fm_ereport(qlge_t *qlge, char *detail);
928 928 extern int ql_fm_check_acc_handle(ddi_acc_handle_t handle);
929 929 extern int ql_fm_check_dma_handle(ddi_dma_handle_t handle);
930 930
931 931
932 932 #ifdef __cplusplus
933 933 }
934 934 #endif
935 935
936 936 #endif /* _QLGE_H */
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