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bcm2835: move strict alignment check disable code into the loader
Since the loader wants to muck with alignment related bits of the SCTLR
anyway, it should set both A and U to the desired values (0 and 1
respectively).


  80          * code should never make use of these, and we want loud and violent
  81          * failure should we accidentally try.
  82          */
  83         cps #(CPU_MODE_UND)
  84         mov sp, #-1
  85         cps #(CPU_MODE_ABT)
  86         mov sp, #-1
  87         cps #(CPU_MODE_FIQ)
  88         mov sp, #-1
  89         cps #(CPU_MODE_IRQ)
  90         mov sp, #-1
  91         cps #(CPU_MODE_SVC)
  92 
  93         /* Enable highvecs (moves the base of the exception vector) */
  94         mrc     p15, 0, r3, c1, c0, 0
  95         mov     r4, #1
  96         lsl     r4, r4, #13
  97         orr     r3, r3, r4
  98         mcr     p15, 0, r3, c1, c0, 0
  99 
 100         /* Disable A (disables strict alignment checks) */
 101         mrc     p15, 0, r3, c1, c0, 0
 102         bic     r3, r3, #2
 103         mcr     p15, 0, r3, c1, c0, 0
 104 
 105         /* Enable access to p10 and p11 (privileged mode only) */
 106         mrc     p15, 0, r0, c1, c0, 2
 107         orr     r0, #0x00500000
 108         mcr     p15, 0, r0, c1, c0, 2
 109 
 110         bl _fakebop_start
 111         SET_SIZE(_start)
 112 
 113         ENTRY(arm_reg_read)
 114         ldr r0, [r0]
 115         bx lr
 116         SET_SIZE(arm_reg_read)
 117 
 118         ENTRY(arm_reg_write)
 119         str r1, [r0]
 120         bx lr
 121         SET_SIZE(arm_reg_write)



  80          * code should never make use of these, and we want loud and violent
  81          * failure should we accidentally try.
  82          */
  83         cps #(CPU_MODE_UND)
  84         mov sp, #-1
  85         cps #(CPU_MODE_ABT)
  86         mov sp, #-1
  87         cps #(CPU_MODE_FIQ)
  88         mov sp, #-1
  89         cps #(CPU_MODE_IRQ)
  90         mov sp, #-1
  91         cps #(CPU_MODE_SVC)
  92 
  93         /* Enable highvecs (moves the base of the exception vector) */
  94         mrc     p15, 0, r3, c1, c0, 0
  95         mov     r4, #1
  96         lsl     r4, r4, #13
  97         orr     r3, r3, r4
  98         mcr     p15, 0, r3, c1, c0, 0
  99 





 100         /* Enable access to p10 and p11 (privileged mode only) */
 101         mrc     p15, 0, r0, c1, c0, 2
 102         orr     r0, #0x00500000
 103         mcr     p15, 0, r0, c1, c0, 2
 104 
 105         bl _fakebop_start
 106         SET_SIZE(_start)
 107 
 108         ENTRY(arm_reg_read)
 109         ldr r0, [r0]
 110         bx lr
 111         SET_SIZE(arm_reg_read)
 112 
 113         ENTRY(arm_reg_write)
 114         str r1, [r0]
 115         bx lr
 116         SET_SIZE(arm_reg_write)