155 {}
156
157 void
158 armv6_text_flush_range(caddr_t start, size_t len)
159 {}
160
161 void
162 armv6_text_flush(void)
163 {}
164
165 #else /* __lint */
166
167 ENTRY(armv6_icache_enable)
168 mrc p15, 0, r0, c1, c0, 0
169 orr r0, #0x1000
170 mcr p15, 0, r0, c1, c0, 0
171 SET_SIZE(armv6_icache_enable)
172
173 ENTRY(armv6_dcache_enable)
174 mrc p15, 0, r0, c1, c0, 0
175 orr r0, #0x2
176 mcr p15, 0, r0, c1, c0, 0
177 SET_SIZE(armv6_dcache_enable)
178
179 ENTRY(armv6_icache_disable)
180 mrc p15, 0, r0, c1, c0, 0
181 bic r0, #0x1000
182 mcr p15, 0, r0, c1, c0, 0
183 SET_SIZE(armv6_icache_disable)
184
185 ENTRY(armv6_dcache_disable)
186 mrc p15, 0, r0, c1, c0, 0
187 bic r0, #0x2
188 mcr p15, 0, r0, c1, c0, 0
189 SET_SIZE(armv6_dcache_disable)
190
191 ENTRY(armv6_icache_inval)
192 mcr p15, 0, r0, c7, c5, 0 @ Invalidate i-cache
193 bx lr
194 SET_SIZE(armv6_icache_inval)
195
196 ENTRY(armv6_dcache_inval)
197 mcr p15, 0, r0, c7, c6, 0 @ Invalidate d-cache
198 ARM_DSB_INSTR(r2)
199 bx lr
200 SET_SIZE(armv6_dcache_inval)
201
202 ENTRY(armv6_dcache_flush)
203 mcr p15, 0, r0, c7, c10, 4 @ Flush d-cache
204 ARM_DSB_INSTR(r2)
205 bx lr
206 SET_SIZE(armv6_dcache_flush)
207
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155 {}
156
157 void
158 armv6_text_flush_range(caddr_t start, size_t len)
159 {}
160
161 void
162 armv6_text_flush(void)
163 {}
164
165 #else /* __lint */
166
167 ENTRY(armv6_icache_enable)
168 mrc p15, 0, r0, c1, c0, 0
169 orr r0, #0x1000
170 mcr p15, 0, r0, c1, c0, 0
171 SET_SIZE(armv6_icache_enable)
172
173 ENTRY(armv6_dcache_enable)
174 mrc p15, 0, r0, c1, c0, 0
175 orr r0, #0x4
176 mcr p15, 0, r0, c1, c0, 0
177 SET_SIZE(armv6_dcache_enable)
178
179 ENTRY(armv6_icache_disable)
180 mrc p15, 0, r0, c1, c0, 0
181 bic r0, #0x1000
182 mcr p15, 0, r0, c1, c0, 0
183 SET_SIZE(armv6_icache_disable)
184
185 ENTRY(armv6_dcache_disable)
186 mrc p15, 0, r0, c1, c0, 0
187 bic r0, #0x4
188 mcr p15, 0, r0, c1, c0, 0
189 SET_SIZE(armv6_dcache_disable)
190
191 ENTRY(armv6_icache_inval)
192 mcr p15, 0, r0, c7, c5, 0 @ Invalidate i-cache
193 bx lr
194 SET_SIZE(armv6_icache_inval)
195
196 ENTRY(armv6_dcache_inval)
197 mcr p15, 0, r0, c7, c6, 0 @ Invalidate d-cache
198 ARM_DSB_INSTR(r2)
199 bx lr
200 SET_SIZE(armv6_dcache_inval)
201
202 ENTRY(armv6_dcache_flush)
203 mcr p15, 0, r0, c7, c10, 4 @ Flush d-cache
204 ARM_DSB_INSTR(r2)
205 bx lr
206 SET_SIZE(armv6_dcache_flush)
207
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