58 SET_SIZE(fakeload_unaligned_enable);
59
60 #endif /* __lint */
61
62 #if defined(__lint)
63
64 fakeload_pt_setup(uintptr_t ptroot)
65 {}
66
67 #else /* __lint */
68
69 /*
70 * We need to set up the world for the first time. We'll do the
71 * following in order:
72 *
73 * o Set the TTBCR to always use TTBR0
74 * o Set domain 0 to manager mode
75 * o Program the Page table root
76 */
77 ENTRY(fakeload_pt_setup)
78 mov r1, #0
79 mcr p15, 0, r1, c2, c0, 2
80 mov r1, #3
81 mcr p15, 0, r1, c3, c0, 0
82 orr r0, r0, #0x1b
83 mcr p15, 0, r0, c2, c0, 0
84 bx lr
85 SET_SIZE(fakeload_pt_setup)
86
87 #endif /* __lint */
88
89 #if defined(__lint)
90
91 /* ARGSUSED */
92 void
93 fakeload_mmu_enable(void)
94 {}
95
96 #else /* __lint */
97
98 /*
99 * We first make sure that the ARMv6 pages are enabled (bit 23) and then
100 * enable the MMU (bit 0).
101 */
102 ENTRY(fakeload_mmu_enable)
103 mrc p15, 0, r0, c1, c0, 0
104 orr r0, #0x800000
105 mcr p15, 0, r0, c1, c0, 0
106 mrc p15, 0, r0, c1, c0, 0
107 orr r0, #0x1
108 mcr p15, 0, r0, c1, c0, 0
109 bx lr
110 SET_SIZE(fakeload_mmu_enable)
111 #endif /* __lint */
112
113
114 ENTRY(fakeload_exec)
115 blx r3
116 /* We should never execute this. If we do we'll go back to a panic */
117 bx lr
118 SET_SIZE(fakeload_exec)
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58 SET_SIZE(fakeload_unaligned_enable);
59
60 #endif /* __lint */
61
62 #if defined(__lint)
63
64 fakeload_pt_setup(uintptr_t ptroot)
65 {}
66
67 #else /* __lint */
68
69 /*
70 * We need to set up the world for the first time. We'll do the
71 * following in order:
72 *
73 * o Set the TTBCR to always use TTBR0
74 * o Set domain 0 to manager mode
75 * o Program the Page table root
76 */
77 ENTRY(fakeload_pt_setup)
78 /* use TTBR0 only (should already be true) */
79 mov r1, #0
80 mcr p15, 0, r1, c2, c0, 2
81
82 /* set domain 0 to manager mode */
83 mov r1, #3
84 mcr p15, 0, r1, c3, c0, 0
85
86 /* set TTBR0 to page table root */
87 orr r0, r0, #0x18 /* Outer WB, no WA Cachable */
88 orr r0, r0, #0x2 /* Sharable */
89 orr r0, r0, #0x1 /* Inner Cachable */
90 mcr p15, 0, r0, c2, c0, 0
91 bx lr
92 SET_SIZE(fakeload_pt_setup)
93
94 #endif /* __lint */
95
96 #if defined(__lint)
97
98 /* ARGSUSED */
99 void
100 fakeload_mmu_enable(void)
101 {}
102
103 #else /* __lint */
104
105 /*
106 * We first make sure that the ARMv6 pages are enabled (bit 23) and then
107 * enable the MMU (bit 0).
108 */
109 ENTRY(fakeload_mmu_enable)
110 mrc p15, 0, r0, c1, c0, 0
111 orr r0, #0x800000 /* enable ARMv6 pages */
112 orr r0, #0x1 /* enable MMU */
113 mcr p15, 0, r0, c1, c0, 0
114 bx lr
115 SET_SIZE(fakeload_mmu_enable)
116 #endif /* __lint */
117
118
119 ENTRY(fakeload_exec)
120 blx r3
121 /* We should never execute this. If we do we'll go back to a panic */
122 bx lr
123 SET_SIZE(fakeload_exec)
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