loader: document the page table setup
loader: simplify MMU enabling code

@@ -73,15 +73,22 @@
          * o Set the TTBCR to always use TTBR0
          * o Set domain 0 to manager mode
          * o Program the Page table root
          */
         ENTRY(fakeload_pt_setup)
+        /* use TTBR0 only (should already be true) */
         mov     r1, #0
         mcr     p15, 0, r1, c2, c0, 2
+
+        /* set domain 0 to manager mode */
         mov     r1, #3
         mcr     p15, 0, r1, c3, c0, 0
-        orr     r0, r0, #0x1b
+
+        /* set TTBR0 to page table root */
+        orr     r0, r0, #0x18           /* Outer WB, no WA Cachable */
+        orr     r0, r0, #0x2            /* Sharable */
+        orr     r0, r0, #0x1            /* Inner Cachable */
         mcr     p15, 0, r0, c2, c0, 0
         bx      lr
         SET_SIZE(fakeload_pt_setup)
 
 #endif /* __lint */

@@ -99,14 +106,12 @@
          * We first make sure that the ARMv6 pages are enabled (bit 23) and then
          * enable the MMU (bit 0).
          */
         ENTRY(fakeload_mmu_enable)
         mrc     p15, 0, r0, c1, c0, 0
-        orr     r0, #0x800000
-        mcr     p15, 0, r0, c1, c0, 0
-        mrc     p15, 0, r0, c1, c0, 0
-        orr     r0, #0x1
+        orr     r0, #0x800000           /* enable ARMv6 pages */
+        orr     r0, #0x1                /* enable MMU */
         mcr     p15, 0, r0, c1, c0, 0
         bx      lr
         SET_SIZE(fakeload_mmu_enable)
 #endif  /* __lint */