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loader: document the page table setup
loader: simplify MMU enabling code
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--- old/usr/src/uts/armv6/loader/fakeloader_core.s
+++ new/usr/src/uts/armv6/loader/fakeloader_core.s
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2013 (c) Joyent, Inc. All rights reserved.
14 14 * Copyright 2015 (c) Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
15 15 */
16 16
17 17 /*
18 18 * Every story needs a beginning, this is the loader's.
19 19 */
20 20
21 21 #include <sys/asm_linkage.h>
22 22
23 23 /*
24 24 * We put _start into the .text.init section so we can more easily shove it
25 25 * at the front of the .text.
26 26 */
27 27 .section .text.init
28 28 .align 4
29 29 .globl _start
30 30 .type _start, %function
31 31 _start:
32 32 mov sp, #0x8000
33 33 /*
34 34 * XXX manually fix up the tag start
35 35 */
36 36 mov r2, #0x100
37 37 bl fakeload_init
38 38 SET_SIZE(_start)
39 39
40 40 #if defined(__lint)
41 41
42 42 /* ARGSUSED */
43 43 void
44 44 fakeload_unaligned_enable(void)
45 45 {}
46 46
47 47 #else /* __lint */
48 48
49 49 /*
50 50 * Fix up alignment by turning off A and by turning on U.
51 51 */
52 52 ENTRY(fakeload_unaligned_enable)
53 53 mrc p15, 0, r0, c1, c0, 0
54 54 orr r0, #0x400000 /* U = 1 */
55 55 bic r0, r0, #2 /* A = 0 */
56 56 mcr p15, 0, r0, c1, c0, 0
57 57 bx lr
58 58 SET_SIZE(fakeload_unaligned_enable);
59 59
60 60 #endif /* __lint */
61 61
62 62 #if defined(__lint)
63 63
64 64 fakeload_pt_setup(uintptr_t ptroot)
65 65 {}
66 66
67 67 #else /* __lint */
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68 68
69 69 /*
70 70 * We need to set up the world for the first time. We'll do the
71 71 * following in order:
72 72 *
73 73 * o Set the TTBCR to always use TTBR0
74 74 * o Set domain 0 to manager mode
75 75 * o Program the Page table root
76 76 */
77 77 ENTRY(fakeload_pt_setup)
78 + /* use TTBR0 only (should already be true) */
78 79 mov r1, #0
79 80 mcr p15, 0, r1, c2, c0, 2
81 +
82 + /* set domain 0 to manager mode */
80 83 mov r1, #3
81 84 mcr p15, 0, r1, c3, c0, 0
82 - orr r0, r0, #0x1b
85 +
86 + /* set TTBR0 to page table root */
87 + orr r0, r0, #0x18 /* Outer WB, no WA Cachable */
88 + orr r0, r0, #0x2 /* Sharable */
89 + orr r0, r0, #0x1 /* Inner Cachable */
83 90 mcr p15, 0, r0, c2, c0, 0
84 91 bx lr
85 92 SET_SIZE(fakeload_pt_setup)
86 93
87 94 #endif /* __lint */
88 95
89 96 #if defined(__lint)
90 97
91 98 /* ARGSUSED */
92 99 void
93 100 fakeload_mmu_enable(void)
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94 101 {}
95 102
96 103 #else /* __lint */
97 104
98 105 /*
99 106 * We first make sure that the ARMv6 pages are enabled (bit 23) and then
100 107 * enable the MMU (bit 0).
101 108 */
102 109 ENTRY(fakeload_mmu_enable)
103 110 mrc p15, 0, r0, c1, c0, 0
104 - orr r0, #0x800000
105 - mcr p15, 0, r0, c1, c0, 0
106 - mrc p15, 0, r0, c1, c0, 0
107 - orr r0, #0x1
111 + orr r0, #0x800000 /* enable ARMv6 pages */
112 + orr r0, #0x1 /* enable MMU */
108 113 mcr p15, 0, r0, c1, c0, 0
109 114 bx lr
110 115 SET_SIZE(fakeload_mmu_enable)
111 116 #endif /* __lint */
112 117
113 118
114 119 ENTRY(fakeload_exec)
115 120 blx r3
116 121 /* We should never execute this. If we do we'll go back to a panic */
117 122 bx lr
118 123 SET_SIZE(fakeload_exec)
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