172
173 ENTRY(armv6_dcache_enable)
174 mrc p15, 0, r0, c1, c0, 0
175 orr r0, #0x4
176 mcr p15, 0, r0, c1, c0, 0
177 SET_SIZE(armv6_dcache_enable)
178
179 ENTRY(armv6_icache_disable)
180 mrc p15, 0, r0, c1, c0, 0
181 bic r0, #0x1000
182 mcr p15, 0, r0, c1, c0, 0
183 SET_SIZE(armv6_icache_disable)
184
185 ENTRY(armv6_dcache_disable)
186 mrc p15, 0, r0, c1, c0, 0
187 bic r0, #0x4
188 mcr p15, 0, r0, c1, c0, 0
189 SET_SIZE(armv6_dcache_disable)
190
191 ENTRY(armv6_icache_inval)
192 mcr p15, 0, r0, c7, c5, 0 @ Invalidate i-cache
193 bx lr
194 SET_SIZE(armv6_icache_inval)
195
196 ENTRY(armv6_dcache_inval)
197 mcr p15, 0, r0, c7, c6, 0 @ Invalidate d-cache
198 ARM_DSB_INSTR(r2)
199 bx lr
200 SET_SIZE(armv6_dcache_inval)
201
202 ENTRY(armv6_dcache_flush)
203 mcr p15, 0, r0, c7, c10, 4 @ Flush d-cache
204 ARM_DSB_INSTR(r2)
205 bx lr
206 SET_SIZE(armv6_dcache_flush)
207
208 ENTRY(armv6_text_flush_range)
209 add r1, r1, r0
210 sub r1, r1, r0
211 mcrr p15, 0, r1, r0, c5 @ Invalidate i-cache range
212 mcrr p15, 0, r1, r0, c12 @ Flush d-cache range
213 ARM_DSB_INSTR(r2)
214 ARM_ISB_INSTR(r2)
215 bx lr
216 SET_SIZE(armv6_text_flush_range)
217
218 ENTRY(armv6_text_flush)
219 mcr p15, 0, r0, c7, c5, 0 @ Invalidate i-cache
220 mcr p15, 0, r0, c7, c10, 4 @ Flush d-cache
221 ARM_DSB_INSTR(r2)
222 ARM_ISB_INSTR(r2)
223 bx lr
224 SET_SIZE(armv6_text_flush)
225
226 #endif
227
228 #ifdef __lint
229
230 /*
231 * Perform all of the operations necessary for tlb maintenance after an update
232 * to the page tables.
233 */
234 void
235 armv6_tlb_sync(void)
236 {}
237
238 #else /* __lint */
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172
173 ENTRY(armv6_dcache_enable)
174 mrc p15, 0, r0, c1, c0, 0
175 orr r0, #0x4
176 mcr p15, 0, r0, c1, c0, 0
177 SET_SIZE(armv6_dcache_enable)
178
179 ENTRY(armv6_icache_disable)
180 mrc p15, 0, r0, c1, c0, 0
181 bic r0, #0x1000
182 mcr p15, 0, r0, c1, c0, 0
183 SET_SIZE(armv6_icache_disable)
184
185 ENTRY(armv6_dcache_disable)
186 mrc p15, 0, r0, c1, c0, 0
187 bic r0, #0x4
188 mcr p15, 0, r0, c1, c0, 0
189 SET_SIZE(armv6_dcache_disable)
190
191 ENTRY(armv6_icache_inval)
192 mov r0, #0
193 mcr p15, 0, r0, c7, c5, 0 @ Invalidate i-cache
194 bx lr
195 SET_SIZE(armv6_icache_inval)
196
197 ENTRY(armv6_dcache_inval)
198 mov r0, #0
199 mcr p15, 0, r0, c7, c6, 0 @ Invalidate d-cache
200 ARM_DSB_INSTR(r2)
201 bx lr
202 SET_SIZE(armv6_dcache_inval)
203
204 ENTRY(armv6_dcache_flush)
205 mov r0, #0
206 mcr p15, 0, r0, c7, c10, 4 @ Flush d-cache
207 ARM_DSB_INSTR(r2)
208 bx lr
209 SET_SIZE(armv6_dcache_flush)
210
211 ENTRY(armv6_text_flush_range)
212 add r1, r1, r0
213 sub r1, r1, r0
214 mcrr p15, 0, r1, r0, c5 @ Invalidate i-cache range
215 mcrr p15, 0, r1, r0, c12 @ Flush d-cache range
216 ARM_DSB_INSTR(r2)
217 ARM_ISB_INSTR(r2)
218 bx lr
219 SET_SIZE(armv6_text_flush_range)
220
221 ENTRY(armv6_text_flush)
222 mov r0, #0
223 mcr p15, 0, r0, c7, c5, 0 @ Invalidate i-cache
224 mcr p15, 0, r0, c7, c10, 4 @ Flush d-cache
225 ARM_DSB_INSTR(r2)
226 ARM_ISB_INSTR(r2)
227 bx lr
228 SET_SIZE(armv6_text_flush)
229
230 #endif
231
232 #ifdef __lint
233
234 /*
235 * Perform all of the operations necessary for tlb maintenance after an update
236 * to the page tables.
237 */
238 void
239 armv6_tlb_sync(void)
240 {}
241
242 #else /* __lint */
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