81 
  82         ENTRY(membar_consumer)
  83         dmb
  84         bx lr
  85         SET_SIZE(membar_consumer)
  86 
  87         ENTRY(instr_sbarrier)
  88         isb
  89         bx lr
  90         SET_SIZE(membar_consumer)
  91 
  92         ENTRY(data_sbarrier)
  93         isb
  94         bx lr
  95         SET_SIZE(data_sbarrier)
  96 
  97 #endif  /* __lint */
  98 
  99 #if defined(lint) || defined(__lint)
 100 
 101 /* The ARM architecture uses a modified Harvard Architecture which means that we

 102  * get the joys of fixing up this mess. Primarily this means that when we update
 103  * data, it gets written to do the data cache. That needs to be flushed to main
 104  * memory and then the instruction cache needs to be invalidated. This is
 105  * particularly important for things like krtld and DTrace. While the data cache
 106  * does write itself out over time, we cannot rely on it having written itself
 107  * out to the state that we care about by the time that we'd like it to. As
 108  * such, we need to ensure that it's been flushed out ourselves. This also means
 109  * that we could accidentally flush a region of the icache that's already
 110  * updated itself, but that's just what we have to do to keep Von Neumann's
 111  * spirt and great gift alive.
 112  *
 113  * The controllers for the caches have a few different options for invalidation.
 114  * One may:
 115  *
 116  *   o Invalidate or flush the entire cache
 117  *   o Invalidate or flush a cache line
 118  *   o Invalidate or flush a cache range
 119  *
 120  * We opt to take the third option here for the general case of making sure that
 121  * text has been synchronized. While the data cache allows us to both invalidate

  81 
  82         ENTRY(membar_consumer)
  83         dmb
  84         bx lr
  85         SET_SIZE(membar_consumer)
  86 
  87         ENTRY(instr_sbarrier)
  88         isb
  89         bx lr
  90         SET_SIZE(membar_consumer)
  91 
  92         ENTRY(data_sbarrier)
  93         isb
  94         bx lr
  95         SET_SIZE(data_sbarrier)
  96 
  97 #endif  /* __lint */
  98 
  99 #if defined(lint) || defined(__lint)
 100 
 101 /*
 102  * The ARM architecture uses a modified Harvard Architecture which means that we
 103  * get the joys of fixing up this mess. Primarily this means that when we update
 104  * data, it gets written to do the data cache. That needs to be flushed to main
 105  * memory and then the instruction cache needs to be invalidated. This is
 106  * particularly important for things like krtld and DTrace. While the data cache
 107  * does write itself out over time, we cannot rely on it having written itself
 108  * out to the state that we care about by the time that we'd like it to. As
 109  * such, we need to ensure that it's been flushed out ourselves. This also means
 110  * that we could accidentally flush a region of the icache that's already
 111  * updated itself, but that's just what we have to do to keep Von Neumann's
 112  * spirt and great gift alive.
 113  *
 114  * The controllers for the caches have a few different options for invalidation.
 115  * One may:
 116  *
 117  *   o Invalidate or flush the entire cache
 118  *   o Invalidate or flush a cache line
 119  *   o Invalidate or flush a cache range
 120  *
 121  * We opt to take the third option here for the general case of making sure that
 122  * text has been synchronized. While the data cache allows us to both invalidate