1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2014 Joyent, Inc. All rights reserved.
14 */
15
16 .file "cpuid.s"
17
18 /*
19 * Read cpuid values from coprocessors
20 */
21
22 #include <sys/asm_linkage.h>
23
24 #if defined(lint) || defined(__lint)
25
26 uint32_t
27 arm_cpuid_midr()
28 {}
29
30 uint32_t
31 arm_cpuid_pfr0()
32 {}
33
34 uint32_t
35 arm_cpuid_pfr1()
36 {}
37
38 uint32_t
39 arm_cpuid_dfr0()
40 {}
41
42 uint32_t
43 arm_cpuid_mmfr0()
44 {}
45
46 uint32_t
47 arm_cpuid_mmfr1()
48 {}
49
50 uint32_t
51 arm_cpuid_mmfr2()
52 {}
53
54 uint32_t
55 arm_cpuid_mmfr3()
56 {}
57
58 uint32_t
59 arm_cpuid_isar0()
60 {}
61
62 uint32_t
63 arm_cpuid_isar1()
64 {}
65
66 uint32_t
67 arm_cpuid_isar2()
68 {}
69
70 uint32_t
71 arm_cpuid_isar3()
72 {}
73
74 uint32_t
75 arm_cpuid_isar4()
76 {}
77
78 uint32_t
79 arm_cpuid_isar5()
80 {}
81
82 uint32_t
83 arm_cpuid_vfpidreg()
84 {}
85
86 uint32_t
87 arm_cpuid_mvfr0()
88 {}
89
90 uint32_t
91 arm_cpuid_mvfr1()
92 {}
93
94 #else /* __lint */
95
96 ENTRY(arm_cpuid_midr)
97 mrc p15, 0, r0, c0, c0, 0
98 bx lr
99 SET_SIZE(arm_cpuid_midr)
100
101 ENTRY(arm_cpuid_pfr0)
102 mrc p15, 0, r0, c0, c1, 0
103 bx lr
104 SET_SIZE(arm_cpuid_pfr0)
105
106 ENTRY(arm_cpuid_pfr1)
107 mrc p15, 0, r0, c0, c1, 1
108 bx lr
109 SET_SIZE(arm_cpuid_pfr1)
110
111 ENTRY(arm_cpuid_dfr0)
112 mrc p15, 0, r0, c0, c1, 2
113 bx lr
114 SET_SIZE(arm_cpuid_dfr0)
115
116 ENTRY(arm_cpuid_mmfr0)
117 mrc p15, 0, r0, c0, c1, 4
118 bx lr
119 SET_SIZE(arm_cpuid_mmfr0)
120
121 ENTRY(arm_cpuid_mmfr1)
122 mrc p15, 0, r0, c0, c1, 5
123 bx lr
124 SET_SIZE(arm_cpuid_mmfr1)
125
126 ENTRY(arm_cpuid_mmfr2)
127 mrc p15, 0, r0, c0, c1, 6
128 bx lr
129 SET_SIZE(arm_cpuid_mmfr2)
130
131 ENTRY(arm_cpuid_mmfr3)
132 mrc p15, 0, r0, c0, c1, 7
133 bx lr
134 SET_SIZE(arm_cpuid_mmfr3)
135
136 ENTRY(arm_cpuid_isar0)
137 mrc p15, 0, r0, c0, c2, 0
138 bx lr
139 SET_SIZE(arm_cpuid_isar0)
140
141 ENTRY(arm_cpuid_isar1)
142 mrc p15, 0, r0, c0, c2, 1
143 bx lr
144 SET_SIZE(arm_cpuid_isar1)
145
146 ENTRY(arm_cpuid_isar2)
147 mrc p15, 0, r0, c0, c2, 2
148 bx lr
149 SET_SIZE(arm_cpuid_isar2)
150
151 ENTRY(arm_cpuid_isar3)
152 mrc p15, 0, r0, c0, c2, 3
153 bx lr
154 SET_SIZE(arm_cpuid_isar3)
155
156 ENTRY(arm_cpuid_isar4)
157 mrc p15, 0, r0, c0, c2, 4
158 bx lr
159 SET_SIZE(arm_cpuid_isar4)
160
161 ENTRY(arm_cpuid_isar5)
162 mrc p15, 0, r0, c0, c2, 5
163 bx lr
164 SET_SIZE(arm_cpuid_isar5)
165
166 ENTRY(arm_cpuid_vfpidreg)
167 vmrs r0, FPSID
168 bx lr
169 SET_SIZE(arm_cpuid_vfpidreg)
170
171 ENTRY(arm_cpuid_mvfr0)
172 vmrs r0, MVFR0
173 bx lr
174 SET_SIZE(arm_cpuid_mvfr0)
175
176 ENTRY(arm_cpuid_mvfr1)
177 vmrs r0, MVFR1
178 bx lr
179 SET_SIZE(arm_cpuid_mvfr1)
180 #endif /* __lint */
181
182 ENTRY(arm_cpuid_clidr)
183 mrc p15, 1, r0, c0, c0, 1
184 bx lr
185 SET_SIZE(arm_cpuid_clidr)
186
187 ENTRY(arm_cpuid_ccsidr)
188 lsl r0, r0, #1
189 cmp r1, #0 /* icache == B_FALSE */
190 orrne r0, r0, #1
191 mcr p15, 2, r0, c0, c0, 0 /* write CSSELR */
192 mrc p15, 1, r0, c0, c0, 0 /* read selected CCSIDR */
193 bx lr
194 SET_SIZE(arm_cpuid_ccsidr)