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cpuid for ARMv7


   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source.  A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11 
  12 /*
  13  * Copyright 2014 Joyent, Inc.  All rights reserved.
  14  */
  15 
  16         .file   "cpuid.s"
  17 
  18 /*
  19  * Read cpuid values from coprocessors
  20  */
  21 
  22 #include <sys/asm_linkage.h>
  23 
  24 #if defined(lint) || defined(__lint)
  25 
  26 uint32_t
  27 arm_cpuid_idreg()
  28 {}
  29 
  30 uint32_t
  31 arm_cpuid_pfr0()
  32 {}
  33 
  34 uint32_t
  35 arm_cpuid_pfr1()
  36 {}
  37 
  38 uint32_t
  39 arm_cpuid_dfr0()
  40 {}
  41 
  42 uint32_t
  43 arm_cpuid_mmfr0()
  44 {}
  45 
  46 uint32_t
  47 arm_cpuid_mmfr1()


  74 uint32_t
  75 arm_cpuid_isar4()
  76 {}
  77 
  78 uint32_t
  79 arm_cpuid_isar5()
  80 {}
  81 
  82 uint32_t
  83 arm_cpuid_vfpidreg()
  84 {}
  85 
  86 uint32_t
  87 arm_cpuid_mvfr0()
  88 {}
  89 
  90 uint32_t
  91 arm_cpuid_mvfr1()
  92 {}
  93 
  94 uint32_t
  95 arm_cpuid_ctr()
  96 {}
  97 
  98 #else   /* __lint */
  99 
 100         ENTRY(arm_cpuid_idreg)
 101         mrc     p15, 0, r0, c0, c0, 0
 102         bx      lr
 103         SET_SIZE(arm_cpuid_idreg)
 104 
 105         ENTRY(arm_cpuid_pfr0)
 106         mrc     p15, 0, r0, c0, c1, 0
 107         bx      lr
 108         SET_SIZE(arm_cpuid_pfr0)
 109 
 110         ENTRY(arm_cpuid_pfr1)
 111         mrc     p15, 0, r0, c0, c1, 1
 112         bx      lr
 113         SET_SIZE(arm_cpuid_pfr1)
 114 
 115         ENTRY(arm_cpuid_dfr0)
 116         mrc     p15, 0, r0, c0, c1, 2
 117         bx      lr
 118         SET_SIZE(arm_cpuid_dfr0)
 119 
 120         ENTRY(arm_cpuid_mmfr0)
 121         mrc     p15, 0, r0, c0, c1, 4
 122         bx      lr
 123         SET_SIZE(arm_cpuid_mmfr0)


 164 
 165         ENTRY(arm_cpuid_isar5)
 166         mrc     p15, 0, r0, c0, c2, 5
 167         bx      lr
 168         SET_SIZE(arm_cpuid_isar5)
 169 
 170         ENTRY(arm_cpuid_vfpidreg)
 171         vmrs    r0, FPSID
 172         bx      lr
 173         SET_SIZE(arm_cpuid_vfpidreg)
 174 
 175         ENTRY(arm_cpuid_mvfr0)
 176         vmrs    r0, MVFR0
 177         bx      lr
 178         SET_SIZE(arm_cpuid_mvfr0)
 179 
 180         ENTRY(arm_cpuid_mvfr1)
 181         vmrs    r0, MVFR1
 182         bx      lr
 183         SET_SIZE(arm_cpuid_mvfr1)

 184 
 185         ENTRY(arm_cpuid_ctr)
 186         mrc     p15, 0, r0, c0, c0, 1
 187         bx      lr
 188         SET_SIZE(arm_cpuid_ctr)
 189 #endif /* __lint */










   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source.  A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11 
  12 /*
  13  * Copyright 2014 Joyent, Inc.  All rights reserved.
  14  */
  15 
  16         .file   "cpuid.s"
  17 
  18 /*
  19  * Read cpuid values from coprocessors
  20  */
  21 
  22 #include <sys/asm_linkage.h>
  23 
  24 #if defined(lint) || defined(__lint)
  25 
  26 uint32_t
  27 arm_cpuid_midr()
  28 {}
  29 
  30 uint32_t
  31 arm_cpuid_pfr0()
  32 {}
  33 
  34 uint32_t
  35 arm_cpuid_pfr1()
  36 {}
  37 
  38 uint32_t
  39 arm_cpuid_dfr0()
  40 {}
  41 
  42 uint32_t
  43 arm_cpuid_mmfr0()
  44 {}
  45 
  46 uint32_t
  47 arm_cpuid_mmfr1()


  74 uint32_t
  75 arm_cpuid_isar4()
  76 {}
  77 
  78 uint32_t
  79 arm_cpuid_isar5()
  80 {}
  81 
  82 uint32_t
  83 arm_cpuid_vfpidreg()
  84 {}
  85 
  86 uint32_t
  87 arm_cpuid_mvfr0()
  88 {}
  89 
  90 uint32_t
  91 arm_cpuid_mvfr1()
  92 {}
  93 




  94 #else   /* __lint */
  95 
  96         ENTRY(arm_cpuid_midr)
  97         mrc     p15, 0, r0, c0, c0, 0
  98         bx      lr
  99         SET_SIZE(arm_cpuid_midr)
 100 
 101         ENTRY(arm_cpuid_pfr0)
 102         mrc     p15, 0, r0, c0, c1, 0
 103         bx      lr
 104         SET_SIZE(arm_cpuid_pfr0)
 105 
 106         ENTRY(arm_cpuid_pfr1)
 107         mrc     p15, 0, r0, c0, c1, 1
 108         bx      lr
 109         SET_SIZE(arm_cpuid_pfr1)
 110 
 111         ENTRY(arm_cpuid_dfr0)
 112         mrc     p15, 0, r0, c0, c1, 2
 113         bx      lr
 114         SET_SIZE(arm_cpuid_dfr0)
 115 
 116         ENTRY(arm_cpuid_mmfr0)
 117         mrc     p15, 0, r0, c0, c1, 4
 118         bx      lr
 119         SET_SIZE(arm_cpuid_mmfr0)


 160 
 161         ENTRY(arm_cpuid_isar5)
 162         mrc     p15, 0, r0, c0, c2, 5
 163         bx      lr
 164         SET_SIZE(arm_cpuid_isar5)
 165 
 166         ENTRY(arm_cpuid_vfpidreg)
 167         vmrs    r0, FPSID
 168         bx      lr
 169         SET_SIZE(arm_cpuid_vfpidreg)
 170 
 171         ENTRY(arm_cpuid_mvfr0)
 172         vmrs    r0, MVFR0
 173         bx      lr
 174         SET_SIZE(arm_cpuid_mvfr0)
 175 
 176         ENTRY(arm_cpuid_mvfr1)
 177         vmrs    r0, MVFR1
 178         bx      lr
 179         SET_SIZE(arm_cpuid_mvfr1)
 180 #endif /* __lint */
 181 
 182         ENTRY(arm_cpuid_clidr)
 183         mrc     p15, 1, r0, c0, c0, 1
 184         bx      lr
 185         SET_SIZE(arm_cpuid_clidr)
 186 
 187         ENTRY(arm_cpuid_ccsidr)
 188         lsl     r0, r0, #1
 189         cmp     r1, #0                          /* icache == B_FALSE */
 190         orrne   r0, r0, #1
 191         mcr     p15, 2, r0, c0, c0, 0           /* write CSSELR */
 192         mrc     p15, 1, r0, c0, c0, 0           /* read selected CCSIDR */
 193         bx      lr
 194         SET_SIZE(arm_cpuid_ccsidr)