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cpuid for ARMv7
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--- old/usr/src/uts/armv7/ml/cpuid_ml.s
+++ new/usr/src/uts/armv7/ml/cpuid_ml.s
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2014 Joyent, Inc. All rights reserved.
14 14 */
15 15
16 16 .file "cpuid.s"
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17 17
18 18 /*
19 19 * Read cpuid values from coprocessors
20 20 */
21 21
22 22 #include <sys/asm_linkage.h>
23 23
24 24 #if defined(lint) || defined(__lint)
25 25
26 26 uint32_t
27 -arm_cpuid_idreg()
27 +arm_cpuid_midr()
28 28 {}
29 29
30 30 uint32_t
31 31 arm_cpuid_pfr0()
32 32 {}
33 33
34 34 uint32_t
35 35 arm_cpuid_pfr1()
36 36 {}
37 37
38 38 uint32_t
39 39 arm_cpuid_dfr0()
40 40 {}
41 41
42 42 uint32_t
43 43 arm_cpuid_mmfr0()
44 44 {}
45 45
46 46 uint32_t
47 47 arm_cpuid_mmfr1()
48 48 {}
49 49
50 50 uint32_t
51 51 arm_cpuid_mmfr2()
52 52 {}
53 53
54 54 uint32_t
55 55 arm_cpuid_mmfr3()
56 56 {}
57 57
58 58 uint32_t
59 59 arm_cpuid_isar0()
60 60 {}
61 61
62 62 uint32_t
63 63 arm_cpuid_isar1()
64 64 {}
65 65
66 66 uint32_t
67 67 arm_cpuid_isar2()
68 68 {}
69 69
70 70 uint32_t
71 71 arm_cpuid_isar3()
72 72 {}
73 73
74 74 uint32_t
75 75 arm_cpuid_isar4()
76 76 {}
77 77
78 78 uint32_t
79 79 arm_cpuid_isar5()
80 80 {}
81 81
82 82 uint32_t
83 83 arm_cpuid_vfpidreg()
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84 84 {}
85 85
86 86 uint32_t
87 87 arm_cpuid_mvfr0()
88 88 {}
89 89
90 90 uint32_t
91 91 arm_cpuid_mvfr1()
92 92 {}
93 93
94 -uint32_t
95 -arm_cpuid_ctr()
96 -{}
97 -
98 94 #else /* __lint */
99 95
100 - ENTRY(arm_cpuid_idreg)
96 + ENTRY(arm_cpuid_midr)
101 97 mrc p15, 0, r0, c0, c0, 0
102 98 bx lr
103 - SET_SIZE(arm_cpuid_idreg)
99 + SET_SIZE(arm_cpuid_midr)
104 100
105 101 ENTRY(arm_cpuid_pfr0)
106 102 mrc p15, 0, r0, c0, c1, 0
107 103 bx lr
108 104 SET_SIZE(arm_cpuid_pfr0)
109 105
110 106 ENTRY(arm_cpuid_pfr1)
111 107 mrc p15, 0, r0, c0, c1, 1
112 108 bx lr
113 109 SET_SIZE(arm_cpuid_pfr1)
114 110
115 111 ENTRY(arm_cpuid_dfr0)
116 112 mrc p15, 0, r0, c0, c1, 2
117 113 bx lr
118 114 SET_SIZE(arm_cpuid_dfr0)
119 115
120 116 ENTRY(arm_cpuid_mmfr0)
121 117 mrc p15, 0, r0, c0, c1, 4
122 118 bx lr
123 119 SET_SIZE(arm_cpuid_mmfr0)
124 120
125 121 ENTRY(arm_cpuid_mmfr1)
126 122 mrc p15, 0, r0, c0, c1, 5
127 123 bx lr
128 124 SET_SIZE(arm_cpuid_mmfr1)
129 125
130 126 ENTRY(arm_cpuid_mmfr2)
131 127 mrc p15, 0, r0, c0, c1, 6
132 128 bx lr
133 129 SET_SIZE(arm_cpuid_mmfr2)
134 130
135 131 ENTRY(arm_cpuid_mmfr3)
136 132 mrc p15, 0, r0, c0, c1, 7
137 133 bx lr
138 134 SET_SIZE(arm_cpuid_mmfr3)
139 135
140 136 ENTRY(arm_cpuid_isar0)
141 137 mrc p15, 0, r0, c0, c2, 0
142 138 bx lr
143 139 SET_SIZE(arm_cpuid_isar0)
144 140
145 141 ENTRY(arm_cpuid_isar1)
146 142 mrc p15, 0, r0, c0, c2, 1
147 143 bx lr
148 144 SET_SIZE(arm_cpuid_isar1)
149 145
150 146 ENTRY(arm_cpuid_isar2)
151 147 mrc p15, 0, r0, c0, c2, 2
152 148 bx lr
153 149 SET_SIZE(arm_cpuid_isar2)
154 150
155 151 ENTRY(arm_cpuid_isar3)
156 152 mrc p15, 0, r0, c0, c2, 3
157 153 bx lr
158 154 SET_SIZE(arm_cpuid_isar3)
159 155
160 156 ENTRY(arm_cpuid_isar4)
161 157 mrc p15, 0, r0, c0, c2, 4
162 158 bx lr
163 159 SET_SIZE(arm_cpuid_isar4)
164 160
165 161 ENTRY(arm_cpuid_isar5)
166 162 mrc p15, 0, r0, c0, c2, 5
167 163 bx lr
168 164 SET_SIZE(arm_cpuid_isar5)
169 165
170 166 ENTRY(arm_cpuid_vfpidreg)
171 167 vmrs r0, FPSID
172 168 bx lr
173 169 SET_SIZE(arm_cpuid_vfpidreg)
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174 170
175 171 ENTRY(arm_cpuid_mvfr0)
176 172 vmrs r0, MVFR0
177 173 bx lr
178 174 SET_SIZE(arm_cpuid_mvfr0)
179 175
180 176 ENTRY(arm_cpuid_mvfr1)
181 177 vmrs r0, MVFR1
182 178 bx lr
183 179 SET_SIZE(arm_cpuid_mvfr1)
180 +#endif /* __lint */
184 181
185 - ENTRY(arm_cpuid_ctr)
186 - mrc p15, 0, r0, c0, c0, 1
182 + ENTRY(arm_cpuid_clidr)
183 + mrc p15, 1, r0, c0, c0, 1
187 184 bx lr
188 - SET_SIZE(arm_cpuid_ctr)
189 -#endif /* __lint */
185 + SET_SIZE(arm_cpuid_clidr)
186 +
187 + ENTRY(arm_cpuid_ccsidr)
188 + lsl r0, r0, #1
189 + cmp r1, #0 /* icache == B_FALSE */
190 + orrne r0, r0, #1
191 + mcr p15, 2, r0, c0, c0, 0 /* write CSSELR */
192 + mrc p15, 1, r0, c0, c0, 0 /* read selected CCSIDR */
193 + bx lr
194 + SET_SIZE(arm_cpuid_ccsidr)
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