cpuid for ARMv7

          --- old/usr/src/uts/armv7/sys/cpuid_impl.h
          +++ new/usr/src/uts/armv7/sys/cpuid_impl.h

   1    1  /*
   2    2   * This file and its contents are supplied under the terms of the
   3    3   * Common Development and Distribution License ("CDDL"), version 1.0.
   4    4   * You may only use this file in accordance with the terms of version
   5    5   * 1.0 of the CDDL.
   6    6   *
   7    7   * A full copy of the text of the CDDL should have accompanied this
   8    8   * source.  A copy of the CDDL is also available via the Internet at
   9    9   * http://www.illumos.org/license/CDDL.
  10   10   */
  11   11  
  12   12  /*
  13   13   * Copyright (c) 2014 Joyent, Inc.  All rights reserved.
  14   14   */
  15   15  
  16   16  #ifndef _SYS_CPUID_IMPL_H
  17   17  #define _SYS_CPUID_IMPL_H
  18   18  
  19   19  #include <sys/stdint.h>
  20   20  #include <sys/arm_archext.h>
  21   21  #include <sys/types.h>
  22   22  

  23   23  /*
  24   24   * Routines to read ARM cpuid co-processors
  25   25   */
  26   26  
  27   27  #ifdef __cplusplus
  28   28  extern "C" {
  29   29  #endif
  30   30  
  31   31  typedef struct arm_cpuid_cache {
  32   32          boolean_t acc_exists;
  33      -        boolean_t acc_rcolor;
  34      -        uint8_t acc_assoc;
       33 +        boolean_t acc_unified;
       34 +        boolean_t acc_wt;
       35 +        boolean_t acc_wb;
       36 +        boolean_t acc_ra;
       37 +        boolean_t acc_wa;
       38 +        uint16_t acc_sets;
  35   39          uint8_t acc_linesz;
       40 +        uint16_t acc_assoc;
       41 +
       42 +        boolean_t acc_rcolor;
  36   43          uint32_t acc_size;
  37   44  } arm_cpuid_cache_t;
  38   45  
  39   46  typedef struct arm_cpuid {
  40   47          uint32_t ac_ident;
  41   48          uint32_t ac_pfr[2];
  42   49          uint32_t ac_dfr;
  43   50          uint32_t ac_mmfr[4];
  44   51          uint32_t ac_isar[6];
  45   52          uint32_t ac_fpident;
  46   53          uint32_t ac_mvfr[2];
  47      -        boolean_t ac_unifiedl1;
  48      -        arm_cpuid_cache_t ac_icache;
  49      -        arm_cpuid_cache_t ac_dcache;
       54 +        uint32_t ac_clidr;
       55 +
       56 +        /*
       57 +         * ARM supports 7 levels of caches.  Each level can have separate
       58 +         * I/D caches or a unified cache.  We keep track of all these as a
       59 +         * two dimensional array.  First, we select if we're dealing with a
       60 +         * I cache (B_TRUE) or a D/unified cache (B_FALSE), and then we
       61 +         * index on the level.  Note that L1 caches are at index 0.
       62 +         */
       63 +        uint32_t ac_ccsidr[2][7];
       64 +        arm_cpuid_cache_t ac_caches[2][7];
  50   65  } arm_cpuid_t;
  51   66  
  52      -extern uint32_t arm_cpuid_idreg();
       67 +extern uint32_t arm_cpuid_midr();
  53   68  extern uint32_t arm_cpuid_pfr0();
  54   69  extern uint32_t arm_cpuid_pfr1();
  55   70  extern uint32_t arm_cpuid_dfr0();
  56   71  extern uint32_t arm_cpuid_mmfr0();
  57   72  extern uint32_t arm_cpuid_mmfr1();
  58   73  extern uint32_t arm_cpuid_mmfr2();
  59   74  extern uint32_t arm_cpuid_mmfr3();
  60   75  extern uint32_t arm_cpuid_isar0();
  61   76  extern uint32_t arm_cpuid_isar1();
  62   77  extern uint32_t arm_cpuid_isar2();
  63   78  extern uint32_t arm_cpuid_isar3();
  64   79  extern uint32_t arm_cpuid_isar4();
  65   80  extern uint32_t arm_cpuid_isar5();
  66   81  
  67   82  extern uint32_t arm_cpuid_vfpidreg();
  68   83  extern uint32_t arm_cpuid_mvfr0();
  69   84  extern uint32_t arm_cpuid_mvfr1();
  70   85  
  71      -extern uint32_t arm_cpuid_ctr();
       86 +extern uint32_t arm_cpuid_clidr();
       87 +extern uint32_t arm_cpuid_ccsidr(uint32_t level, boolean_t icache);
  72   88  
  73   89  #ifdef __cplusplus
  74   90  }
  75   91  #endif
  76   92  
  77   93  #endif /* _SYS_CPUID_IMPL_H */
    

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