251 * they'll always get the same data.
252 */
253 extern uint_t mmu_page_sizes;
254 extern uint_t mmu_exported_page_sizes;
255 extern uint_t mmu_legacy_page_sizes;
256
257 /*
258 * These macros are used for converting between userland page sizes and kernel
259 * page sizes. However, these are the same on ARMv7 (just like i86pc).
260 */
261 #define USERSZC_2_SZC(userszc) userszc
262 #define SZC_2_USERSZC(szc) szc
263
264 /*
265 * for hw_page_map_t, sized to hold the ratio of large page to base
266 * pagesize
267 */
268 typedef short hpmctr_t;
269
270 /*
271 * On ARMv6 the layer two cache isn't architecturally defined. A given
272 * implementation may or may not support it. The maximum size appears to be
273 * 64-bytes; however, we end up having to defer to the individual platforms for
274 * more information. Because of this, we also get and use the l1 cache
275 * information. This is further complicated by the fact that the I-cache and
276 * D-cache are separate usually; therefore we us the the l1 d-cache for
277 * CPUSETSIZE().
278 */
279 extern int armv6_cachesz, armv6_cache_assoc;
280 extern int armv6_l2cache_size, armv6_l2cache_linesz;
281 #define L2CACHE_ALIGN armv6_l2cache_linesz
282 #define L2CACHE_ALIGN_MAX 64
283 #define CPUSETSIZE() (armv6_cachesz / armv6_cache_assoc)
284
285 /*
286 * Return the log2(pagesize(szc) / MMU_PAGESIZE) --- or the shift count
287 * for the number of base pages in this pagesize
288 */
289 #define PAGE_BSZS_SHIFT(szc) (PNUM_SHIFT(szc) - MMU_PAGESHIFT)
290
291 /*
292 * Internal PG_ flags.
293 */
294 #define PGI_RELOCONLY 0x010000 /* opposite of PG_NORELOC */
295 #define PGI_NOCAGE 0x020000 /* cage is disabled */
296 #define PGI_PGCPHIPRI 0x040000 /* page_get_contig_page pri alloc */
297 #define PGI_PGCPSZC0 0x080000 /* relocate base pagesize page */
298
299 /*
300 * XXX Consider PGI flags for ourselves
301 */
302
303 #define AS_2_BIN(as, seg, vp, addr, bin, szc) panic("as_2_bin")
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251 * they'll always get the same data.
252 */
253 extern uint_t mmu_page_sizes;
254 extern uint_t mmu_exported_page_sizes;
255 extern uint_t mmu_legacy_page_sizes;
256
257 /*
258 * These macros are used for converting between userland page sizes and kernel
259 * page sizes. However, these are the same on ARMv7 (just like i86pc).
260 */
261 #define USERSZC_2_SZC(userszc) userszc
262 #define SZC_2_USERSZC(szc) szc
263
264 /*
265 * for hw_page_map_t, sized to hold the ratio of large page to base
266 * pagesize
267 */
268 typedef short hpmctr_t;
269
270 /*
271 * get the setsize of the current cpu
272 *
273 * This is complicated by the fact that the I-cache and D-cache may be
274 * separate.
275 */
276 extern int l2cache_sz, l2cache_linesz, l2cache_assoc;
277 #define L2CACHE_ALIGN l2cache_linesz
278 #define L2CACHE_ALIGN_MAX 64
279 #define CPUSETSIZE() (l2cache_sz / l2cache_assoc)
280
281 /*
282 * Return the log2(pagesize(szc) / MMU_PAGESIZE) --- or the shift count
283 * for the number of base pages in this pagesize
284 */
285 #define PAGE_BSZS_SHIFT(szc) (PNUM_SHIFT(szc) - MMU_PAGESHIFT)
286
287 /*
288 * Internal PG_ flags.
289 */
290 #define PGI_RELOCONLY 0x010000 /* opposite of PG_NORELOC */
291 #define PGI_NOCAGE 0x020000 /* cage is disabled */
292 #define PGI_PGCPHIPRI 0x040000 /* page_get_contig_page pri alloc */
293 #define PGI_PGCPSZC0 0x080000 /* relocate base pagesize page */
294
295 /*
296 * XXX Consider PGI flags for ourselves
297 */
298
299 #define AS_2_BIN(as, seg, vp, addr, bin, szc) panic("as_2_bin")
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