84         bx      lr
  85         SET_SIZE(fakeload_pt_setup)
  86 
  87 #endif /* __lint */
  88 
  89 #if defined(__lint)
  90 
  91 /* ARGSUSED */
  92 void
  93 fakeload_mmu_enable(void)
  94 {}
  95 
  96 #else   /* __lint */
  97 
  98         /*
  99          * We first make sure that the ARMv6 pages are enabled (bit 23) and then
 100          * enable the MMU (bit 0).
 101          */
 102         ENTRY(fakeload_mmu_enable)
 103         mrc     p15, 0, r0, c1, c0, 0
 104         orr     r0, #0x800000
 105         mcr     p15, 0, r0, c1, c0, 0
 106         mrc     p15, 0, r0, c1, c0, 0
 107         orr     r0, #0x1
 108         mcr     p15, 0, r0, c1, c0, 0
 109         bx      lr
 110         SET_SIZE(fakeload_mmu_enable)
 111 #endif  /* __lint */
 112 
 113 
 114         ENTRY(fakeload_exec)
 115         blx     r3
 116         /* We should never execute this. If we do we'll go back to a panic */
 117         bx      lr
 118         SET_SIZE(fakeload_exec)

  84         bx      lr
  85         SET_SIZE(fakeload_pt_setup)
  86 
  87 #endif /* __lint */
  88 
  89 #if defined(__lint)
  90 
  91 /* ARGSUSED */
  92 void
  93 fakeload_mmu_enable(void)
  94 {}
  95 
  96 #else   /* __lint */
  97 
  98         /*
  99          * We first make sure that the ARMv6 pages are enabled (bit 23) and then
 100          * enable the MMU (bit 0).
 101          */
 102         ENTRY(fakeload_mmu_enable)
 103         mrc     p15, 0, r0, c1, c0, 0
 104         orr     r0, #0x800000           /* enable ARMv6 pages */
 105         orr     r0, #0x1                /* enable MMU */


 106         mcr     p15, 0, r0, c1, c0, 0
 107         bx      lr
 108         SET_SIZE(fakeload_mmu_enable)
 109 #endif  /* __lint */
 110 
 111 
 112         ENTRY(fakeload_exec)
 113         blx     r3
 114         /* We should never execute this. If we do we'll go back to a panic */
 115         bx      lr
 116         SET_SIZE(fakeload_exec)