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4665 pcplusmp open-codes register operations

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          --- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
          +++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
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 564  564                          apic_nsec_since_boot += apic_nsec_per_intr;
 565  565                          apic_hrtime_stamp++;
 566  566                          last_count_read = apic_hertz_count;
 567  567                          apic_redistribute_compute();
 568  568                  }
 569  569  
 570  570                  /* We will avoid all the book keeping overhead for clock */
 571  571                  nipl = apic_ipls[vector];
 572  572  
 573  573                  *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
 574      -                if (apic_mode == LOCAL_APIC) {
 575      -#if defined(__amd64)
 576      -                        setcr8((ulong_t)(apic_ipltopri[nipl] >>
 577      -                            APIC_IPL_SHIFT));
 578      -#else
 579      -                        if (apic_have_32bit_cr8)
 580      -                                setcr8((ulong_t)(apic_ipltopri[nipl] >>
 581      -                                    APIC_IPL_SHIFT));
 582      -                        else
 583      -                                LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
 584      -                                    (uint32_t)apic_ipltopri[nipl]);
 585      -#endif
 586      -                        LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
 587      -                } else {
 588      -                        X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
 589      -                        X2APIC_WRITE(APIC_EOI_REG, 0);
 590      -                }
      574 +
      575 +                apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
      576 +                apic_reg_ops->apic_send_eoi(0);
 591  577  
 592  578                  return (nipl);
 593  579          }
 594  580  
 595  581          cpu_infop = &apic_cpus[psm_get_cpu_id()];
 596  582  
 597  583          if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
 598  584                  cpu_infop->aci_spur_cnt++;
 599  585                  return (APIC_INT_SPURIOUS);
 600  586          }
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 611  597                   */
 612  598                  iflag = intr_clear();
 613  599                  vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
 614  600                      APIC_BASE_VECT;
 615  601                  intr_restore(iflag);
 616  602          }
 617  603  
 618  604          nipl = apic_ipls[vector];
 619  605          *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
 620  606  
 621      -        if (apic_mode == LOCAL_APIC) {
 622      -#if defined(__amd64)
 623      -                setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
 624      -#else
 625      -                if (apic_have_32bit_cr8)
 626      -                        setcr8((ulong_t)(apic_ipltopri[nipl] >>
 627      -                            APIC_IPL_SHIFT));
 628      -                else
 629      -                        LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
 630      -                            (uint32_t)apic_ipltopri[nipl]);
 631      -#endif
 632      -        } else {
 633      -                X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
 634      -        }
      607 +        apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
 635  608  
 636  609          cpu_infop->aci_current[nipl] = (uchar_t)irq;
 637  610          cpu_infop->aci_curipl = (uchar_t)nipl;
 638  611          cpu_infop->aci_ISR_in_progress |= 1 << nipl;
 639  612  
 640  613          /*
 641  614           * apic_level_intr could have been assimilated into the irq struct.
 642  615           * but, having it as a character array is more efficient in terms of
 643  616           * cache usage. So, we leave it as is.
 644  617           */
 645  618          if (!apic_level_intr[irq]) {
 646      -                if (apic_mode == LOCAL_APIC) {
 647      -                        LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
 648      -                } else {
 649      -                        X2APIC_WRITE(APIC_EOI_REG, 0);
 650      -                }
      619 +                apic_reg_ops->apic_send_eoi(0);
 651  620          }
 652  621  
 653  622  #ifdef  DEBUG
 654  623          APIC_DEBUG_BUF_PUT(vector);
 655  624          APIC_DEBUG_BUF_PUT(irq);
 656  625          APIC_DEBUG_BUF_PUT(nipl);
 657  626          APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
 658  627          if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
 659  628                  drv_usecwait(apic_stretch_interrupts);
 660  629  
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 680  649  
 681  650  /*
 682  651   * Any changes made to this function must also change X2APIC
 683  652   * version of intr_exit.
 684  653   */
 685  654  void
 686  655  apic_intr_exit(int prev_ipl, int irq)
 687  656  {
 688  657          apic_cpus_info_t *cpu_infop;
 689  658  
 690      -#if defined(__amd64)
 691      -        setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
 692      -#else
 693      -        if (apic_have_32bit_cr8)
 694      -                setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
 695      -        else
 696      -                apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
 697      -#endif
      659 +        apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
 698  660  
 699  661          APIC_INTR_EXIT();
 700  662  }
 701  663  
 702  664  /*
 703  665   * Same as apic_intr_exit() except it uses MSR rather than MMIO
 704  666   * to access local apic registers.
 705  667   */
 706  668  void
 707  669  x2apic_intr_exit(int prev_ipl, int irq)
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 722  684  }
 723  685  
 724  686  /*
 725  687   * Mask all interrupts below or equal to the given IPL.
 726  688   * Any changes made to this function must also change X2APIC
 727  689   * version of setspl.
 728  690   */
 729  691  static void
 730  692  apic_setspl(int ipl)
 731  693  {
 732      -#if defined(__amd64)
 733      -        setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
 734      -#else
 735      -        if (apic_have_32bit_cr8)
 736      -                setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
 737      -        else
 738      -                apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
 739      -#endif
      694 +        apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
 740  695  
 741  696          /* interrupts at ipl above this cannot be in progress */
 742  697          apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
 743  698          /*
 744  699           * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
 745  700           * have enough time to come in before the priority is raised again
 746  701           * during the idle() loop.
 747  702           */
 748  703          if (apic_setspl_delay)
 749  704                  (void) apic_reg_ops->apic_get_pri();
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