1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2010 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26 /*
27 * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
28 */
29
30 #ifndef _EMLXS_FC_H
31 #define _EMLXS_FC_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 typedef struct emlxs_buf
38 {
39 fc_packet_t *pkt; /* scsi_pkt reference */
40 struct emlxs_port *port; /* pointer to port */
41 void *bmp; /* Save the buffer pointer */
42 /* list for later use. */
43 struct emlxs_buf *fc_fwd; /* Use it by chip_Q */
44 struct emlxs_buf *fc_bkwd; /* Use it by chip_Q */
45 struct emlxs_buf *next; /* Use it when the iodone */
46 struct emlxs_node *node;
47 void *channel; /* Save channel and used by */
48 /* abort */
49 struct emlxs_buf *fpkt; /* Flush pkt pointer */
50 struct XRIobj *xrip; /* Exchange resource */
51 IOCBQ iocbq;
52 kmutex_t mtx;
53 uint32_t pkt_flags;
54 uint32_t iotag; /* iotag for this cmd */
55 uint32_t ticks; /* save the timeout ticks */
56 /* for the fc_packet_t */
57 uint32_t abort_attempts;
58 uint32_t lun;
59 #define EMLXS_LUN_NONE 0xFFFFFFFF
60
61 uint32_t class; /* Save class and used by */
62 /* abort */
63 uint32_t ucmd; /* Unsolicted command that */
64 /* this packet is responding */
65 /* to, if any */
66 int32_t flush_count; /* Valid only in flush pkts */
67 uint32_t did;
68
69 #ifdef SFCT_SUPPORT
70 kmutex_t fct_mtx;
71 fc_packet_t *fct_pkt;
72 fct_cmd_t *fct_cmd;
73
74 uint8_t fct_type;
75
76 #define EMLXS_FCT_ELS_CMD 0x01 /* Unsolicted */
77 #define EMLXS_FCT_ELS_REQ 0x02 /* Solicited */
78 #define EMLXS_FCT_ELS_RSP 0x04
79 #define EMLXS_FCT_CT_REQ 0x08 /* Solicited */
80 #define EMLXS_FCT_FCP_CMD 0x10 /* Unsolicted */
81 #define EMLXS_FCT_FCP_DATA 0x20
82 #define EMLXS_FCT_FCP_STATUS 0x40
83
84
85 uint8_t fct_flags;
86
87 #define EMLXS_FCT_SEND_STATUS 0x01
88 #define EMLXS_FCT_ABORT_INP 0x02
89 #define EMLXS_FCT_IO_INP 0x04
90 #define EMLXS_FCT_PLOGI_RECEIVED 0x10
91 #define EMLXS_FCT_REGISTERED 0x20
92
93 uint16_t fct_state;
94
95 #define EMLXS_FCT_FCP_CMD_RECEIVED 1
96 #define EMLXS_FCT_ELS_CMD_RECEIVED 2
97 #define EMLXS_FCT_CMD_POSTED 3
98 #define EMLXS_FCT_CMD_WAITQ 4
99 #define EMLXS_FCT_SEND_CMD_RSP 5
100 #define EMLXS_FCT_SEND_ELS_RSP 6
101 #define EMLXS_FCT_SEND_ELS_REQ 7
102 #define EMLXS_FCT_SEND_CT_REQ 8
103 #define EMLXS_FCT_RSP_PENDING 9
104 #define EMLXS_FCT_REQ_PENDING 10
105 #define EMLXS_FCT_REG_PENDING 11
106 #define EMLXS_FCT_REG_COMPLETE 12
107 #define EMLXS_FCT_OWNED 13
108 #define EMLXS_FCT_SEND_FCP_DATA 14
109 #define EMLXS_FCT_SEND_FCP_STATUS 15
110 #define EMLXS_FCT_DATA_PENDING 16
111 #define EMLXS_FCT_STATUS_PENDING 17
112 #define EMLXS_FCT_PKT_COMPLETE 18
113 #define EMLXS_FCT_PKT_FCPRSP_COMPLETE 19
114 #define EMLXS_FCT_PKT_ELSRSP_COMPLETE 20
115 #define EMLXS_FCT_PKT_ELSCMD_COMPLETE 21
116 #define EMLXS_FCT_PKT_CTCMD_COMPLETE 22
117 #define EMLXS_FCT_REQ_COMPLETE 23
118 #define EMLXS_FCT_CLOSE_PENDING 24
119 #define EMLXS_FCT_ABORT_PENDING 25
120 #define EMLXS_FCT_ABORT_DONE 26
121 #define EMLXS_FCT_IO_DONE 27
122
123 #define EMLXS_FCT_IOCB_ISSUED 256 /* For tracing only */
124 #define EMLXS_FCT_IOCB_COMPLETE 257 /* For tracing only */
125
126 stmf_data_buf_t *fct_buf;
127
128 #endif /* SFCT_SUPPORT */
129
130 #ifdef SAN_DIAG_SUPPORT
131 hrtime_t sd_start_time;
132 #endif
133 } emlxs_buf_t;
134
135
136
137 #ifdef FCT_IO_TRACE
138 #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \
139 (_cmd_sbp)->fct_state = _state; \
140 emlxs_fct_io_trace((_cmd_sbp)->port, _fct_cmd, _state)
141 #else
142 /* define to set fct_state */
143 #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \
144 (_cmd_sbp)->fct_state = _state
145 #endif /* FCT_IO_TRACE */
146
147
148 /* pkt_flags */
149 #define PACKET_IN_COMPLETION 0x00000001
150 #define PACKET_IN_TXQ 0x00000002
151 #define PACKET_IN_CHIPQ 0x00000004
152 #define PACKET_IN_DONEQ 0x00000008
153
154 #define PACKET_FCP_RESET 0x00000030
155 #define PACKET_FCP_TGT_RESET 0x00000010
156 #define PACKET_FCP_LUN_RESET 0x00000020
157 #define PACKET_POLLED 0x00000040
158
159 #ifdef EMLXS_I386
160 #define PACKET_FCP_SWAPPED 0x00000100
161 #define PACKET_ELS_SWAPPED 0x00000200
162 #define PACKET_CT_SWAPPED 0x00000400
163 #define PACKET_CSP_SWAPPED 0x00000800
164 #endif /* EMLXS_I386 */
165
166 #define PACKET_STALE 0x00001000
167
168 #define PACKET_IN_TIMEOUT 0x00010000
169 #define PACKET_IN_FLUSH 0x00020000
170 #define PACKET_IN_ABORT 0x00040000
171 #define PACKET_XRI_CLOSED 0x00080000 /* An XRI abort/close was issued */
172
173 #define PACKET_CHIP_COMP 0x00100000
174 #define PACKET_COMPLETED 0x00200000
175 #define PACKET_ULP_OWNED 0x00400000
176
177 #define PACKET_STATE_VALID 0x01000000
178 #define PACKET_FCP_RSP_VALID 0x02000000
179 #define PACKET_ELS_RSP_VALID 0x04000000
180 #define PACKET_CT_RSP_VALID 0x08000000
181
182 #define PACKET_DELAY_REQUIRED 0x10000000
183 #define PACKET_ALLOCATED 0x40000000
184 #define PACKET_VALID 0x80000000
185
186
187 #define STALE_PACKET ((emlxs_buf_t *)0xFFFFFFFF)
188
189
190 /*
191 * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
192 * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
193 *
194 * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
195 * Each FCA defines its own set with values greater >= 0x7F
196 */
197 #define FC_REASON_FCA_DEFINED 0x100
198
199
200 /*
201 * Device VPD save area
202 */
203
204 typedef struct emlxs_vpd
205 {
206 uint32_t biuRev;
207 uint32_t smRev;
208 uint32_t smFwRev;
209 uint32_t endecRev;
210 uint16_t rBit;
211 uint8_t fcphHigh;
212 uint8_t fcphLow;
213 uint8_t feaLevelHigh;
214 uint8_t feaLevelLow;
215
216 uint32_t postKernRev;
217 char postKernName[32];
218
219 uint32_t opFwRev;
220 char opFwName[32];
221 char opFwLabel[32];
222
223 uint32_t sli1FwRev;
224 char sli1FwName[32];
225 char sli1FwLabel[32];
226
227 uint32_t sli2FwRev;
228 char sli2FwName[32];
229 char sli2FwLabel[32];
230
231 uint32_t sli3FwRev;
232 char sli3FwName[32];
233 char sli3FwLabel[32];
234
235 uint32_t sli4FwRev;
236 char sli4FwName[32];
237 char sli4FwLabel[32];
238
239 char fw_version[32];
240 char fw_label[32];
241
242 char fcode_version[32];
243 char boot_version[32];
244
245 char serial_num[32];
246 char part_num[32];
247 char port_num[20];
248 char eng_change[32];
249 char manufacturer[80];
250 char model[80];
251 char model_desc[256];
252 char prog_types[256];
253 char id[80];
254
255 uint32_t port_index;
256 uint16_t link_speed;
257 } emlxs_vpd_t;
258
259
260 typedef struct emlxs_queue
261 {
262 void *q_first; /* queue first element */
263 void *q_last; /* queue last element */
264 uint16_t q_cnt; /* current length of queue */
265 uint16_t q_max; /* max length queue can get */
266 } emlxs_queue_t;
267 typedef emlxs_queue_t Q;
268
269
270
271 /*
272 * This structure is used when allocating a buffer pool.
273 * Note: this should be identical to gasket buf_info (fldl.h).
274 */
275 typedef struct emlxs_buf_info
276 {
277 int32_t size; /* Specifies the number of bytes to allocate. */
278 int32_t align; /* The desired address boundary. */
279
280 int32_t flags;
281
282 #define FC_MBUF_DMA 0x01 /* blocks are for DMA */
283 #define FC_MBUF_PHYSONLY 0x02 /* For malloc - map a given virtual */
284 /* address to physical address (skip */
285 /* the malloc). */
286 /* For free - just unmap the given */
287 /* physical address (skip the free). */
288 #define FC_MBUF_IOCTL 0x04 /* called from dfc_ioctl */
289 #define FC_MBUF_UNLOCK 0x08 /* called with driver unlocked */
290 #define FC_MBUF_SNGLSG 0x10 /* allocate a single contiguous */
291 /* physical memory */
292 #define FC_MBUF_DMA32 0x20
293
294 uint64_t phys; /* specifies physical buffer pointer */
295 void *virt; /* specifies virtual buffer pointer */
296 void *data_handle;
297 void *dma_handle;
298 } emlxs_buf_info_t;
299 typedef emlxs_buf_info_t MBUF_INFO;
300
301
302 #define EMLXS_MAX_HBQ 16 /* Max HBQs handled by firmware */
303 #define EMLXS_ELS_HBQ_ID 0
304 #define EMLXS_IP_HBQ_ID 1
305 #define EMLXS_CT_HBQ_ID 2
306 #define EMLXS_FCT_HBQ_ID 3
307
308 #ifdef SFCT_SUPPORT
309 #define EMLXS_NUM_HBQ 4 /* Number of HBQs supported by driver */
310 #else
311 #define EMLXS_NUM_HBQ 3 /* Number of HBQs supported by driver */
312 #endif /* SFCT_SUPPORT */
313
314
315 /*
316 * An IO Channel is a object that comprises a xmit/cmpl
317 * path for IOs.
318 * For SLI3, an IO path maps to a ring (cmd/rsp)
319 * For SLI4, an IO path map to a queue pair (WQ/CQ)
320 */
321 typedef struct emlxs_channel
322 {
323 struct emlxs_hba *hba; /* ptr to hba for channel */
324 void *iopath; /* ptr to SLI3/4 io path */
325
326 kmutex_t rsp_lock;
327 IOCBQ *rsp_head; /* deferred completion head */
328 IOCBQ *rsp_tail; /* deferred completion tail */
329 emlxs_thread_t intr_thread;
330
331
332 uint16_t channelno;
333 uint16_t chan_flag;
334
335 #define EMLXS_NEEDS_TRIGGER 1
336
337 /* Protected by EMLXS_TX_CHANNEL_LOCK */
338 emlxs_queue_t nodeq; /* Node service queue */
339
340 kmutex_t channel_cmd_lock;
341 uint32_t timeout;
342
343 /* Channel command counters */
344 uint32_t ulpSendCmd;
345 uint32_t ulpCmplCmd;
346 uint32_t hbaSendCmd;
347 uint32_t hbaCmplCmd;
348 uint32_t hbaSendCmd_sbp;
349 uint32_t hbaCmplCmd_sbp;
350
351 } emlxs_channel_t;
352 typedef emlxs_channel_t CHANNEL;
353
354 /*
355 * Should be able to handle max number of io paths for a
356 * SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS)
357 */
358 #define MAX_CHANNEL EMLXS_MSI_MAX_INTRS
359
360
361 /* Structure used to access adapter rings */
362 typedef struct emlxs_ring
363 {
364 void *fc_cmdringaddr; /* virtual offset for cmd */
365 /* rings */
366 void *fc_rspringaddr; /* virtual offset for rsp */
367 /* rings */
368
369 void *fc_mpon; /* index ptr for match */
370 /* structure */
371 void *fc_mpoff; /* index ptr for match */
372 /* structure */
373 struct emlxs_hba *hba; /* ptr to hba for ring */
374
375 uint8_t fc_numCiocb; /* number of command iocb's */
376 /* per ring */
377 uint8_t fc_numRiocb; /* number of response iocb's */
378 /* per ring */
379 uint8_t fc_rspidx; /* current index in response */
380 /* ring */
381 uint8_t fc_cmdidx; /* current index in command */
382 /* ring */
383 uint8_t fc_port_rspidx;
384 uint8_t fc_port_cmdidx;
385 uint8_t ringno;
386
387 uint16_t fc_missbufcnt; /* buf cnt we need to repost */
388 CHANNEL *channelp;
389
390
391 } emlxs_ring_t;
392 typedef emlxs_ring_t RING;
393
394
395 #ifdef SAN_DIAG_SUPPORT
396 /*
397 * Although right now it's just 1 field, SAN Diag anticipates that this
398 * structure will grow in the future.
399 */
400 typedef struct sd_timestat_level0 {
401 int count;
402 } sd_timestat_level0_t;
403 #endif
404
405 typedef struct emlxs_node
406 {
407 struct emlxs_node *nlp_list_next;
408 struct emlxs_node *nlp_list_prev;
409
410 NAME_TYPE nlp_portname; /* port name */
411 NAME_TYPE nlp_nodename; /* node name */
412
413 uint32_t nlp_DID; /* fibre channel D_ID */
414 uint32_t nlp_oldDID;
415
416 uint16_t nlp_Rpi; /* login id returned by */
417 /* REG_LOGIN */
418 uint16_t nlp_Xri; /* login id returned by */
419 /* REG_LOGIN */
420
421 uint8_t nlp_fcp_info; /* Remote class info */
422
423 /* nlp_fcp_info */
424 #define NLP_FCP_TGT_DEVICE 0x10 /* FCP TGT device */
425 #define NLP_FCP_INI_DEVICE 0x20 /* FCP Initiator device */
426 #define NLP_FCP_2_DEVICE 0x40 /* FCP-2 TGT device */
427 #define NLP_EMLX_VPORT 0x80 /* Virtual port */
428
429 uint32_t nlp_force_rscn;
430 uint32_t nlp_tag; /* Tag used by port_offline */
431 uint32_t flag;
432
433 #define NODE_POOL_ALLOCATED 0x00000001
434
435 SERV_PARM sparm;
436
437 /* Protected by EMLXS_TX_CHANNEL_LOCK */
438 uint32_t nlp_active; /* Node active flag */
439 uint32_t nlp_base;
440 uint32_t nlp_flag[MAX_CHANNEL]; /* Node level channel */
441 /* flags */
442
443 /* nlp_flag */
444 #define NLP_CLOSED 0x1
445 #define NLP_OFFLINE 0x2
446 #define NLP_RPI_XRI 0x4
447
448 uint32_t nlp_tics[MAX_CHANNEL]; /* gate timeout */
449 emlxs_queue_t nlp_tx[MAX_CHANNEL]; /* Transmit Q head */
450 emlxs_queue_t nlp_ptx[MAX_CHANNEL]; /* Priority transmit */
451 /* Queue head */
452 void *nlp_next[MAX_CHANNEL]; /* Service Request */
453 /* Queue pointer used */
454 /* when node needs */
455 /* servicing */
456 #ifdef DHCHAP_SUPPORT
457 emlxs_node_dhc_t node_dhc;
458 #endif /* DHCHAP_SUPPORT */
459
460 #ifdef SAN_DIAG_SUPPORT
461 sd_timestat_level0_t sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS];
462 #endif
463
464 struct RPIobj *rpip; /* SLI4 only */
465 #define EMLXS_NODE_TO_RPI(_p, _n) \
466 ((_n)?((_n->rpip)?_n->rpip:emlxs_rpi_find(_p, _n->nlp_Rpi)):NULL)
467
468 } emlxs_node_t;
469 typedef emlxs_node_t NODELIST;
470
471
472
473 #define NADDR_LEN 6 /* MAC network address length */
474 typedef struct emlxs_fcip_nethdr
475 {
476 NAME_TYPE fc_destname; /* destination port name */
477 NAME_TYPE fc_srcname; /* source port name */
478 } emlxs_fcip_nethdr_t;
479 typedef emlxs_fcip_nethdr_t NETHDR;
480
481
482 #define MEM_NLP 0 /* memory segment to hold node list entries */
483 #define MEM_IOCB 1 /* memory segment to hold iocb commands */
484 #define MEM_MBOX 2 /* memory segment to hold mailbox cmds */
485 #define MEM_BPL 3 /* and to hold buffer ptr lists - SLI2 */
486 #define MEM_BUF 4 /* memory segment to hold buffer data */
487 #define MEM_ELSBUF 4 /* memory segment to hold buffer data */
488 #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */
489 #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */
490 #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */
491
492 #ifdef SFCT_SUPPORT
493 #define FC_MAX_SEG 8
494 #else
495 #define FC_MAX_SEG 7
496 #endif /* SFCT_SUPPORT */
497
498
499 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
500 #define BPL_TO_SGLLEN(_bpl) ((_bpl/12)-2)
501 #define MEM_BPL_SIZE 1024 /* Default size */
502
503 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
504 #define SGL_TO_SGLLEN(_sgl) ((_sgl/16)-2)
505 #define MEM_SGL_SIZE 4096 /* Default size */
506
507 #ifdef EMLXS_I386
508 #define EMLXS_SGLLEN BPL_TO_SGLLEN(MEM_BPL_SIZE)
509 #else /* EMLXS_SPARC */
510 #define EMLXS_SGLLEN 1
511 #endif /* EMLXS_I386 */
512
513 #define MEM_BUF_SIZE 1024
514 #define MEM_BUF_COUNT 64
515
516 #define MEM_ELSBUF_SIZE MEM_BUF_SIZE
517 #define MEM_ELSBUF_COUNT hba->max_nodes
518 #define MEM_IPBUF_SIZE 65535
519 #define MEM_IPBUF_COUNT 60
520 #define MEM_CTBUF_SIZE MAX_CT_PAYLOAD /* (1024*320) */
521 #define MEM_CTBUF_COUNT 8
522 #define MEM_FCTBUF_SIZE 65535
523 #define MEM_FCTBUF_COUNT 128
524
525 typedef struct emlxs_memseg
526 {
527 void *fc_memget_ptr;
528 void *fc_memget_end;
529 void *fc_memput_ptr;
530 void *fc_memput_end;
531
532 void *fc_memstart_virt; /* beginning address */
533 /* of memory block */
534 uint64_t fc_memstart_phys; /* beginning address */
535 /* of memory block */
536 ddi_dma_handle_t fc_mem_dma_handle;
537 ddi_acc_handle_t fc_mem_dat_handle;
538 uint32_t fc_total_memsize;
539 uint32_t fc_memsize; /* size of mem blks */
540 uint32_t fc_numblks; /* no of mem blks */
541 uint32_t fc_memget_cnt; /* no of mem get blks */
542 uint32_t fc_memput_cnt; /* no of mem put blks */
543 uint32_t fc_memflag; /* emlxs_buf_info_t FLAGS */
544 uint32_t fc_reserved; /* used with priority flag */
545 uint32_t fc_memalign;
546 uint32_t fc_memtag;
547 char fc_label[32];
548
549 } emlxs_memseg_t;
550 typedef emlxs_memseg_t MEMSEG;
551
552
553 /* Board stat counters */
554 typedef struct emlxs_stats
555 {
556 uint32_t LinkUp;
557 uint32_t LinkDown;
558 uint32_t LinkEvent;
559 uint32_t LinkMultiEvent;
560
561 uint32_t MboxIssued;
562 uint32_t MboxCompleted; /* MboxError + MbxGood */
563 uint32_t MboxGood;
564 uint32_t MboxError;
565 uint32_t MboxBusy;
566 uint32_t MboxInvalid;
567
568 uint32_t IocbIssued[MAX_CHANNEL];
569 uint32_t IocbReceived[MAX_CHANNEL];
570 uint32_t IocbTxPut[MAX_CHANNEL];
571 uint32_t IocbTxGet[MAX_CHANNEL];
572 uint32_t IocbRingFull[MAX_CHANNEL];
573 uint32_t IocbThrottled;
574
575 uint32_t IntrEvent[8];
576
577 uint32_t FcpIssued;
578 uint32_t FcpCompleted; /* FcpGood + FcpError */
579 uint32_t FcpGood;
580 uint32_t FcpError;
581
582 uint32_t FcpEvent; /* FcpStray + FcpCompleted */
583 uint32_t FcpStray;
584 #ifdef SFCT_SUPPORT
585 uint32_t FctRingEvent;
586 uint32_t FctRingError;
587 uint32_t FctRingDropped;
588 #endif /* SFCT_SUPPORT */
589
590 uint32_t ElsEvent; /* ElsStray + ElsCmplt (cmd + rsp) */
591 uint32_t ElsStray;
592
593 uint32_t ElsCmdIssued;
594 uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */
595 uint32_t ElsCmdGood;
596 uint32_t ElsCmdError;
597
598 uint32_t ElsRspIssued;
599 uint32_t ElsRspCompleted;
600
601 uint32_t ElsRcvEvent; /* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */
602 uint32_t ElsRcvError;
603 uint32_t ElsRcvDropped;
604 uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */
605 uint32_t ElsRscnReceived;
606 uint32_t ElsFlogiReceived;
607 uint32_t ElsPlogiReceived;
608 uint32_t ElsPrliReceived;
609 uint32_t ElsPrloReceived;
610 uint32_t ElsLogoReceived;
611 uint32_t ElsAdiscReceived;
612 uint32_t ElsAuthReceived;
613 uint32_t ElsGenReceived;
614
615 uint32_t CtEvent; /* CtStray + CtCompleted (cmd + rsp) */
616 uint32_t CtStray;
617
618 uint32_t CtCmdIssued;
619 uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */
620 uint32_t CtCmdGood;
621 uint32_t CtCmdError;
622
623 uint32_t CtRspIssued;
624 uint32_t CtRspCompleted;
625
626 uint32_t CtRcvEvent; /* CtRcvError + CtRcvDrop + CtCmdRcvd */
627 uint32_t CtRcvError;
628 uint32_t CtRcvDropped;
629 uint32_t CtCmdReceived;
630
631 uint32_t IpEvent; /* IpStray + IpSeqCmpl + IpBcastCmpl */
632 uint32_t IpStray;
633
634 uint32_t IpSeqIssued;
635 uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */
636 uint32_t IpSeqGood;
637 uint32_t IpSeqError;
638
639 uint32_t IpBcastIssued;
640 uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */
641 uint32_t IpBcastGood;
642 uint32_t IpBcastError;
643
644 uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */
645 uint32_t IpDropped;
646 uint32_t IpSeqReceived;
647 uint32_t IpBcastReceived;
648
649 uint32_t IpUbPosted;
650 uint32_t ElsUbPosted;
651 uint32_t CtUbPosted;
652 #ifdef SFCT_SUPPORT
653 uint32_t FctUbPosted;
654 #endif /* SFCT_SUPPORT */
655
656 uint32_t ResetTime; /* Time of last reset */
657
658 uint32_t ElsTestReceived;
659 uint32_t ElsEstcReceived;
660 uint32_t ElsFarprReceived;
661 uint32_t ElsEchoReceived;
662 uint32_t ElsRlsReceived;
663 uint32_t ElsRtvReceived;
664
665 } emlxs_stats_t;
666
667
668 #define FC_MAX_ADPTMSG (8*28) /* max size of a msg from adapter */
669
670 #define EMLXS_NUM_THREADS 8
671 #define EMLXS_MIN_TASKS 8
672 #define EMLXS_MAX_TASKS 8
673
674 #define EMLXS_NUM_HASH_QUES 32
675 #define EMLXS_DID_HASH(x) ((x) & (EMLXS_NUM_HASH_QUES - 1))
676
677
678 /* pkt_tran_flag */
679 #define FC_TRAN_COMPLETED 0x8000
680
681
682 typedef struct emlxs_dfc_event
683 {
684 uint32_t pid;
685 uint32_t event;
686 uint32_t last_id;
687
688 void *dataout;
689 uint32_t size;
690 uint32_t mode;
691 } emlxs_dfc_event_t;
692
693
694 typedef struct emlxs_hba_event
695 {
696 uint32_t last_id;
697 uint32_t new;
698 uint32_t missed;
699 } emlxs_hba_event_t;
700
701
702 #ifdef SFCT_SUPPORT
703
704 #define TGTPORTSTAT port->fct_stat
705
706 /*
707 * FctP2IOXcnt will count IOs by their fcpDL. Counters
708 * are for buckets of various power of 2 sizes.
709 * Bucket 0 < 512 > 0
710 * Bucket 1 >= 512 < 1024
711 * Bucket 2 >= 1024 < 2048
712 * Bucket 3 >= 2048 < 4096
713 * Bucket 4 >= 4096 < 8192
714 * Bucket 5 >= 8192 < 16K
715 * Bucket 6 >= 16K < 32K
716 * Bucket 7 >= 32K < 64K
717 * Bucket 8 >= 64K < 128K
718 * Bucket 9 >= 128K < 256K
719 * Bucket 10 >= 256K < 512K
720 * Bucket 11 >= 512K < 1MB
721 * Bucket 12 >= 1MB < 2MB
722 * Bucket 13 >= 2MB < 4MB
723 * Bucket 14 >= 4MB < 8MB
724 * Bucket 15 >= 8MB
725 */
726 #define MAX_TGTPORT_IOCNT 16
727
728
729 /*
730 * These routines will bump the right counter, based on
731 * the size of the IO inputed, with the least number of
732 * comparisions. A max of 5 comparisions is only needed
733 * to classify the IO in one of 16 ranges. A binary search
734 * to locate the high bit in the size is used.
735 */
736 #define EMLXS_BUMP_RDIOCTR(port, cnt) \
737 { \
738 /* Use binary search to find the first high bit */ \
739 if (cnt & 0xffff0000) { \
740 if (cnt & 0xff800000) { \
741 TGTPORTSTAT.FctP2IORcnt[15]++; \
742 } \
743 else { \
744 /* It must be 0x007f0000 */ \
745 if (cnt & 0x00700000) { \
746 if (cnt & 0x00400000) { \
747 TGTPORTSTAT.FctP2IORcnt[14]++; \
748 } \
749 else { \
750 /* it must be 0x00300000 */ \
751 if (cnt & 0x00200000) { \
752 TGTPORTSTAT.FctP2IORcnt[13]++; \
753 } \
754 else { \
755 /* It must be 0x00100000 */ \
756 TGTPORTSTAT.FctP2IORcnt[12]++; \
757 } \
758 } \
759 } \
760 else { \
761 /* It must be 0x000f0000 */ \
762 if (cnt & 0x000c0000) { \
763 if (cnt & 0x00080000) { \
764 TGTPORTSTAT.FctP2IORcnt[11]++; \
765 } \
766 else { \
767 /* It must be 0x00040000 */ \
768 TGTPORTSTAT.FctP2IORcnt[10]++; \
769 } \
770 } \
771 else { \
772 /* It must be 0x00030000 */ \
773 if (cnt & 0x00020000) { \
774 TGTPORTSTAT.FctP2IORcnt[9]++; \
775 } \
776 else { \
777 /* It must be 0x00010000 */ \
778 TGTPORTSTAT.FctP2IORcnt[8]++; \
779 } \
780 } \
781 } \
782 } \
783 } \
784 else { \
785 if (cnt & 0x0000fe00) { \
786 if (cnt & 0x0000f000) { \
787 if (cnt & 0x0000c000) { \
788 if (cnt & 0x00008000) { \
789 TGTPORTSTAT.FctP2IORcnt[7]++; \
790 } \
791 else { \
792 /* It must be 0x00004000 */ \
793 TGTPORTSTAT.FctP2IORcnt[6]++; \
794 } \
795 } \
796 else { \
797 /* It must be 0x00000300 */ \
798 if (cnt & 0x00000200) { \
799 TGTPORTSTAT.FctP2IORcnt[5]++; \
800 } \
801 else { \
802 /* It must be 0x00000100 */ \
803 TGTPORTSTAT.FctP2IORcnt[4]++; \
804 } \
805 } \
806 } \
807 else { \
808 /* It must be 0x00000e00 */ \
809 if (cnt & 0x00000800) { \
810 TGTPORTSTAT.FctP2IORcnt[3]++; \
811 } \
812 else { \
813 /* It must be 0x00000600 */ \
814 if (cnt & 0x00000400) { \
815 TGTPORTSTAT.FctP2IORcnt[2]++; \
816 } \
817 else { \
818 /* It must be 0x00000200 */ \
819 TGTPORTSTAT.FctP2IORcnt[1]++; \
820 } \
821 } \
822 } \
823 } \
824 else { \
825 /* It must be 0x000001ff */ \
826 TGTPORTSTAT.FctP2IORcnt[0]++; \
827 } \
828 } \
829 }
830
831
832 #define EMLXS_BUMP_WRIOCTR(port, cnt) \
833 { \
834 /* Use binary search to find the first high bit */ \
835 if (cnt & 0xffff0000) { \
836 if (cnt & 0xff800000) { \
837 TGTPORTSTAT.FctP2IOWcnt[15]++; \
838 } \
839 else { \
840 /* It must be 0x007f0000 */ \
841 if (cnt & 0x00700000) { \
842 if (cnt & 0x00400000) { \
843 TGTPORTSTAT.FctP2IOWcnt[14]++; \
844 } \
845 else { \
846 /* It must be 0x00300000 */ \
847 if (cnt & 0x00200000) { \
848 TGTPORTSTAT.FctP2IOWcnt[13]++; \
849 } \
850 else { \
851 /* It must be 0x00100000 */ \
852 TGTPORTSTAT.FctP2IOWcnt[12]++; \
853 } \
854 } \
855 } \
856 else { \
857 /* It must be 0x000f0000 */ \
858 if (cnt & 0x000c0000) { \
859 if (cnt & 0x00080000) { \
860 TGTPORTSTAT.FctP2IOWcnt[11]++; \
861 } \
862 else { \
863 /* it must be 0x00040000 */ \
864 TGTPORTSTAT.FctP2IOWcnt[10]++; \
865 } \
866 } \
867 else { \
868 /* It must be 0x00030000 */ \
869 if (cnt & 0x00020000) { \
870 TGTPORTSTAT.FctP2IOWcnt[9]++; \
871 } \
872 else { \
873 /* It must be 0x00010000 */ \
874 TGTPORTSTAT.FctP2IOWcnt[8]++; \
875 } \
876 } \
877 } \
878 } \
879 } \
880 else { \
881 if (cnt & 0x0000fe00) { \
882 if (cnt & 0x0000f000) { \
883 if (cnt & 0x0000c000) { \
884 if (cnt & 0x00008000) { \
885 TGTPORTSTAT.FctP2IOWcnt[7]++; \
886 } \
887 else { \
888 /* It must be 0x00004000 */ \
889 TGTPORTSTAT.FctP2IOWcnt[6]++; \
890 } \
891 } \
892 else { \
893 /* It must be 0x00000300 */ \
894 if (cnt & 0x00000200) { \
895 TGTPORTSTAT.FctP2IOWcnt[5]++; \
896 } \
897 else { \
898 /* It must be 0x00000100 */ \
899 TGTPORTSTAT.FctP2IOWcnt[4]++; \
900 } \
901 } \
902 } \
903 else { \
904 /* It must be 0x00000e00 */ \
905 if (cnt & 0x00000800) { \
906 TGTPORTSTAT.FctP2IOWcnt[3]++; \
907 } \
908 else { \
909 /* It must be 0x00000600 */ \
910 if (cnt & 0x00000400) { \
911 TGTPORTSTAT.FctP2IOWcnt[2]++; \
912 } \
913 else { \
914 /* It must be 0x00000200 */ \
915 TGTPORTSTAT.FctP2IOWcnt[1]++; \
916 } \
917 } \
918 } \
919 } \
920 else { \
921 /* It must be 0x000001ff */ \
922 TGTPORTSTAT.FctP2IOWcnt[0]++; \
923 } \
924 } \
925 }
926
927 typedef struct emlxs_tgtport_stat
928 {
929 /* IO counters */
930 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */
931 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */
932 uint64_t FctIOCmdCnt; /* Other, ie TUR */
933 uint64_t FctCmdReceived; /* total IOs */
934 uint64_t FctReadBytes; /* total read bytes */
935 uint64_t FctWriteBytes; /* total write bytes */
936
937 /* IOCB handling counters */
938 uint64_t FctEvent; /* FctStray + FctCompleted */
939 uint64_t FctCompleted; /* FctCmplGood + FctCmplError */
940 uint64_t FctCmplGood;
941
942 uint32_t FctCmplError;
943 uint32_t FctStray;
944
945 /* Fct event counters */
946 uint32_t FctRcvDropped;
947 uint32_t FctOverQDepth;
948 uint32_t FctOutstandingIO;
949 uint32_t FctFailedPortRegister;
950 uint32_t FctPortRegister;
951 uint32_t FctPortDeregister;
952
953 uint32_t FctAbortSent;
954 uint32_t FctNoBuffer;
955 uint32_t FctScsiStatusErr;
956 uint32_t FctScsiQfullErr;
957 uint32_t FctScsiResidOver;
958 uint32_t FctScsiResidUnder;
959 uint32_t FctScsiSenseErr;
960
961 uint32_t FctFiller1;
962 } emlxs_tgtport_stat_t;
963
964 #ifdef FCT_IO_TRACE
965 #define MAX_IO_TRACE 67
966 typedef struct emlxs_iotrace
967 {
968 fct_cmd_t *fct_cmd;
969 uint32_t xri;
970 uint8_t marker; /* 0xff */
971 uint8_t trc[MAX_IO_TRACE]; /* trc[0] = index */
972 } emlxs_iotrace_t;
973 #endif /* FCT_IO_TRACE */
974 #endif /* SFCT_SUPPORT */
975
976
977 #include <emlxs_fcf.h>
978
979 /*
980 * Port Information Data Structure
981 */
982
983 typedef struct emlxs_port
984 {
985 struct emlxs_hba *hba;
986
987 /* Virtual port management */
988 struct VPIobj VPIobj;
989 uint32_t vpi;
990
991 uint32_t flag;
992 #define EMLXS_PORT_ENABLE 0x00000001
993 #define EMLXS_PORT_BOUND 0x00000002
994
995 #define EMLXS_PORT_REG_VPI 0x00010000 /* SLI3 */
996 #define EMLXS_PORT_REG_VPI_CMPL 0x00020000 /* SLI3 */
997
998 #define EMLXS_PORT_IP_UP 0x00000010
999 #define EMLXS_PORT_CONFIG 0x00000020
1000 #define EMLXS_PORT_RESTRICTED 0x00000040 /* Restrict logins */
1001 #define EMLXS_PORT_FLOGI_CMPL 0x00000080
1002
1003 #define EMLXS_PORT_RESET_MASK 0x0000FFFF /* Flags to keep */
1004 /* across hard reset */
1005 #define EMLXS_PORT_LINKDOWN_MASK 0xFFFFFF7F /* Flags to keep */
1006 /* across link reset */
1007
1008 uint32_t options;
1009 #define EMLXS_OPT_RESTRICT 0x00000001 /* Force restricted */
1010 /* logins */
1011 #define EMLXS_OPT_UNRESTRICT 0x00000002 /* Force Unrestricted */
1012 /* logins */
1013 #define EMLXS_OPT_RESTRICT_MASK 0x00000003
1014
1015
1016 /* FC world wide names */
1017 NAME_TYPE wwnn;
1018 NAME_TYPE wwpn;
1019 char snn[256];
1020 char spn[256];
1021
1022 /* Common service paramters */
1023 SERV_PARM sparam;
1024 SERV_PARM fabric_sparam;
1025 SERV_PARM prev_fabric_sparam;
1026
1027 /* fc_id management */
1028 uint32_t did;
1029 uint32_t prev_did;
1030
1031 /* support FC_PORT_GET_P2P_INFO only */
1032 uint32_t rdid;
1033
1034 /* FC_AL management */
1035 uint8_t lip_type;
1036 uint8_t alpa_map[128];
1037
1038 /* Node management */
1039 emlxs_node_t node_base;
1040 uint32_t node_count;
1041 krwlock_t node_rwlock;
1042 emlxs_node_t *node_table[EMLXS_NUM_HASH_QUES];
1043
1044 /* Polled packet management */
1045 kcondvar_t pkt_lock_cv; /* pkt polling */
1046 kmutex_t pkt_lock; /* pkt polling */
1047
1048 /* ULP */
1049 uint32_t ulp_statec;
1050 void (*ulp_statec_cb) (); /* Port state change */
1051 /* callback routine */
1052 void (*ulp_unsol_cb) (); /* unsolicited event */
1053 /* callback routine */
1054 opaque_t ulp_handle;
1055
1056 /* ULP unsolicited buffers */
1057 kmutex_t ub_lock;
1058 uint32_t ub_count;
1059 emlxs_unsol_buf_t *ub_pool;
1060 uint32_t ub_post[MAX_CHANNEL];
1061 uint32_t ub_timer;
1062
1063 emlxs_ub_priv_t *ub_wait_head; /* Unsolicited IO received */
1064 /* before link up */
1065 emlxs_ub_priv_t *ub_wait_tail; /* Unsolicited IO received */
1066 /* before link up */
1067
1068
1069 #ifdef DHCHAP_SUPPORT
1070 emlxs_port_dhc_t port_dhc;
1071 #endif /* DHCHAP_SUPPORT */
1072
1073 uint16_t ini_mode;
1074 uint16_t tgt_mode;
1075
1076 #ifdef SFCT_SUPPORT
1077
1078 #define FCT_BUF_COUNT_512 256
1079 #define FCT_BUF_COUNT_8K 128
1080 #define FCT_BUF_COUNT_64K 64
1081 #define FCT_BUF_COUNT_128K 64
1082 #define FCT_MAX_BUCKETS 16
1083 #define FCT_DMEM_MAX_BUF_SIZE 131072 /* 128K */
1084 #define FCT_DMEM_MAX_BUF_SEGMENT 8388608 /* 8M */
1085
1086 struct emlxs_fct_dmem_bucket dmem_bucket[FCT_MAX_BUCKETS];
1087
1088 char cfd_name[24];
1089 stmf_port_provider_t *port_provider;
1090 fct_local_port_t *fct_port;
1091 uint32_t fct_flags;
1092
1093 #define FCT_STATE_PORT_ONLINE 0x00000001
1094 #define FCT_STATE_NOT_ACKED 0x00000002
1095 #define FCT_STATE_LINK_UP 0x00000010
1096 #define FCT_STATE_LINK_UP_ACKED 0x00000020
1097
1098 emlxs_tgtport_stat_t fct_stat;
1099
1100 /* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
1101 emlxs_buf_t *fct_wait_head;
1102 emlxs_buf_t *fct_wait_tail;
1103
1104 /* Used to save context for deferred unsol FLOGIs */
1105 fct_flogi_xchg_t fx;
1106
1107 #ifdef FCT_IO_TRACE
1108 emlxs_iotrace_t *iotrace;
1109 uint16_t iotrace_cnt;
1110 uint16_t iotrace_index;
1111 kmutex_t iotrace_mtx;
1112 #endif /* FCT_IO_TRACE */
1113
1114 #endif /* SFCT_SUPPORT */
1115
1116 #ifdef SAN_DIAG_SUPPORT
1117 uint8_t sd_io_latency_state;
1118 #define SD_INVALID 0x00
1119 #define SD_COLLECTING 0x01
1120 #define SD_STOPPED 0x02
1121
1122 /* SD event management list */
1123 uint32_t sd_event_mask; /* bit-mask */
1124 emlxs_dfc_event_t sd_events[MAX_DFC_EVENTS];
1125 #endif
1126
1127 } emlxs_port_t;
1128
1129
1130 /* Host Attn reg */
1131 #define FC_HA_REG(_hba) ((volatile uint32_t *) \
1132 ((_hba)->sli.sli3.ha_reg_addr))
1133
1134 /* Chip Attn reg */
1135 #define FC_CA_REG(_hba) ((volatile uint32_t *) \
1136 ((_hba)->sli.sli3.ca_reg_addr))
1137
1138 /* Host Status reg */
1139 #define FC_HS_REG(_hba) ((volatile uint32_t *) \
1140 ((_hba)->sli.sli3.hs_reg_addr))
1141
1142 /* Host Cntl reg */
1143 #define FC_HC_REG(_hba) ((volatile uint32_t *) \
1144 ((_hba)->sli.sli3.hc_reg_addr))
1145
1146 /* BIU Configuration reg */
1147 #define FC_BC_REG(_hba) ((volatile uint32_t *) \
1148 ((_hba)->sli.sli3.bc_reg_addr))
1149
1150 /* Used by SBUS adapter */
1151 /* TITAN Cntl reg */
1152 #define FC_SHC_REG(_hba) ((volatile uint32_t *) \
1153 ((_hba)->sli.sli3.shc_reg_addr))
1154
1155 /* TITAN Status reg */
1156 #define FC_SHS_REG(_hba) ((volatile uint32_t *) \
1157 ((_hba)->sli.sli3.shs_reg_addr))
1158
1159 /* TITAN Update reg */
1160 #define FC_SHU_REG(_hba) ((volatile uint32_t *) \
1161 ((_hba)->sli.sli3.shu_reg_addr))
1162
1163 /* MPU Semaphore reg */
1164 #define FC_SEMA_REG(_hba) ((volatile uint32_t *)\
1165 ((_hba)->sli.sli4.MPUEPSemaphore_reg_addr))
1166
1167 /* Bootstrap Mailbox Doorbell reg */
1168 #define FC_MBDB_REG(_hba) ((volatile uint32_t *) \
1169 ((_hba)->sli.sli4.MBDB_reg_addr))
1170
1171 /* MQ Doorbell reg */
1172 #define FC_MQDB_REG(_hba) ((volatile uint32_t *) \
1173 ((_hba)->sli.sli4.MQDB_reg_addr))
1174
1175 /* CQ Doorbell reg */
1176 #define FC_CQDB_REG(_hba) ((volatile uint32_t *) \
1177 ((_hba)->sli.sli4.CQDB_reg_addr))
1178
1179 /* WQ Doorbell reg */
1180 #define FC_WQDB_REG(_hba) ((volatile uint32_t *) \
1181 ((_hba)->sli.sli4.WQDB_reg_addr))
1182
1183 /* RQ Doorbell reg */
1184 #define FC_RQDB_REG(_hba) ((volatile uint32_t *) \
1185 ((_hba)->sli.sli4.RQDB_reg_addr))
1186
1187
1188 #define FC_SLIM2_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim2.virt)
1189
1190 #define FC_SLIM1_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim_addr)
1191
1192 #define FC_MAILBOX(_hba) (((_hba)->flag & FC_SLIM2_MODE) ? \
1193 FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba))
1194
1195 #define WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\
1196 (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp), \
1197 (uint32_t)(_value))
1198
1199 #define READ_CSR_REG(_hba, _regp) ddi_get32(\
1200 (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp))
1201
1202 #define WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\
1203 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp), \
1204 (uint32_t)(_value))
1205
1206 #define READ_SLIM_ADDR(_hba, _regp) ddi_get32(\
1207 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp))
1208
1209 #define WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\
1210 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1211 (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1212
1213 #define READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\
1214 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1215 (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1216
1217 /* Used by SBUS adapter */
1218 #define WRITE_SBUS_CSR_REG(_hba, _regp, _value) ddi_put32(\
1219 (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp), \
1220 (uint32_t)(_value))
1221
1222 #define READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\
1223 (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp))
1224
1225 #define SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\
1226 (_hba)->sli.sli3.sbus_flash_acc_handle, \
1227 (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1228 (_offset)), (uint8_t)(_value))
1229
1230 #define SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\
1231 (_hba)->sli.sli3.sbus_flash_acc_handle, \
1232 (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1233 (_offset)))
1234
1235 /* SLI4 registers */
1236 #define WRITE_BAR1_REG(_hba, _regp, _value) ddi_put32(\
1237 (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp), \
1238 (uint32_t)(_value))
1239
1240 #define READ_BAR1_REG(_hba, _regp) ddi_get32(\
1241 (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp))
1242
1243 #define WRITE_BAR2_REG(_hba, _regp, _value) ddi_put32(\
1244 (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp), \
1245 (uint32_t)(_value))
1246
1247 #define READ_BAR2_REG(_hba, _regp) ddi_get32(\
1248 (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp))
1249
1250
1251 #define EMLXS_STATE_CHANGE(_hba, _state)\
1252 { \
1253 mutex_enter(&EMLXS_PORT_LOCK); \
1254 EMLXS_STATE_CHANGE_LOCKED((_hba), (_state)); \
1255 mutex_exit(&EMLXS_PORT_LOCK); \
1256 }
1257
1258 /* Used when EMLXS_PORT_LOCK is already held */
1259 #define EMLXS_STATE_CHANGE_LOCKED(_hba, _state) \
1260 { \
1261 if ((_hba)->state != (_state)) \
1262 { \
1263 uint32_t _st = _state; \
1264 EMLXS_MSGF(EMLXS_CONTEXT, \
1265 &emlxs_state_msg, "%s --> %s", \
1266 emlxs_ffstate_xlate((_hba)->state), \
1267 emlxs_ffstate_xlate(_state)); \
1268 (_hba)->state = (_state); \
1269 if ((_st) == FC_ERROR) \
1270 { \
1271 (_hba)->flag |= FC_HARDWARE_ERROR; \
1272 } \
1273 } \
1274 }
1275
1276 #ifdef FMA_SUPPORT
1277 #define EMLXS_CHK_ACC_HANDLE(_hba, _acc) \
1278 if (emlxs_fm_check_acc_handle(_hba, _acc) != DDI_FM_OK) { \
1279 EMLXS_MSGF(EMLXS_CONTEXT, \
1280 &emlxs_invalid_access_handle_msg, NULL); \
1281 }
1282 #endif /* FMA_SUPPORT */
1283
1284 /*
1285 * This is the HBA control area for the adapter
1286 */
1287
1288 #ifdef MODSYM_SUPPORT
1289
1290 typedef struct emlxs_modsym
1291 {
1292 ddi_modhandle_t mod_fctl; /* For Leadville */
1293
1294 /* Leadville (fctl) */
1295 int (*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *);
1296 int (*fc_fca_detach)(dev_info_t *);
1297 int (*fc_fca_init)(struct dev_ops *);
1298
1299 #ifdef SFCT_SUPPORT
1300 uint32_t fct_modopen;
1301 uint32_t reserved; /* Padding for alignment */
1302
1303 ddi_modhandle_t mod_fct; /* For Comstar */
1304 ddi_modhandle_t mod_stmf; /* For Comstar */
1305
1306 /* Comstar (fct) */
1307 void* (*fct_alloc)(fct_struct_id_t, int, int);
1308 void (*fct_free)(void *);
1309 void* (*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *,
1310 uint16_t, uint16_t);
1311 int (*fct_register_local_port)(fct_local_port_t *);
1312 void (*fct_deregister_local_port)(fct_local_port_t *);
1313 void (*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t);
1314 void (*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *);
1315 void (*fct_ctl)(void *, int, void *);
1316 void (*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t);
1317 void (*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t);
1318 void (*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t);
1319 void (*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *,
1320 uint32_t);
1321 fct_status_t (*fct_port_shutdown)
1322 (fct_local_port_t *, uint32_t, char *);
1323 fct_status_t (*fct_port_initialize)
1324 (fct_local_port_t *, uint32_t, char *);
1325 void (*fct_cmd_fca_aborted)
1326 (fct_cmd_t *, fct_status_t, int);
1327 fct_status_t (*fct_handle_rcvd_flogi)
1328 (fct_local_port_t *, fct_flogi_xchg_t *);
1329
1330 /* Comstar (stmf) */
1331 void* (*stmf_alloc)(stmf_struct_id_t, int, int);
1332 void (*stmf_free)(void *);
1333 void (*stmf_deregister_port_provider) (stmf_port_provider_t *);
1334 int (*stmf_register_port_provider) (stmf_port_provider_t *);
1335 #endif /* SFCT_SUPPORT */
1336 } emlxs_modsym_t;
1337 extern emlxs_modsym_t emlxs_modsym;
1338
1339 #define MODSYM(_f) emlxs_modsym._f
1340
1341 #else
1342
1343 #define MODSYM(_f) _f
1344
1345 #endif /* MODSYM_SUPPORT */
1346
1347
1348
1349 typedef struct RPIHdrTmplate
1350 {
1351 uint32_t Word[16]; /* 64 bytes */
1352 } RPIHdrTmplate_t;
1353
1354
1355 typedef struct EQ_DESC
1356 {
1357 uint16_t host_index;
1358 uint16_t max_index;
1359 uint16_t qid;
1360 uint16_t msix_vector;
1361 kmutex_t lastwq_lock;
1362 uint16_t lastwq;
1363 MBUF_INFO addr;
1364 } EQ_DESC_t;
1365
1366
1367 typedef struct CQ_DESC
1368 {
1369 uint16_t host_index;
1370 uint16_t max_index;
1371 uint16_t qid;
1372 uint16_t eqid;
1373 uint16_t type;
1374 #define EMLXS_CQ_TYPE_GROUP1 1 /* associated with a MQ and async events */
1375 #define EMLXS_CQ_TYPE_GROUP2 2 /* associated with a WQ and RQ */
1376 uint16_t rsvd;
1377
1378 MBUF_INFO addr;
1379 CHANNEL *channelp; /* ptr to CHANNEL associated with CQ */
1380
1381 } CQ_DESC_t;
1382
1383
1384 typedef struct WQ_DESC
1385 {
1386 uint16_t host_index;
1387 uint16_t max_index;
1388 uint16_t port_index;
1389 uint16_t release_depth;
1390 #define WQE_RELEASE_DEPTH (8 * EMLXS_NUM_WQ_PAGES)
1391 uint16_t qid;
1392 uint16_t cqid;
1393 MBUF_INFO addr;
1394 } WQ_DESC_t;
1395
1396
1397 typedef struct RQ_DESC
1398 {
1399 uint16_t host_index;
1400 uint16_t max_index;
1401 uint16_t qid;
1402 uint16_t cqid;
1403
1404 MBUF_INFO addr;
1405 MBUF_INFO rqb[RQ_DEPTH];
1406
1407 kmutex_t lock;
1408
1409 } RQ_DESC_t;
1410
1411
1412 typedef struct RXQ_DESC
1413 {
1414 kmutex_t lock;
1415 emlxs_queue_t active;
1416
1417 } RXQ_DESC_t;
1418
1419
1420 typedef struct MQ_DESC
1421 {
1422 uint16_t host_index;
1423 uint16_t max_index;
1424 uint16_t qid;
1425 uint16_t cqid;
1426 MBUF_INFO addr;
1427 } MQ_DESC_t;
1428
1429
1430 /* Define the number of queues the driver will be using */
1431 #define EMLXS_MAX_EQS EMLXS_MSI_MAX_INTRS
1432 #define EMLXS_MAX_WQS EMLXS_MSI_MAX_INTRS
1433 #define EMLXS_MAX_RQS 2 /* ONLY 1 pair is allowed */
1434 #define EMLXS_MAX_MQS 1
1435
1436 /* One CQ for each WQ & (RQ pair) plus one for the MQ */
1437 #define EMLXS_MAX_CQS (EMLXS_MAX_WQS + (EMLXS_MAX_RQS/2) + 1)
1438
1439 /* The First CQ created is ALWAYS for mbox / event handling */
1440 #define EMLXS_CQ_MBOX 0
1441
1442 /* The Second CQ created is ALWAYS for unsol rcv handling */
1443 /* At this time we are allowing ONLY 1 pair of RQs */
1444 #define EMLXS_CQ_RCV 1
1445
1446 /* The remaining CQs are for WQ completions */
1447 #define EMLXS_CQ_OFFSET_WQ 2
1448
1449
1450 /* FCFI RQ Configuration */
1451 #define EMLXS_FCFI_RQ0_INDEX 0
1452 #define EMLXS_FCFI_RQ0_RMASK 0 /* match all */
1453 #define EMLXS_FCFI_RQ0_RCTL 0 /* match all */
1454 #define EMLXS_FCFI_RQ0_TMASK 0 /* match all */
1455 #define EMLXS_FCFI_RQ0_TYPE 0 /* match all */
1456
1457 /* Define the maximum value for a Queue Id */
1458 #define EMLXS_MAX_EQ_IDS 256
1459 #define EMLXS_MAX_CQ_IDS 1024
1460 #define EMLXS_MAX_WQ_IDS 1024
1461 #define EMLXS_MAX_RQ_IDS 4
1462
1463 #define EMLXS_RXQ_ELS 0
1464 #define EMLXS_RXQ_CT 1
1465 #define EMLXS_MAX_RXQS 2
1466
1467 #define PCI_CONFIG_SIZE 0x80
1468
1469 typedef struct emlxs_sli3
1470 {
1471 /* SLIM management */
1472 MATCHMAP slim2;
1473
1474 /* HBQ management */
1475 uint32_t hbq_count; /* Total number of HBQs */
1476 /* configured */
1477 HBQ_INIT_t hbq_table[EMLXS_NUM_HBQ];
1478
1479 /* Adapter memory management */
1480 caddr_t csr_addr;
1481 caddr_t slim_addr;
1482 ddi_acc_handle_t csr_acc_handle;
1483 ddi_acc_handle_t slim_acc_handle;
1484
1485 /* SBUS adapter management */
1486 caddr_t sbus_flash_addr; /* Virt addr of R/W */
1487 /* Flash */
1488 caddr_t sbus_core_addr; /* Virt addr of TITAN */
1489 /* CORE */
1490 caddr_t sbus_csr_addr; /* Virt addr of TITAN */
1491 /* CSR */
1492 ddi_acc_handle_t sbus_flash_acc_handle;
1493 ddi_acc_handle_t sbus_core_acc_handle;
1494 ddi_acc_handle_t sbus_csr_handle;
1495
1496 /* SLI 2/3 Adapter register management */
1497 uint32_t *bc_reg_addr; /* virtual offset for BIU */
1498 /* config reg */
1499 uint32_t *ha_reg_addr; /* virtual offset for host */
1500 /* attn reg */
1501 uint32_t *hc_reg_addr; /* virtual offset for host */
1502 /* ctl reg */
1503 uint32_t *ca_reg_addr; /* virtual offset for FF */
1504 /* attn reg */
1505 uint32_t *hs_reg_addr; /* virtual offset for */
1506 /* status reg */
1507 uint32_t *shc_reg_addr; /* virtual offset for SBUS */
1508 /* Ctrl reg */
1509 uint32_t *shs_reg_addr; /* virtual offset for SBUS */
1510 /* Status reg */
1511 uint32_t *shu_reg_addr; /* virtual offset for SBUS */
1512 /* Update reg */
1513 uint16_t hgp_ring_offset;
1514 uint16_t hgp_hbq_offset;
1515 uint16_t iocb_cmd_size;
1516 uint16_t iocb_rsp_size;
1517 uint32_t hc_copy; /* local copy of HC register */
1518
1519 /* Ring management */
1520 uint32_t ring_count;
1521 emlxs_ring_t ring[MAX_RINGS];
1522 kmutex_t ring_cmd_lock[MAX_RINGS];
1523 uint8_t ring_masks[4]; /* number of masks/rings used */
1524 uint8_t ring_rval[6];
1525 uint8_t ring_rmask[6];
1526 uint8_t ring_tval[6];
1527 uint8_t ring_tmask[6];
1528
1529 /* Protected by EMLXS_FCTAB_LOCK */
1530 #ifdef EMLXS_SPARC
1531 MEMSEG fcp_bpl_seg;
1532 MATCHMAP **fcp_bpl_table; /* iotag table for */
1533 /* bpl buffers */
1534 #endif /* EMLXS_SPARC */
1535 uint32_t mem_bpl_size;
1536 } emlxs_sli3_t;
1537
1538 typedef struct emlxs_sli4
1539 {
1540 MATCHMAP bootstrapmb;
1541 caddr_t bar1_addr;
1542 caddr_t bar2_addr;
1543 ddi_acc_handle_t bar1_acc_handle;
1544 ddi_acc_handle_t bar2_acc_handle;
1545
1546 /* SLI4 Adapter register management */
1547 uint32_t *MPUEPSemaphore_reg_addr;
1548 uint32_t *MBDB_reg_addr;
1549
1550 uint32_t *CQDB_reg_addr;
1551 uint32_t *MQDB_reg_addr;
1552 uint32_t *WQDB_reg_addr;
1553 uint32_t *RQDB_reg_addr;
1554
1555 uint32_t flag;
1556 #define EMLXS_SLI4_INTR_ENABLED 0x00000001
1557 #define EMLXS_SLI4_HW_ERROR 0x00000002
1558 #define EMLXS_SLI4_DOWN_LINK 0x00000004
1559
1560 uint16_t XRICount;
1561 uint16_t XRIBase;
1562 uint16_t RPICount;
1563 uint16_t RPIBase;
1564 uint16_t VPICount;
1565 uint16_t VPIBase;
1566 uint16_t VFICount;
1567 uint16_t VFIBase;
1568 uint16_t FCFICount;
1569
1570 kmutex_t fcf_lock;
1571 FCFTable_t fcftab;
1572 VFIobj_t *VFI_table;
1573
1574 /* Save Config Region 23 info */
1575 tlv_fcoe_t cfgFCOE;
1576 tlv_fcfconnectlist_t cfgFCF;
1577
1578 MBUF_INFO slim2;
1579 MBUF_INFO dump_region;
1580 #define EMLXS_DUMP_REGION_SIZE 1024
1581
1582 RPIobj_t *RPIp;
1583 MBUF_INFO HeaderTmplate;
1584 XRIobj_t *XRIp;
1585
1586 /* Double linked list for available XRIs */
1587 XRIobj_t *XRIfree_f;
1588 XRIobj_t *XRIfree_b;
1589 uint32_t xrif_count;
1590 uint32_t mem_sgl_size;
1591
1592 /* Double linked list for XRIs in use */
1593 XRIobj_t *XRIinuse_f;
1594 XRIobj_t *XRIinuse_b;
1595 uint32_t xria_count;
1596
1597 kmutex_t que_lock[EMLXS_MAX_WQS];
1598 EQ_DESC_t eq[EMLXS_MAX_EQS];
1599 CQ_DESC_t cq[EMLXS_MAX_CQS];
1600 WQ_DESC_t wq[EMLXS_MAX_WQS];
1601 RQ_DESC_t rq[EMLXS_MAX_RQS];
1602 MQ_DESC_t mq;
1603
1604 /* Used to map a queue ID to a queue DESC_t */
1605 uint16_t eq_map[EMLXS_MAX_EQ_IDS];
1606 uint16_t cq_map[EMLXS_MAX_CQ_IDS];
1607 uint16_t wq_map[EMLXS_MAX_WQ_IDS];
1608 uint16_t rq_map[EMLXS_MAX_RQ_IDS];
1609
1610 RXQ_DESC_t rxq[EMLXS_MAX_RXQS];
1611
1612 uint32_t ue_mask_lo;
1613 uint32_t ue_mask_hi;
1614
1615 } emlxs_sli4_t;
1616
1617
1618 typedef struct emlxs_sli_api
1619 {
1620 int (*sli_map_hdw)();
1621 void (*sli_unmap_hdw)();
1622 int32_t (*sli_online)();
1623 void (*sli_offline)();
1624 uint32_t (*sli_hba_reset)();
1625 void (*sli_hba_kill)();
1626 void (*sli_issue_iocb_cmd)();
1627 uint32_t (*sli_issue_mbox_cmd)();
1628 uint32_t (*sli_prep_fct_iocb)();
1629 uint32_t (*sli_prep_fcp_iocb)();
1630 uint32_t (*sli_prep_ip_iocb)();
1631 uint32_t (*sli_prep_els_iocb)();
1632 uint32_t (*sli_prep_ct_iocb)();
1633 void (*sli_poll_intr)();
1634 int32_t (*sli_intx_intr)();
1635 uint32_t (*sli_msi_intr)();
1636 void (*sli_disable_intr)();
1637 void (*sli_timer)();
1638 void (*sli_poll_erratt)();
1639
1640 } emlxs_sli_api_t;
1641
1642
1643 typedef struct emlxs_hba
1644 {
1645 dev_info_t *dip;
1646 int32_t emlxinst;
1647 int32_t ddiinst;
1648 uint8_t pci_function_number;
1649 uint8_t pci_device_number;
1650 uint8_t pci_bus_number;
1651 uint8_t pci_cap_offset[PCI_CAP_MAX_PTR];
1652
1653 #ifdef FMA_SUPPORT
1654 int32_t fm_caps; /* FMA capabilities */
1655 #endif /* FMA_SUPPORT */
1656 fc_fca_tran_t *fca_tran;
1657
1658 /* DMA attributes */
1659 ddi_dma_attr_t dma_attr;
1660 ddi_dma_attr_t dma_attr_ro;
1661 ddi_dma_attr_t dma_attr_1sg;
1662 ddi_dma_attr_t dma_attr_fcip_rsp;
1663
1664 /* HBA Info */
1665 emlxs_model_t model_info;
1666 emlxs_vpd_t vpd; /* vital product data */
1667 NAME_TYPE wwnn;
1668 NAME_TYPE wwpn;
1669 char snn[256];
1670 char spn[256];
1671 PROG_ID load_list[MAX_LOAD_ENTRY];
1672 WAKE_UP_PARMS wakeup_parms;
1673 uint32_t max_nodes;
1674 uint32_t io_throttle;
1675 uint32_t io_active;
1676 uint32_t bus_type;
1677 #define PCI_FC 0
1678 #define SBUS_FC 1
1679
1680 /* Link management */
1681 uint32_t link_event_tag;
1682 uint8_t topology;
1683 uint8_t linkspeed;
1684 uint16_t qos_linkspeed;
1685 uint32_t linkup_wait_flag;
1686 kcondvar_t linkup_lock_cv;
1687 kmutex_t linkup_lock;
1688
1689 /* Memory Pool management */
1690 emlxs_memseg_t memseg[FC_MAX_SEG]; /* memory for buffer */
1691 /* structures */
1692 kmutex_t memget_lock; /* locks all memory pools get */
1693 kmutex_t memput_lock; /* locks all memory pools put */
1694
1695 /* Fibre Channel Service Parameters */
1696 SERV_PARM sparam;
1697 uint32_t fc_edtov; /* E_D_TOV timer value */
1698 uint32_t fc_arbtov; /* ARB_TOV timer value */
1699 uint32_t fc_ratov; /* R_A_TOV timer value */
1700 uint32_t fc_rttov; /* R_T_TOV timer value */
1701 uint32_t fc_altov; /* AL_TOV timer value */
1702 uint32_t fc_crtov; /* C_R_TOV timer value */
1703 uint32_t fc_citov; /* C_I_TOV timer value */
1704
1705 /* Adapter State management */
1706 int32_t state;
1707 #define FC_ERROR 0x01 /* Adapter shutdown */
1708 #define FC_KILLED 0x02 /* Adapter interlocked/killed */
1709 #define FC_WARM_START 0x03 /* Adapter reset, but not restarted */
1710 #define FC_INIT_START 0x10 /* Adapter restarted */
1711 #define FC_INIT_NVPARAMS 0x11
1712 #define FC_INIT_REV 0x12
1713 #define FC_INIT_CFGPORT 0x13
1714 #define FC_INIT_CFGRING 0x14
1715 #define FC_INIT_INITLINK 0x15
1716 #define FC_LINK_DOWN 0x20
1717 #define FC_LINK_DOWN_PERSIST 0x21
1718 #define FC_LINK_UP 0x30
1719 #define FC_CLEAR_LA 0x31
1720 #define FC_READY 0x40
1721
1722 uint32_t flag;
1723 #define FC_ONLINING_MODE 0x00000001
1724 #define FC_ONLINE_MODE 0x00000002
1725 #define FC_OFFLINING_MODE 0x00000004
1726 #define FC_OFFLINE_MODE 0x00000008
1727
1728 #define FC_NPIV_ENABLED 0x00000010 /* NPIV enabled on adapter */
1729 #define FC_NPIV_SUPPORTED 0x00000020 /* NPIV supported on fabric */
1730 #define FC_NPIV_UNSUPPORTED 0x00000040 /* NPIV unsupported on fabric */
1731 #define FC_NPIV_LINKUP 0x00000100 /* NPIV enabled, supported, */
1732 /* and link is ready */
1733 #define FC_NPIV_DELAY_REQUIRED 0x00000200 /* Delay issuing FLOGI/FDISC */
1734 /* and NameServer cmds */
1735
1736 #define FC_BOOTSTRAPMB_INIT 0x00000400
1737 #define FC_FIP_SUPPORTED 0x00000800 /* FIP supported */
1738
1739 #define FC_FABRIC_ATTACHED 0x00001000
1740 #define FC_PT_TO_PT 0x00002000
1741 #define FC_BYPASSED_MODE 0x00004000
1742 #define FC_MENLO_MODE 0x00008000 /* Menlo maintenance mode */
1743
1744 #define FC_DUMP_SAFE 0x00010000 /* Safe to DUMP */
1745 #define FC_DUMP_ACTIVE 0x00020000 /* DUMP in progress */
1746 #define FC_NEW_FABRIC 0x00040000
1747
1748 #define FC_SLIM2_MODE 0x00100000 /* SLIM in host memory */
1749 #define FC_INTERLOCKED 0x00200000
1750 #define FC_HBQ_ENABLED 0x00400000
1751 #define FC_ASYNC_EVENTS 0x00800000
1752
1753 #define FC_ILB_MODE 0x01000000
1754 #define FC_ELB_MODE 0x02000000
1755 #define FC_LOOPBACK_MODE 0x03000000 /* Loopback Mode Mask */
1756 #define FC_DUMP 0x04000000 /* DUMP in progress */
1757 #define FC_SHUTDOWN 0x08000000 /* SHUTDOWN in progress */
1758
1759 #define FC_OVERTEMP_EVENT 0x10000000 /* FC_ERROR reason: */
1760 /* over temperature event */
1761 #define FC_MBOX_TIMEOUT 0x20000000 /* FC_ERROR reason: */
1762 /* mailbox timeout event */
1763 #define FC_DMA_CHECK_ERROR 0x40000000 /* Shared memory (slim,..) */
1764 /* DMA handle went bad */
1765 #define FC_HARDWARE_ERROR 0x80000000 /* FC_ERROR state triggered */
1766
1767 #define FC_RESET_MASK 0x00030C1F /* Bits to protect during */
1768 /* a hard reset */
1769 #define FC_LINKDOWN_MASK 0xFFF30C1F /* Bits to protect during */
1770 /* a linkdown */
1771
1772 uint32_t fw_timer;
1773 uint32_t fw_flag;
1774 #define FW_UPDATE_NEEDED 0x00000001
1775 #define FW_UPDATE_KERNEL 0x00000002
1776
1777 uint32_t temperature; /* Last reported temperature */
1778
1779 /* SBUS adapter management */
1780 caddr_t sbus_pci_addr; /* Virt addr of TITAN */
1781 /* pci config */
1782 ddi_acc_handle_t sbus_pci_handle;
1783
1784 /* PCI BUS adapter management */
1785 caddr_t pci_addr;
1786 ddi_acc_handle_t pci_acc_handle;
1787
1788 uint32_t sli_mode;
1789 #define EMLXS_HBA_SLI1_MODE 1
1790 #define EMLXS_HBA_SLI2_MODE 2
1791 #define EMLXS_HBA_SLI3_MODE 3
1792 #define EMLXS_HBA_SLI4_MODE 4
1793
1794 /* SLI private data */
1795 union {
1796 emlxs_sli3_t sli3;
1797 emlxs_sli4_t sli4;
1798 } sli;
1799
1800 /* SLI API entry point routines */
1801 emlxs_sli_api_t sli_api;
1802
1803 uint32_t io_poll_count; /* Number of poll commands */
1804 /* in progress */
1805
1806 /* IO Completion management */
1807 uint32_t iodone_count; /* Number of IO's on done Q */
1808 /* Protected by EMLXS_PORT_LOCK */
1809 emlxs_buf_t *iodone_list; /* fc_packet being deferred */
1810 emlxs_buf_t *iodone_tail; /* fc_packet being deferred */
1811 emlxs_thread_t iodone_thread;
1812 emlxs_thread_t *spawn_thread_head;
1813 emlxs_thread_t *spawn_thread_tail;
1814 kmutex_t spawn_lock;
1815 uint32_t spawn_open;
1816
1817 /* IO Channel management */
1818 int32_t chan_count;
1819 emlxs_channel_t chan[MAX_CHANNEL];
1820 kmutex_t channel_tx_lock;
1821 uint8_t channel_fcp; /* Default channel to use for FCP IO */
1822 #define CHANNEL_FCT channel_fcp
1823 uint8_t channel_ip; /* Default channel to use for IP IO */
1824 uint8_t channel_els; /* Default channel to use for ELS IO */
1825 uint8_t channel_ct; /* Default channel to use for CT IO */
1826
1827 /* IOTag management */
1828 emlxs_buf_t **fc_table; /* sc_buf pointers indexed by */
1829 /* iotag */
1830 uint16_t fc_iotag; /* used to identify I/Os */
1831 uint16_t fc_oor_iotag; /* OutOfRange (fc_table) iotags */
1832 /* typically used for Abort/close */
1833 #define EMLXS_MAX_ABORT_TAG 0x7fff
1834 uint16_t max_iotag; /* ALL IOCBs except aborts */
1835 kmutex_t iotag_lock;
1836 uint32_t io_count; /* No of IO holding */
1837 /* regular iotag */
1838 uint32_t channel_tx_count; /* No of IO on tx Q */
1839
1840 /* Mailbox Management */
1841 uint32_t mbox_queue_flag;
1842 emlxs_queue_t mbox_queue;
1843 void *mbox_mqe; /* active mbox mqe */
1844 void *mbox_mbq; /* active MAILBOXQ */
1845 kcondvar_t mbox_lock_cv; /* MBX_SLEEP */
1846 kmutex_t mbox_lock; /* MBX_SLEEP */
1847 uint32_t mbox_timer;
1848
1849 /* Interrupt management */
1850 void *intr_arg;
1851 uint32_t intr_unclaimed;
1852 uint32_t intr_autoClear;
1853 uint32_t intr_flags;
1854 #define EMLXS_INTX_INITED 0x0001
1855 #define EMLXS_INTX_ADDED 0x0002
1856 #define EMLXS_MSI_ENABLED 0x0010
1857 #define EMLXS_MSI_INITED 0x0020
1858 #define EMLXS_MSI_ADDED 0x0040
1859 #define EMLXS_INTR_INITED (EMLXS_INTX_INITED|EMLXS_MSI_INITED)
1860 #define EMLXS_INTR_ADDED (EMLXS_INTX_ADDED|EMLXS_MSI_ADDED)
1861
1862 #ifdef MSI_SUPPORT
1863 ddi_intr_handle_t *intr_htable;
1864 uint32_t *intr_pri;
1865 int32_t *intr_cap;
1866 uint32_t intr_count;
1867 uint32_t intr_type;
1868 uint32_t intr_cond;
1869 uint32_t intr_map[EMLXS_MSI_MAX_INTRS];
1870 uint32_t intr_mask;
1871
1872 kmutex_t msiid_lock; /* for last_msiid */
1873 int last_msiid;
1874
1875 kmutex_t intr_lock[EMLXS_MSI_MAX_INTRS];
1876 int chan2msi[MAX_CHANNEL];
1877 /* Index is the channel id */
1878 int msi2chan[EMLXS_MSI_MAX_INTRS];
1879 /* Index is the MSX-X msg id */
1880 #endif /* MSI_SUPPORT */
1881
1882 uint32_t heartbeat_timer;
1883 uint32_t heartbeat_flag;
1884 uint32_t heartbeat_active;
1885
1886 /* IOCTL management */
1887 kmutex_t ioctl_lock;
1888 uint32_t ioctl_flags;
1889 #define EMLXS_OPEN 0x00000001
1890 #define EMLXS_OPEN_EXCLUSIVE 0x00000002
1891
1892 /* Timer management */
1893 kcondvar_t timer_lock_cv;
1894 kmutex_t timer_lock;
1895 timeout_id_t timer_id;
1896 uint32_t timer_tics;
1897 uint32_t timer_flags;
1898 #define EMLXS_TIMER_STARTED 0x0000001
1899 #define EMLXS_TIMER_BUSY 0x0000002
1900 #define EMLXS_TIMER_KILL 0x0000004
1901 #define EMLXS_TIMER_ENDED 0x0000008
1902
1903 /* Misc Timers */
1904 uint32_t linkup_timer;
1905 uint32_t discovery_timer;
1906 uint32_t pkt_timer;
1907
1908 /* Power Management */
1909 uint32_t pm_state;
1910 /* pm_state */
1911 #define EMLXS_PM_IN_ATTACH 0x00000001
1912 #define EMLXS_PM_IN_DETACH 0x00000002
1913 #define EMLXS_PM_IN_SOL_CB 0x00000010
1914 #define EMLXS_PM_IN_UNSOL_CB 0x00000020
1915 #define EMLXS_PM_IN_LINK_RESET 0x00000100
1916 #define EMLXS_PM_IN_HARD_RESET 0x00000200
1917 #define EMLXS_PM_SUSPENDED 0x01000000
1918
1919 uint32_t pm_level;
1920 /* pm_level */
1921 #define EMLXS_PM_ADAPTER_DOWN 0
1922 #define EMLXS_PM_ADAPTER_UP 1
1923
1924 uint32_t pm_busy;
1925 kmutex_t pm_lock;
1926 uint8_t pm_config[PCI_CONFIG_SIZE];
1927 #ifdef IDLE_TIMER
1928 uint32_t pm_idle_timer;
1929 uint32_t pm_active; /* Only used by timer */
1930 #endif /* IDLE_TIMER */
1931
1932 /* Loopback management */
1933 uint32_t loopback_tics;
1934 void *loopback_pkt;
1935
1936 /* Event management */
1937 emlxs_event_queue_t event_queue;
1938 uint32_t event_mask;
1939 uint32_t event_timer;
1940 emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS];
1941 emlxs_hba_event_t hba_event;
1942
1943 /* Parameter management */
1944 emlxs_config_t config[NUM_CFG_PARAM];
1945
1946 /* Driver stat management */
1947 kstat_t *kstat;
1948 emlxs_stats_t stats;
1949
1950 /* Log management */
1951 emlxs_msg_log_t log;
1952
1953 /* Port managment */
1954 uint32_t vpi_base;
1955 uint32_t vpi_max;
1956 uint32_t vpi_high;
1957 uint32_t num_of_ports;
1958
1959 kmutex_t port_lock; /* locks port, nodes, rings */
1960 emlxs_port_t port[MAX_VPORTS + 1]; /* port specific info */
1961 /* Last one is for */
1962 /* NPIV ready test */
1963
1964 #ifdef DHCHAP_SUPPORT
1965 kmutex_t dhc_lock;
1966 kmutex_t auth_lock;
1967 emlxs_auth_cfg_t auth_cfg; /* Default auth_cfg. */
1968 /* Points to list of entries. */
1969 /* Protected by auth_lock */
1970 uint32_t auth_cfg_count;
1971 emlxs_auth_key_t auth_key; /* Default auth_key. */
1972 /* Points to list of entries. */
1973 /* Protected by auth_lock */
1974 uint32_t auth_key_count;
1975 uint32_t rdn_flag;
1976 #endif /* DHCHAP_SUPPORT */
1977
1978 uint16_t ini_mode;
1979 uint16_t tgt_mode;
1980
1981 #ifdef TEST_SUPPORT
1982 uint32_t underrun_counter;
1983 #endif /* TEST_SUPPORT */
1984
1985 #ifdef MODFW_SUPPORT
1986 ddi_modhandle_t fw_modhandle;
1987 #endif /* MODFW_SUPPORT */
1988
1989 #ifdef DUMP_SUPPORT
1990 emlxs_file_t dump_txtfile;
1991 emlxs_file_t dump_dmpfile;
1992 emlxs_file_t dump_ceefile;
1993 kmutex_t dump_lock;
1994 #define EMLXS_DUMP_LOCK hba->dump_lock
1995 #define EMLXS_TXT_FILE 1
1996 #define EMLXS_DMP_FILE 2
1997 #define EMLXS_CEE_FILE 3
1998
1999 #define EMLXS_DRV_DUMP 0
2000 #define EMLXS_TEMP_DUMP 1
2001 #define EMLXS_USER_DUMP 2
2002
2003 #endif /* DUMP_SUPPORT */
2004
2005 } emlxs_hba_t;
2006
2007 #define EMLXS_SLI_MAP_HDW (hba->sli_api.sli_map_hdw)
2008 #define EMLXS_SLI_UNMAP_HDW (hba->sli_api.sli_unmap_hdw)
2009 #define EMLXS_SLI_ONLINE (hba->sli_api.sli_online)
2010 #define EMLXS_SLI_OFFLINE (hba->sli_api.sli_offline)
2011 #define EMLXS_SLI_HBA_RESET (hba->sli_api.sli_hba_reset)
2012 #define EMLXS_SLI_HBA_KILL (hba->sli_api.sli_hba_kill)
2013 #define EMLXS_SLI_ISSUE_IOCB_CMD (hba->sli_api.sli_issue_iocb_cmd)
2014 #define EMLXS_SLI_ISSUE_MBOX_CMD (hba->sli_api.sli_issue_mbox_cmd)
2015 #define EMLXS_SLI_PREP_FCT_IOCB (hba->sli_api.sli_prep_fct_iocb)
2016 #define EMLXS_SLI_PREP_FCP_IOCB (hba->sli_api.sli_prep_fcp_iocb)
2017 #define EMLXS_SLI_PREP_IP_IOCB (hba->sli_api.sli_prep_ip_iocb)
2018 #define EMLXS_SLI_PREP_ELS_IOCB (hba->sli_api.sli_prep_els_iocb)
2019 #define EMLXS_SLI_PREP_CT_IOCB (hba->sli_api.sli_prep_ct_iocb)
2020 #define EMLXS_SLI_POLL_INTR (hba->sli_api.sli_poll_intr)
2021 #define EMLXS_SLI_INTX_INTR (hba->sli_api.sli_intx_intr)
2022 #define EMLXS_SLI_MSI_INTR (hba->sli_api.sli_msi_intr)
2023 #define EMLXS_SLI_DISABLE_INTR (hba->sli_api.sli_disable_intr)
2024 #define EMLXS_SLI_TIMER (hba->sli_api.sli_timer)
2025 #define EMLXS_SLI_POLL_ERRATT (hba->sli_api.sli_poll_erratt)
2026
2027 #define EMLXS_HBA_T 1 /* flag emlxs_hba_t is already typedefed */
2028
2029 #ifdef MSI_SUPPORT
2030 #define EMLXS_INTR_INIT(_hba, _m) emlxs_msi_init(_hba, _m)
2031 #define EMLXS_INTR_UNINIT(_hba) emlxs_msi_uninit(_hba)
2032 #define EMLXS_INTR_ADD(_hba) emlxs_msi_add(_hba)
2033 #define EMLXS_INTR_REMOVE(_hba) emlxs_msi_remove(_hba)
2034 #else
2035 #define EMLXS_INTR_INIT(_hba, _m) emlxs_intx_init(_hba, _m)
2036 #define EMLXS_INTR_UNINIT(_hba) emlxs_intx_uninit(_hba)
2037 #define EMLXS_INTR_ADD(_hba) emlxs_intx_add(_hba)
2038 #define EMLXS_INTR_REMOVE(_hba) emlxs_intx_remove(_hba)
2039 #endif /* MSI_SUPPORT */
2040
2041
2042 /* Power Management Component */
2043 #define EMLXS_PM_ADAPTER 0
2044
2045
2046 #define DRV_TIME (uint32_t)((gethrtime() - emlxs_device.drv_timestamp) / NANOSEC)
2047
2048 #define HBA port->hba
2049 #define PPORT hba->port[0]
2050 #define VPORT(x) hba->port[x]
2051 #define EMLXS_TIMER_LOCK hba->timer_lock
2052 #define VPD hba->vpd
2053 #define CFG hba->config[0]
2054 #define LOG hba->log
2055 #define EVENTQ hba->event_queue
2056 #define EMLXS_MBOX_LOCK hba->mbox_lock
2057 #define EMLXS_MBOX_CV hba->mbox_lock_cv
2058 #define EMLXS_LINKUP_LOCK hba->linkup_lock
2059 #define EMLXS_LINKUP_CV hba->linkup_lock_cv
2060 #define EMLXS_TX_CHANNEL_LOCK hba->channel_tx_lock /* ring txq lock */
2061 #define EMLXS_MEMGET_LOCK hba->memget_lock /* mempool get lock */
2062 #define EMLXS_MEMPUT_LOCK hba->memput_lock /* mempool put lock */
2063 #define EMLXS_IOCTL_LOCK hba->ioctl_lock /* ioctl lock */
2064 #define EMLXS_SPAWN_LOCK hba->spawn_lock /* spawn lock */
2065 #define EMLXS_PM_LOCK hba->pm_lock /* pm lock */
2066 #define HBASTATS hba->stats
2067 #define EMLXS_CMD_RING_LOCK(n) hba->sli.sli3.ring_cmd_lock[n]
2068
2069 #define EMLXS_QUE_LOCK(n) hba->sli.sli4.que_lock[n]
2070 #define EMLXS_MSIID_LOCK hba->msiid_lock
2071
2072 #define EMLXS_FCTAB_LOCK hba->iotag_lock
2073
2074 #define EMLXS_FCF_LOCK hba->sli.sli4.fcf_lock
2075
2076 #define EMLXS_PORT_LOCK hba->port_lock /* locks ports, */
2077 /* nodes, rings */
2078 #define EMLXS_INTR_LOCK(_id) hba->intr_lock[_id] /* locks intr threads */
2079
2080 #define EMLXS_PKT_LOCK port->pkt_lock /* used for pkt */
2081 /* polling */
2082 #define EMLXS_PKT_CV port->pkt_lock_cv /* Used for pkt */
2083 /* polling */
2084 #define EMLXS_UB_LOCK port->ub_lock /* locks unsolicited */
2085 /* buffer pool */
2086
2087 /* These SWAPs will swap on any platform */
2088 #define SWAP32_BUFFER(_b, _c) emlxs_swap32_buffer(_b, _c)
2089 #define SWAP32_BCOPY(_s, _d, _c) emlxs_swap32_bcopy(_s, _d, _c)
2090
2091 #define SWAP64(_x) ((((uint64_t)(_x) & 0xFF)<<56) | \
2092 (((uint64_t)(_x) & 0xFF00)<<40) | \
2093 (((uint64_t)(_x) & 0xFF0000)<<24) | \
2094 (((uint64_t)(_x) & 0xFF000000)<<8) | \
2095 (((uint64_t)(_x) & 0xFF00000000)>>8) | \
2096 (((uint64_t)(_x) & 0xFF0000000000)>>24) | \
2097 (((uint64_t)(_x) & 0xFF000000000000)>>40) | \
2098 (((uint64_t)(_x) & 0xFF00000000000000)>>56))
2099
2100 #define SWAP32(_x) ((((uint32_t)(_x) & 0xFF)<<24) | \
2101 (((uint32_t)(_x) & 0xFF00)<<8) | \
2102 (((uint32_t)(_x) & 0xFF0000)>>8) | \
2103 (((uint32_t)(_x) & 0xFF000000)>>24))
2104
2105 #define SWAP16(_x) ((((uint16_t)(_x) & 0xFF)<<8) | \
2106 (((uint16_t)(_x) & 0xFF00)>>8))
2107
2108 #define SWAP24_LO(_x) ((((uint32_t)(_x) & 0xFF)<<16) | \
2109 ((uint32_t)(_x) & 0xFF00FF00) | \
2110 (((uint32_t)(_x) & 0x00FF0000)>>16))
2111
2112 #define SWAP24_HI(_x) (((uint32_t)(_x) & 0x00FF00FF) | \
2113 (((uint32_t)(_x) & 0x0000FF00)<<16) | \
2114 (((uint32_t)(_x) & 0xFF000000)>>16))
2115
2116 /* These LE_SWAPs will only swap on a LE platform */
2117 #ifdef EMLXS_LITTLE_ENDIAN
2118 #define LE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c)
2119 #define LE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c)
2120 #define LE_SWAP64(_x) SWAP64(_x)
2121 #define LE_SWAP32(_x) SWAP32(_x)
2122 #define LE_SWAP16(_x) SWAP16(_x)
2123 #define LE_SWAP24_LO(_x) SWAP24_LO(X)
2124 #define LE_SWAP24_HI(_x) SWAP24_HI(X)
2125
2126 #if (EMLXS_MODREVX == EMLXS_MODREV2X)
2127 #undef LE_SWAP24_LO
2128 #define LE_SWAP24_LO(_x) (_x)
2129 #undef LE_SWAP24_HI
2130 #define LE_SWAP24_HI(_x) (_x)
2131 #endif /* EMLXS_MODREV2X */
2132
2133 #else /* BIG ENDIAN */
2134 #define LE_SWAP32_BUFFER(_b, _c)
2135 #define LE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c)
2136 #define LE_SWAP64(_x) (_x)
2137 #define LE_SWAP32(_x) (_x)
2138 #define LE_SWAP16(_x) (_x)
2139 #define LE_SWAP24_LO(_x) (_x)
2140 #define LE_SWAP24_HI(_x) (_x)
2141 #endif /* EMLXS_LITTLE_ENDIAN */
2142
2143 /* These BE_SWAPs will only swap on a BE platform */
2144 #ifdef EMLXS_BIG_ENDIAN
2145 #define BE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c)
2146 #define BE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c)
2147 #define BE_SWAP64(_x) SWAP64(_x)
2148 #define BE_SWAP32(_x) SWAP32(_x)
2149 #define BE_SWAP16(_x) SWAP16(_x)
2150 #else /* LITTLE ENDIAN */
2151 #define BE_SWAP32_BUFFER(_b, _c)
2152 #define BE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c)
2153 #define BE_SWAP64(_x) (_x)
2154 #define BE_SWAP32(_x) (_x)
2155 #define BE_SWAP16(_x) (_x)
2156 #endif /* EMLXS_BIG_ENDIAN */
2157
2158 #ifdef __cplusplus
2159 }
2160 #endif
2161
2162 #endif /* _EMLXS_FC_H */