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4786 emlxs shouldn't abuse ddi_get_time(9f)
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--- old/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2010 Emulex. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 +/*
27 + * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
28 + */
26 29
27 30 #ifndef _EMLXS_FC_H
28 31 #define _EMLXS_FC_H
29 32
30 33 #ifdef __cplusplus
31 34 extern "C" {
32 35 #endif
33 36
34 37 typedef struct emlxs_buf
35 38 {
36 39 fc_packet_t *pkt; /* scsi_pkt reference */
37 40 struct emlxs_port *port; /* pointer to port */
38 41 void *bmp; /* Save the buffer pointer */
39 42 /* list for later use. */
40 43 struct emlxs_buf *fc_fwd; /* Use it by chip_Q */
41 44 struct emlxs_buf *fc_bkwd; /* Use it by chip_Q */
42 45 struct emlxs_buf *next; /* Use it when the iodone */
43 46 struct emlxs_node *node;
44 47 void *channel; /* Save channel and used by */
45 48 /* abort */
46 49 struct emlxs_buf *fpkt; /* Flush pkt pointer */
47 50 struct XRIobj *xrip; /* Exchange resource */
48 51 IOCBQ iocbq;
49 52 kmutex_t mtx;
50 53 uint32_t pkt_flags;
51 54 uint32_t iotag; /* iotag for this cmd */
52 55 uint32_t ticks; /* save the timeout ticks */
53 56 /* for the fc_packet_t */
54 57 uint32_t abort_attempts;
55 58 uint32_t lun;
56 59 #define EMLXS_LUN_NONE 0xFFFFFFFF
57 60
58 61 uint32_t class; /* Save class and used by */
59 62 /* abort */
60 63 uint32_t ucmd; /* Unsolicted command that */
61 64 /* this packet is responding */
62 65 /* to, if any */
63 66 int32_t flush_count; /* Valid only in flush pkts */
64 67 uint32_t did;
65 68
66 69 #ifdef SFCT_SUPPORT
67 70 kmutex_t fct_mtx;
68 71 fc_packet_t *fct_pkt;
69 72 fct_cmd_t *fct_cmd;
70 73
71 74 uint8_t fct_type;
72 75
73 76 #define EMLXS_FCT_ELS_CMD 0x01 /* Unsolicted */
74 77 #define EMLXS_FCT_ELS_REQ 0x02 /* Solicited */
75 78 #define EMLXS_FCT_ELS_RSP 0x04
76 79 #define EMLXS_FCT_CT_REQ 0x08 /* Solicited */
77 80 #define EMLXS_FCT_FCP_CMD 0x10 /* Unsolicted */
78 81 #define EMLXS_FCT_FCP_DATA 0x20
79 82 #define EMLXS_FCT_FCP_STATUS 0x40
80 83
81 84
82 85 uint8_t fct_flags;
83 86
84 87 #define EMLXS_FCT_SEND_STATUS 0x01
85 88 #define EMLXS_FCT_ABORT_INP 0x02
86 89 #define EMLXS_FCT_IO_INP 0x04
87 90 #define EMLXS_FCT_PLOGI_RECEIVED 0x10
88 91 #define EMLXS_FCT_REGISTERED 0x20
89 92
90 93 uint16_t fct_state;
91 94
92 95 #define EMLXS_FCT_FCP_CMD_RECEIVED 1
93 96 #define EMLXS_FCT_ELS_CMD_RECEIVED 2
94 97 #define EMLXS_FCT_CMD_POSTED 3
95 98 #define EMLXS_FCT_CMD_WAITQ 4
96 99 #define EMLXS_FCT_SEND_CMD_RSP 5
97 100 #define EMLXS_FCT_SEND_ELS_RSP 6
98 101 #define EMLXS_FCT_SEND_ELS_REQ 7
99 102 #define EMLXS_FCT_SEND_CT_REQ 8
100 103 #define EMLXS_FCT_RSP_PENDING 9
101 104 #define EMLXS_FCT_REQ_PENDING 10
102 105 #define EMLXS_FCT_REG_PENDING 11
103 106 #define EMLXS_FCT_REG_COMPLETE 12
104 107 #define EMLXS_FCT_OWNED 13
105 108 #define EMLXS_FCT_SEND_FCP_DATA 14
106 109 #define EMLXS_FCT_SEND_FCP_STATUS 15
107 110 #define EMLXS_FCT_DATA_PENDING 16
108 111 #define EMLXS_FCT_STATUS_PENDING 17
109 112 #define EMLXS_FCT_PKT_COMPLETE 18
110 113 #define EMLXS_FCT_PKT_FCPRSP_COMPLETE 19
111 114 #define EMLXS_FCT_PKT_ELSRSP_COMPLETE 20
112 115 #define EMLXS_FCT_PKT_ELSCMD_COMPLETE 21
113 116 #define EMLXS_FCT_PKT_CTCMD_COMPLETE 22
114 117 #define EMLXS_FCT_REQ_COMPLETE 23
115 118 #define EMLXS_FCT_CLOSE_PENDING 24
116 119 #define EMLXS_FCT_ABORT_PENDING 25
117 120 #define EMLXS_FCT_ABORT_DONE 26
118 121 #define EMLXS_FCT_IO_DONE 27
119 122
120 123 #define EMLXS_FCT_IOCB_ISSUED 256 /* For tracing only */
121 124 #define EMLXS_FCT_IOCB_COMPLETE 257 /* For tracing only */
122 125
123 126 stmf_data_buf_t *fct_buf;
124 127
125 128 #endif /* SFCT_SUPPORT */
126 129
127 130 #ifdef SAN_DIAG_SUPPORT
128 131 hrtime_t sd_start_time;
129 132 #endif
130 133 } emlxs_buf_t;
131 134
132 135
133 136
134 137 #ifdef FCT_IO_TRACE
135 138 #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \
136 139 (_cmd_sbp)->fct_state = _state; \
137 140 emlxs_fct_io_trace((_cmd_sbp)->port, _fct_cmd, _state)
138 141 #else
139 142 /* define to set fct_state */
140 143 #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \
141 144 (_cmd_sbp)->fct_state = _state
142 145 #endif /* FCT_IO_TRACE */
143 146
144 147
145 148 /* pkt_flags */
146 149 #define PACKET_IN_COMPLETION 0x00000001
147 150 #define PACKET_IN_TXQ 0x00000002
148 151 #define PACKET_IN_CHIPQ 0x00000004
149 152 #define PACKET_IN_DONEQ 0x00000008
150 153
151 154 #define PACKET_FCP_RESET 0x00000030
152 155 #define PACKET_FCP_TGT_RESET 0x00000010
153 156 #define PACKET_FCP_LUN_RESET 0x00000020
154 157 #define PACKET_POLLED 0x00000040
155 158
156 159 #ifdef EMLXS_I386
157 160 #define PACKET_FCP_SWAPPED 0x00000100
158 161 #define PACKET_ELS_SWAPPED 0x00000200
159 162 #define PACKET_CT_SWAPPED 0x00000400
160 163 #define PACKET_CSP_SWAPPED 0x00000800
161 164 #endif /* EMLXS_I386 */
162 165
163 166 #define PACKET_STALE 0x00001000
164 167
165 168 #define PACKET_IN_TIMEOUT 0x00010000
166 169 #define PACKET_IN_FLUSH 0x00020000
167 170 #define PACKET_IN_ABORT 0x00040000
168 171 #define PACKET_XRI_CLOSED 0x00080000 /* An XRI abort/close was issued */
169 172
170 173 #define PACKET_CHIP_COMP 0x00100000
171 174 #define PACKET_COMPLETED 0x00200000
172 175 #define PACKET_ULP_OWNED 0x00400000
173 176
174 177 #define PACKET_STATE_VALID 0x01000000
175 178 #define PACKET_FCP_RSP_VALID 0x02000000
176 179 #define PACKET_ELS_RSP_VALID 0x04000000
177 180 #define PACKET_CT_RSP_VALID 0x08000000
178 181
179 182 #define PACKET_DELAY_REQUIRED 0x10000000
180 183 #define PACKET_ALLOCATED 0x40000000
181 184 #define PACKET_VALID 0x80000000
182 185
183 186
184 187 #define STALE_PACKET ((emlxs_buf_t *)0xFFFFFFFF)
185 188
186 189
187 190 /*
188 191 * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
189 192 * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
190 193 *
191 194 * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
192 195 * Each FCA defines its own set with values greater >= 0x7F
193 196 */
194 197 #define FC_REASON_FCA_DEFINED 0x100
195 198
196 199
197 200 /*
198 201 * Device VPD save area
199 202 */
200 203
201 204 typedef struct emlxs_vpd
202 205 {
203 206 uint32_t biuRev;
204 207 uint32_t smRev;
205 208 uint32_t smFwRev;
206 209 uint32_t endecRev;
207 210 uint16_t rBit;
208 211 uint8_t fcphHigh;
209 212 uint8_t fcphLow;
210 213 uint8_t feaLevelHigh;
211 214 uint8_t feaLevelLow;
212 215
213 216 uint32_t postKernRev;
214 217 char postKernName[32];
215 218
216 219 uint32_t opFwRev;
217 220 char opFwName[32];
218 221 char opFwLabel[32];
219 222
220 223 uint32_t sli1FwRev;
221 224 char sli1FwName[32];
222 225 char sli1FwLabel[32];
223 226
224 227 uint32_t sli2FwRev;
225 228 char sli2FwName[32];
226 229 char sli2FwLabel[32];
227 230
228 231 uint32_t sli3FwRev;
229 232 char sli3FwName[32];
230 233 char sli3FwLabel[32];
231 234
232 235 uint32_t sli4FwRev;
233 236 char sli4FwName[32];
234 237 char sli4FwLabel[32];
235 238
236 239 char fw_version[32];
237 240 char fw_label[32];
238 241
239 242 char fcode_version[32];
240 243 char boot_version[32];
241 244
242 245 char serial_num[32];
243 246 char part_num[32];
244 247 char port_num[20];
245 248 char eng_change[32];
246 249 char manufacturer[80];
247 250 char model[80];
248 251 char model_desc[256];
249 252 char prog_types[256];
250 253 char id[80];
251 254
252 255 uint32_t port_index;
253 256 uint16_t link_speed;
254 257 } emlxs_vpd_t;
255 258
256 259
257 260 typedef struct emlxs_queue
258 261 {
259 262 void *q_first; /* queue first element */
260 263 void *q_last; /* queue last element */
261 264 uint16_t q_cnt; /* current length of queue */
262 265 uint16_t q_max; /* max length queue can get */
263 266 } emlxs_queue_t;
264 267 typedef emlxs_queue_t Q;
265 268
266 269
267 270
268 271 /*
269 272 * This structure is used when allocating a buffer pool.
270 273 * Note: this should be identical to gasket buf_info (fldl.h).
271 274 */
272 275 typedef struct emlxs_buf_info
273 276 {
274 277 int32_t size; /* Specifies the number of bytes to allocate. */
275 278 int32_t align; /* The desired address boundary. */
276 279
277 280 int32_t flags;
278 281
279 282 #define FC_MBUF_DMA 0x01 /* blocks are for DMA */
280 283 #define FC_MBUF_PHYSONLY 0x02 /* For malloc - map a given virtual */
281 284 /* address to physical address (skip */
282 285 /* the malloc). */
283 286 /* For free - just unmap the given */
284 287 /* physical address (skip the free). */
285 288 #define FC_MBUF_IOCTL 0x04 /* called from dfc_ioctl */
286 289 #define FC_MBUF_UNLOCK 0x08 /* called with driver unlocked */
287 290 #define FC_MBUF_SNGLSG 0x10 /* allocate a single contiguous */
288 291 /* physical memory */
289 292 #define FC_MBUF_DMA32 0x20
290 293
291 294 uint64_t phys; /* specifies physical buffer pointer */
292 295 void *virt; /* specifies virtual buffer pointer */
293 296 void *data_handle;
294 297 void *dma_handle;
295 298 } emlxs_buf_info_t;
296 299 typedef emlxs_buf_info_t MBUF_INFO;
297 300
298 301
299 302 #define EMLXS_MAX_HBQ 16 /* Max HBQs handled by firmware */
300 303 #define EMLXS_ELS_HBQ_ID 0
301 304 #define EMLXS_IP_HBQ_ID 1
302 305 #define EMLXS_CT_HBQ_ID 2
303 306 #define EMLXS_FCT_HBQ_ID 3
304 307
305 308 #ifdef SFCT_SUPPORT
306 309 #define EMLXS_NUM_HBQ 4 /* Number of HBQs supported by driver */
307 310 #else
308 311 #define EMLXS_NUM_HBQ 3 /* Number of HBQs supported by driver */
309 312 #endif /* SFCT_SUPPORT */
310 313
311 314
312 315 /*
313 316 * An IO Channel is a object that comprises a xmit/cmpl
314 317 * path for IOs.
315 318 * For SLI3, an IO path maps to a ring (cmd/rsp)
316 319 * For SLI4, an IO path map to a queue pair (WQ/CQ)
317 320 */
318 321 typedef struct emlxs_channel
319 322 {
320 323 struct emlxs_hba *hba; /* ptr to hba for channel */
321 324 void *iopath; /* ptr to SLI3/4 io path */
322 325
323 326 kmutex_t rsp_lock;
324 327 IOCBQ *rsp_head; /* deferred completion head */
325 328 IOCBQ *rsp_tail; /* deferred completion tail */
326 329 emlxs_thread_t intr_thread;
327 330
328 331
329 332 uint16_t channelno;
330 333 uint16_t chan_flag;
331 334
332 335 #define EMLXS_NEEDS_TRIGGER 1
333 336
334 337 /* Protected by EMLXS_TX_CHANNEL_LOCK */
335 338 emlxs_queue_t nodeq; /* Node service queue */
336 339
337 340 kmutex_t channel_cmd_lock;
338 341 uint32_t timeout;
339 342
340 343 /* Channel command counters */
341 344 uint32_t ulpSendCmd;
342 345 uint32_t ulpCmplCmd;
343 346 uint32_t hbaSendCmd;
344 347 uint32_t hbaCmplCmd;
345 348 uint32_t hbaSendCmd_sbp;
346 349 uint32_t hbaCmplCmd_sbp;
347 350
348 351 } emlxs_channel_t;
349 352 typedef emlxs_channel_t CHANNEL;
350 353
351 354 /*
352 355 * Should be able to handle max number of io paths for a
353 356 * SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS)
354 357 */
355 358 #define MAX_CHANNEL EMLXS_MSI_MAX_INTRS
356 359
357 360
358 361 /* Structure used to access adapter rings */
359 362 typedef struct emlxs_ring
360 363 {
361 364 void *fc_cmdringaddr; /* virtual offset for cmd */
362 365 /* rings */
363 366 void *fc_rspringaddr; /* virtual offset for rsp */
364 367 /* rings */
365 368
366 369 void *fc_mpon; /* index ptr for match */
367 370 /* structure */
368 371 void *fc_mpoff; /* index ptr for match */
369 372 /* structure */
370 373 struct emlxs_hba *hba; /* ptr to hba for ring */
371 374
372 375 uint8_t fc_numCiocb; /* number of command iocb's */
373 376 /* per ring */
374 377 uint8_t fc_numRiocb; /* number of response iocb's */
375 378 /* per ring */
376 379 uint8_t fc_rspidx; /* current index in response */
377 380 /* ring */
378 381 uint8_t fc_cmdidx; /* current index in command */
379 382 /* ring */
380 383 uint8_t fc_port_rspidx;
381 384 uint8_t fc_port_cmdidx;
382 385 uint8_t ringno;
383 386
384 387 uint16_t fc_missbufcnt; /* buf cnt we need to repost */
385 388 CHANNEL *channelp;
386 389
387 390
388 391 } emlxs_ring_t;
389 392 typedef emlxs_ring_t RING;
390 393
391 394
392 395 #ifdef SAN_DIAG_SUPPORT
393 396 /*
394 397 * Although right now it's just 1 field, SAN Diag anticipates that this
395 398 * structure will grow in the future.
396 399 */
397 400 typedef struct sd_timestat_level0 {
398 401 int count;
399 402 } sd_timestat_level0_t;
400 403 #endif
401 404
402 405 typedef struct emlxs_node
403 406 {
404 407 struct emlxs_node *nlp_list_next;
405 408 struct emlxs_node *nlp_list_prev;
406 409
407 410 NAME_TYPE nlp_portname; /* port name */
408 411 NAME_TYPE nlp_nodename; /* node name */
409 412
410 413 uint32_t nlp_DID; /* fibre channel D_ID */
411 414 uint32_t nlp_oldDID;
412 415
413 416 uint16_t nlp_Rpi; /* login id returned by */
414 417 /* REG_LOGIN */
415 418 uint16_t nlp_Xri; /* login id returned by */
416 419 /* REG_LOGIN */
417 420
418 421 uint8_t nlp_fcp_info; /* Remote class info */
419 422
420 423 /* nlp_fcp_info */
421 424 #define NLP_FCP_TGT_DEVICE 0x10 /* FCP TGT device */
422 425 #define NLP_FCP_INI_DEVICE 0x20 /* FCP Initiator device */
423 426 #define NLP_FCP_2_DEVICE 0x40 /* FCP-2 TGT device */
424 427 #define NLP_EMLX_VPORT 0x80 /* Virtual port */
425 428
426 429 uint32_t nlp_force_rscn;
427 430 uint32_t nlp_tag; /* Tag used by port_offline */
428 431 uint32_t flag;
429 432
430 433 #define NODE_POOL_ALLOCATED 0x00000001
431 434
432 435 SERV_PARM sparm;
433 436
434 437 /* Protected by EMLXS_TX_CHANNEL_LOCK */
435 438 uint32_t nlp_active; /* Node active flag */
436 439 uint32_t nlp_base;
437 440 uint32_t nlp_flag[MAX_CHANNEL]; /* Node level channel */
438 441 /* flags */
439 442
440 443 /* nlp_flag */
441 444 #define NLP_CLOSED 0x1
442 445 #define NLP_OFFLINE 0x2
443 446 #define NLP_RPI_XRI 0x4
444 447
445 448 uint32_t nlp_tics[MAX_CHANNEL]; /* gate timeout */
446 449 emlxs_queue_t nlp_tx[MAX_CHANNEL]; /* Transmit Q head */
447 450 emlxs_queue_t nlp_ptx[MAX_CHANNEL]; /* Priority transmit */
448 451 /* Queue head */
449 452 void *nlp_next[MAX_CHANNEL]; /* Service Request */
450 453 /* Queue pointer used */
451 454 /* when node needs */
452 455 /* servicing */
453 456 #ifdef DHCHAP_SUPPORT
454 457 emlxs_node_dhc_t node_dhc;
455 458 #endif /* DHCHAP_SUPPORT */
456 459
457 460 #ifdef SAN_DIAG_SUPPORT
458 461 sd_timestat_level0_t sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS];
459 462 #endif
460 463
461 464 struct RPIobj *rpip; /* SLI4 only */
462 465 #define EMLXS_NODE_TO_RPI(_p, _n) \
463 466 ((_n)?((_n->rpip)?_n->rpip:emlxs_rpi_find(_p, _n->nlp_Rpi)):NULL)
464 467
465 468 } emlxs_node_t;
466 469 typedef emlxs_node_t NODELIST;
467 470
468 471
469 472
470 473 #define NADDR_LEN 6 /* MAC network address length */
471 474 typedef struct emlxs_fcip_nethdr
472 475 {
473 476 NAME_TYPE fc_destname; /* destination port name */
474 477 NAME_TYPE fc_srcname; /* source port name */
475 478 } emlxs_fcip_nethdr_t;
476 479 typedef emlxs_fcip_nethdr_t NETHDR;
477 480
478 481
479 482 #define MEM_NLP 0 /* memory segment to hold node list entries */
480 483 #define MEM_IOCB 1 /* memory segment to hold iocb commands */
481 484 #define MEM_MBOX 2 /* memory segment to hold mailbox cmds */
482 485 #define MEM_BPL 3 /* and to hold buffer ptr lists - SLI2 */
483 486 #define MEM_BUF 4 /* memory segment to hold buffer data */
484 487 #define MEM_ELSBUF 4 /* memory segment to hold buffer data */
485 488 #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */
486 489 #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */
487 490 #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */
488 491
489 492 #ifdef SFCT_SUPPORT
490 493 #define FC_MAX_SEG 8
491 494 #else
492 495 #define FC_MAX_SEG 7
493 496 #endif /* SFCT_SUPPORT */
494 497
495 498
496 499 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
497 500 #define BPL_TO_SGLLEN(_bpl) ((_bpl/12)-2)
498 501 #define MEM_BPL_SIZE 1024 /* Default size */
499 502
500 503 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
501 504 #define SGL_TO_SGLLEN(_sgl) ((_sgl/16)-2)
502 505 #define MEM_SGL_SIZE 4096 /* Default size */
503 506
504 507 #ifdef EMLXS_I386
505 508 #define EMLXS_SGLLEN BPL_TO_SGLLEN(MEM_BPL_SIZE)
506 509 #else /* EMLXS_SPARC */
507 510 #define EMLXS_SGLLEN 1
508 511 #endif /* EMLXS_I386 */
509 512
510 513 #define MEM_BUF_SIZE 1024
511 514 #define MEM_BUF_COUNT 64
512 515
513 516 #define MEM_ELSBUF_SIZE MEM_BUF_SIZE
514 517 #define MEM_ELSBUF_COUNT hba->max_nodes
515 518 #define MEM_IPBUF_SIZE 65535
516 519 #define MEM_IPBUF_COUNT 60
517 520 #define MEM_CTBUF_SIZE MAX_CT_PAYLOAD /* (1024*320) */
518 521 #define MEM_CTBUF_COUNT 8
519 522 #define MEM_FCTBUF_SIZE 65535
520 523 #define MEM_FCTBUF_COUNT 128
521 524
522 525 typedef struct emlxs_memseg
523 526 {
524 527 void *fc_memget_ptr;
525 528 void *fc_memget_end;
526 529 void *fc_memput_ptr;
527 530 void *fc_memput_end;
528 531
529 532 void *fc_memstart_virt; /* beginning address */
530 533 /* of memory block */
531 534 uint64_t fc_memstart_phys; /* beginning address */
532 535 /* of memory block */
533 536 ddi_dma_handle_t fc_mem_dma_handle;
534 537 ddi_acc_handle_t fc_mem_dat_handle;
535 538 uint32_t fc_total_memsize;
536 539 uint32_t fc_memsize; /* size of mem blks */
537 540 uint32_t fc_numblks; /* no of mem blks */
538 541 uint32_t fc_memget_cnt; /* no of mem get blks */
539 542 uint32_t fc_memput_cnt; /* no of mem put blks */
540 543 uint32_t fc_memflag; /* emlxs_buf_info_t FLAGS */
541 544 uint32_t fc_reserved; /* used with priority flag */
542 545 uint32_t fc_memalign;
543 546 uint32_t fc_memtag;
544 547 char fc_label[32];
545 548
546 549 } emlxs_memseg_t;
547 550 typedef emlxs_memseg_t MEMSEG;
548 551
549 552
550 553 /* Board stat counters */
551 554 typedef struct emlxs_stats
552 555 {
553 556 uint32_t LinkUp;
554 557 uint32_t LinkDown;
555 558 uint32_t LinkEvent;
556 559 uint32_t LinkMultiEvent;
557 560
558 561 uint32_t MboxIssued;
559 562 uint32_t MboxCompleted; /* MboxError + MbxGood */
560 563 uint32_t MboxGood;
561 564 uint32_t MboxError;
562 565 uint32_t MboxBusy;
563 566 uint32_t MboxInvalid;
564 567
565 568 uint32_t IocbIssued[MAX_CHANNEL];
566 569 uint32_t IocbReceived[MAX_CHANNEL];
567 570 uint32_t IocbTxPut[MAX_CHANNEL];
568 571 uint32_t IocbTxGet[MAX_CHANNEL];
569 572 uint32_t IocbRingFull[MAX_CHANNEL];
570 573 uint32_t IocbThrottled;
571 574
572 575 uint32_t IntrEvent[8];
573 576
574 577 uint32_t FcpIssued;
575 578 uint32_t FcpCompleted; /* FcpGood + FcpError */
576 579 uint32_t FcpGood;
577 580 uint32_t FcpError;
578 581
579 582 uint32_t FcpEvent; /* FcpStray + FcpCompleted */
580 583 uint32_t FcpStray;
581 584 #ifdef SFCT_SUPPORT
582 585 uint32_t FctRingEvent;
583 586 uint32_t FctRingError;
584 587 uint32_t FctRingDropped;
585 588 #endif /* SFCT_SUPPORT */
586 589
587 590 uint32_t ElsEvent; /* ElsStray + ElsCmplt (cmd + rsp) */
588 591 uint32_t ElsStray;
589 592
590 593 uint32_t ElsCmdIssued;
591 594 uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */
592 595 uint32_t ElsCmdGood;
593 596 uint32_t ElsCmdError;
594 597
595 598 uint32_t ElsRspIssued;
596 599 uint32_t ElsRspCompleted;
597 600
598 601 uint32_t ElsRcvEvent; /* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */
599 602 uint32_t ElsRcvError;
600 603 uint32_t ElsRcvDropped;
601 604 uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */
602 605 uint32_t ElsRscnReceived;
603 606 uint32_t ElsFlogiReceived;
604 607 uint32_t ElsPlogiReceived;
605 608 uint32_t ElsPrliReceived;
606 609 uint32_t ElsPrloReceived;
607 610 uint32_t ElsLogoReceived;
608 611 uint32_t ElsAdiscReceived;
609 612 uint32_t ElsAuthReceived;
610 613 uint32_t ElsGenReceived;
611 614
612 615 uint32_t CtEvent; /* CtStray + CtCompleted (cmd + rsp) */
613 616 uint32_t CtStray;
614 617
615 618 uint32_t CtCmdIssued;
616 619 uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */
617 620 uint32_t CtCmdGood;
618 621 uint32_t CtCmdError;
619 622
620 623 uint32_t CtRspIssued;
621 624 uint32_t CtRspCompleted;
622 625
623 626 uint32_t CtRcvEvent; /* CtRcvError + CtRcvDrop + CtCmdRcvd */
624 627 uint32_t CtRcvError;
625 628 uint32_t CtRcvDropped;
626 629 uint32_t CtCmdReceived;
627 630
628 631 uint32_t IpEvent; /* IpStray + IpSeqCmpl + IpBcastCmpl */
629 632 uint32_t IpStray;
630 633
631 634 uint32_t IpSeqIssued;
632 635 uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */
633 636 uint32_t IpSeqGood;
634 637 uint32_t IpSeqError;
635 638
636 639 uint32_t IpBcastIssued;
637 640 uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */
638 641 uint32_t IpBcastGood;
639 642 uint32_t IpBcastError;
640 643
641 644 uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */
642 645 uint32_t IpDropped;
643 646 uint32_t IpSeqReceived;
644 647 uint32_t IpBcastReceived;
645 648
646 649 uint32_t IpUbPosted;
647 650 uint32_t ElsUbPosted;
648 651 uint32_t CtUbPosted;
649 652 #ifdef SFCT_SUPPORT
650 653 uint32_t FctUbPosted;
651 654 #endif /* SFCT_SUPPORT */
652 655
653 656 uint32_t ResetTime; /* Time of last reset */
654 657
655 658 uint32_t ElsTestReceived;
656 659 uint32_t ElsEstcReceived;
657 660 uint32_t ElsFarprReceived;
658 661 uint32_t ElsEchoReceived;
659 662 uint32_t ElsRlsReceived;
660 663 uint32_t ElsRtvReceived;
661 664
662 665 } emlxs_stats_t;
663 666
664 667
665 668 #define FC_MAX_ADPTMSG (8*28) /* max size of a msg from adapter */
666 669
667 670 #define EMLXS_NUM_THREADS 8
668 671 #define EMLXS_MIN_TASKS 8
669 672 #define EMLXS_MAX_TASKS 8
670 673
671 674 #define EMLXS_NUM_HASH_QUES 32
672 675 #define EMLXS_DID_HASH(x) ((x) & (EMLXS_NUM_HASH_QUES - 1))
673 676
674 677
675 678 /* pkt_tran_flag */
676 679 #define FC_TRAN_COMPLETED 0x8000
677 680
678 681
679 682 typedef struct emlxs_dfc_event
680 683 {
681 684 uint32_t pid;
682 685 uint32_t event;
683 686 uint32_t last_id;
684 687
685 688 void *dataout;
686 689 uint32_t size;
687 690 uint32_t mode;
688 691 } emlxs_dfc_event_t;
689 692
690 693
691 694 typedef struct emlxs_hba_event
692 695 {
693 696 uint32_t last_id;
694 697 uint32_t new;
695 698 uint32_t missed;
696 699 } emlxs_hba_event_t;
697 700
698 701
699 702 #ifdef SFCT_SUPPORT
700 703
701 704 #define TGTPORTSTAT port->fct_stat
702 705
703 706 /*
704 707 * FctP2IOXcnt will count IOs by their fcpDL. Counters
705 708 * are for buckets of various power of 2 sizes.
706 709 * Bucket 0 < 512 > 0
707 710 * Bucket 1 >= 512 < 1024
708 711 * Bucket 2 >= 1024 < 2048
709 712 * Bucket 3 >= 2048 < 4096
710 713 * Bucket 4 >= 4096 < 8192
711 714 * Bucket 5 >= 8192 < 16K
712 715 * Bucket 6 >= 16K < 32K
713 716 * Bucket 7 >= 32K < 64K
714 717 * Bucket 8 >= 64K < 128K
715 718 * Bucket 9 >= 128K < 256K
716 719 * Bucket 10 >= 256K < 512K
717 720 * Bucket 11 >= 512K < 1MB
718 721 * Bucket 12 >= 1MB < 2MB
719 722 * Bucket 13 >= 2MB < 4MB
720 723 * Bucket 14 >= 4MB < 8MB
721 724 * Bucket 15 >= 8MB
722 725 */
723 726 #define MAX_TGTPORT_IOCNT 16
724 727
725 728
726 729 /*
727 730 * These routines will bump the right counter, based on
728 731 * the size of the IO inputed, with the least number of
729 732 * comparisions. A max of 5 comparisions is only needed
730 733 * to classify the IO in one of 16 ranges. A binary search
731 734 * to locate the high bit in the size is used.
732 735 */
733 736 #define EMLXS_BUMP_RDIOCTR(port, cnt) \
734 737 { \
735 738 /* Use binary search to find the first high bit */ \
736 739 if (cnt & 0xffff0000) { \
737 740 if (cnt & 0xff800000) { \
738 741 TGTPORTSTAT.FctP2IORcnt[15]++; \
739 742 } \
740 743 else { \
741 744 /* It must be 0x007f0000 */ \
742 745 if (cnt & 0x00700000) { \
743 746 if (cnt & 0x00400000) { \
744 747 TGTPORTSTAT.FctP2IORcnt[14]++; \
745 748 } \
746 749 else { \
747 750 /* it must be 0x00300000 */ \
748 751 if (cnt & 0x00200000) { \
749 752 TGTPORTSTAT.FctP2IORcnt[13]++; \
750 753 } \
751 754 else { \
752 755 /* It must be 0x00100000 */ \
753 756 TGTPORTSTAT.FctP2IORcnt[12]++; \
754 757 } \
755 758 } \
756 759 } \
757 760 else { \
758 761 /* It must be 0x000f0000 */ \
759 762 if (cnt & 0x000c0000) { \
760 763 if (cnt & 0x00080000) { \
761 764 TGTPORTSTAT.FctP2IORcnt[11]++; \
762 765 } \
763 766 else { \
764 767 /* It must be 0x00040000 */ \
765 768 TGTPORTSTAT.FctP2IORcnt[10]++; \
766 769 } \
767 770 } \
768 771 else { \
769 772 /* It must be 0x00030000 */ \
770 773 if (cnt & 0x00020000) { \
771 774 TGTPORTSTAT.FctP2IORcnt[9]++; \
772 775 } \
773 776 else { \
774 777 /* It must be 0x00010000 */ \
775 778 TGTPORTSTAT.FctP2IORcnt[8]++; \
776 779 } \
777 780 } \
778 781 } \
779 782 } \
780 783 } \
781 784 else { \
782 785 if (cnt & 0x0000fe00) { \
783 786 if (cnt & 0x0000f000) { \
784 787 if (cnt & 0x0000c000) { \
785 788 if (cnt & 0x00008000) { \
786 789 TGTPORTSTAT.FctP2IORcnt[7]++; \
787 790 } \
788 791 else { \
789 792 /* It must be 0x00004000 */ \
790 793 TGTPORTSTAT.FctP2IORcnt[6]++; \
791 794 } \
792 795 } \
793 796 else { \
794 797 /* It must be 0x00000300 */ \
795 798 if (cnt & 0x00000200) { \
796 799 TGTPORTSTAT.FctP2IORcnt[5]++; \
797 800 } \
798 801 else { \
799 802 /* It must be 0x00000100 */ \
800 803 TGTPORTSTAT.FctP2IORcnt[4]++; \
801 804 } \
802 805 } \
803 806 } \
804 807 else { \
805 808 /* It must be 0x00000e00 */ \
806 809 if (cnt & 0x00000800) { \
807 810 TGTPORTSTAT.FctP2IORcnt[3]++; \
808 811 } \
809 812 else { \
810 813 /* It must be 0x00000600 */ \
811 814 if (cnt & 0x00000400) { \
812 815 TGTPORTSTAT.FctP2IORcnt[2]++; \
813 816 } \
814 817 else { \
815 818 /* It must be 0x00000200 */ \
816 819 TGTPORTSTAT.FctP2IORcnt[1]++; \
817 820 } \
818 821 } \
819 822 } \
820 823 } \
821 824 else { \
822 825 /* It must be 0x000001ff */ \
823 826 TGTPORTSTAT.FctP2IORcnt[0]++; \
824 827 } \
825 828 } \
826 829 }
827 830
828 831
829 832 #define EMLXS_BUMP_WRIOCTR(port, cnt) \
830 833 { \
831 834 /* Use binary search to find the first high bit */ \
832 835 if (cnt & 0xffff0000) { \
833 836 if (cnt & 0xff800000) { \
834 837 TGTPORTSTAT.FctP2IOWcnt[15]++; \
835 838 } \
836 839 else { \
837 840 /* It must be 0x007f0000 */ \
838 841 if (cnt & 0x00700000) { \
839 842 if (cnt & 0x00400000) { \
840 843 TGTPORTSTAT.FctP2IOWcnt[14]++; \
841 844 } \
842 845 else { \
843 846 /* It must be 0x00300000 */ \
844 847 if (cnt & 0x00200000) { \
845 848 TGTPORTSTAT.FctP2IOWcnt[13]++; \
846 849 } \
847 850 else { \
848 851 /* It must be 0x00100000 */ \
849 852 TGTPORTSTAT.FctP2IOWcnt[12]++; \
850 853 } \
851 854 } \
852 855 } \
853 856 else { \
854 857 /* It must be 0x000f0000 */ \
855 858 if (cnt & 0x000c0000) { \
856 859 if (cnt & 0x00080000) { \
857 860 TGTPORTSTAT.FctP2IOWcnt[11]++; \
858 861 } \
859 862 else { \
860 863 /* it must be 0x00040000 */ \
861 864 TGTPORTSTAT.FctP2IOWcnt[10]++; \
862 865 } \
863 866 } \
864 867 else { \
865 868 /* It must be 0x00030000 */ \
866 869 if (cnt & 0x00020000) { \
867 870 TGTPORTSTAT.FctP2IOWcnt[9]++; \
868 871 } \
869 872 else { \
870 873 /* It must be 0x00010000 */ \
871 874 TGTPORTSTAT.FctP2IOWcnt[8]++; \
872 875 } \
873 876 } \
874 877 } \
875 878 } \
876 879 } \
877 880 else { \
878 881 if (cnt & 0x0000fe00) { \
879 882 if (cnt & 0x0000f000) { \
880 883 if (cnt & 0x0000c000) { \
881 884 if (cnt & 0x00008000) { \
882 885 TGTPORTSTAT.FctP2IOWcnt[7]++; \
883 886 } \
884 887 else { \
885 888 /* It must be 0x00004000 */ \
886 889 TGTPORTSTAT.FctP2IOWcnt[6]++; \
887 890 } \
888 891 } \
889 892 else { \
890 893 /* It must be 0x00000300 */ \
891 894 if (cnt & 0x00000200) { \
892 895 TGTPORTSTAT.FctP2IOWcnt[5]++; \
893 896 } \
894 897 else { \
895 898 /* It must be 0x00000100 */ \
896 899 TGTPORTSTAT.FctP2IOWcnt[4]++; \
897 900 } \
898 901 } \
899 902 } \
900 903 else { \
901 904 /* It must be 0x00000e00 */ \
902 905 if (cnt & 0x00000800) { \
903 906 TGTPORTSTAT.FctP2IOWcnt[3]++; \
904 907 } \
905 908 else { \
906 909 /* It must be 0x00000600 */ \
907 910 if (cnt & 0x00000400) { \
908 911 TGTPORTSTAT.FctP2IOWcnt[2]++; \
909 912 } \
910 913 else { \
911 914 /* It must be 0x00000200 */ \
912 915 TGTPORTSTAT.FctP2IOWcnt[1]++; \
913 916 } \
914 917 } \
915 918 } \
916 919 } \
917 920 else { \
918 921 /* It must be 0x000001ff */ \
919 922 TGTPORTSTAT.FctP2IOWcnt[0]++; \
920 923 } \
921 924 } \
922 925 }
923 926
924 927 typedef struct emlxs_tgtport_stat
925 928 {
926 929 /* IO counters */
927 930 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */
928 931 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */
929 932 uint64_t FctIOCmdCnt; /* Other, ie TUR */
930 933 uint64_t FctCmdReceived; /* total IOs */
931 934 uint64_t FctReadBytes; /* total read bytes */
932 935 uint64_t FctWriteBytes; /* total write bytes */
933 936
934 937 /* IOCB handling counters */
935 938 uint64_t FctEvent; /* FctStray + FctCompleted */
936 939 uint64_t FctCompleted; /* FctCmplGood + FctCmplError */
937 940 uint64_t FctCmplGood;
938 941
939 942 uint32_t FctCmplError;
940 943 uint32_t FctStray;
941 944
942 945 /* Fct event counters */
943 946 uint32_t FctRcvDropped;
944 947 uint32_t FctOverQDepth;
945 948 uint32_t FctOutstandingIO;
946 949 uint32_t FctFailedPortRegister;
947 950 uint32_t FctPortRegister;
948 951 uint32_t FctPortDeregister;
949 952
950 953 uint32_t FctAbortSent;
951 954 uint32_t FctNoBuffer;
952 955 uint32_t FctScsiStatusErr;
953 956 uint32_t FctScsiQfullErr;
954 957 uint32_t FctScsiResidOver;
955 958 uint32_t FctScsiResidUnder;
956 959 uint32_t FctScsiSenseErr;
957 960
958 961 uint32_t FctFiller1;
959 962 } emlxs_tgtport_stat_t;
960 963
961 964 #ifdef FCT_IO_TRACE
962 965 #define MAX_IO_TRACE 67
963 966 typedef struct emlxs_iotrace
964 967 {
965 968 fct_cmd_t *fct_cmd;
966 969 uint32_t xri;
967 970 uint8_t marker; /* 0xff */
968 971 uint8_t trc[MAX_IO_TRACE]; /* trc[0] = index */
969 972 } emlxs_iotrace_t;
970 973 #endif /* FCT_IO_TRACE */
971 974 #endif /* SFCT_SUPPORT */
972 975
973 976
974 977 #include <emlxs_fcf.h>
975 978
976 979 /*
977 980 * Port Information Data Structure
978 981 */
979 982
980 983 typedef struct emlxs_port
981 984 {
982 985 struct emlxs_hba *hba;
983 986
984 987 /* Virtual port management */
985 988 struct VPIobj VPIobj;
986 989 uint32_t vpi;
987 990
988 991 uint32_t flag;
989 992 #define EMLXS_PORT_ENABLE 0x00000001
990 993 #define EMLXS_PORT_BOUND 0x00000002
991 994
992 995 #define EMLXS_PORT_REG_VPI 0x00010000 /* SLI3 */
993 996 #define EMLXS_PORT_REG_VPI_CMPL 0x00020000 /* SLI3 */
994 997
995 998 #define EMLXS_PORT_IP_UP 0x00000010
996 999 #define EMLXS_PORT_CONFIG 0x00000020
997 1000 #define EMLXS_PORT_RESTRICTED 0x00000040 /* Restrict logins */
998 1001 #define EMLXS_PORT_FLOGI_CMPL 0x00000080
999 1002
1000 1003 #define EMLXS_PORT_RESET_MASK 0x0000FFFF /* Flags to keep */
1001 1004 /* across hard reset */
1002 1005 #define EMLXS_PORT_LINKDOWN_MASK 0xFFFFFF7F /* Flags to keep */
1003 1006 /* across link reset */
1004 1007
1005 1008 uint32_t options;
1006 1009 #define EMLXS_OPT_RESTRICT 0x00000001 /* Force restricted */
1007 1010 /* logins */
1008 1011 #define EMLXS_OPT_UNRESTRICT 0x00000002 /* Force Unrestricted */
1009 1012 /* logins */
1010 1013 #define EMLXS_OPT_RESTRICT_MASK 0x00000003
1011 1014
1012 1015
1013 1016 /* FC world wide names */
1014 1017 NAME_TYPE wwnn;
1015 1018 NAME_TYPE wwpn;
1016 1019 char snn[256];
1017 1020 char spn[256];
1018 1021
1019 1022 /* Common service paramters */
1020 1023 SERV_PARM sparam;
1021 1024 SERV_PARM fabric_sparam;
1022 1025 SERV_PARM prev_fabric_sparam;
1023 1026
1024 1027 /* fc_id management */
1025 1028 uint32_t did;
1026 1029 uint32_t prev_did;
1027 1030
1028 1031 /* support FC_PORT_GET_P2P_INFO only */
1029 1032 uint32_t rdid;
1030 1033
1031 1034 /* FC_AL management */
1032 1035 uint8_t lip_type;
1033 1036 uint8_t alpa_map[128];
1034 1037
1035 1038 /* Node management */
1036 1039 emlxs_node_t node_base;
1037 1040 uint32_t node_count;
1038 1041 krwlock_t node_rwlock;
1039 1042 emlxs_node_t *node_table[EMLXS_NUM_HASH_QUES];
1040 1043
1041 1044 /* Polled packet management */
1042 1045 kcondvar_t pkt_lock_cv; /* pkt polling */
1043 1046 kmutex_t pkt_lock; /* pkt polling */
1044 1047
1045 1048 /* ULP */
1046 1049 uint32_t ulp_statec;
1047 1050 void (*ulp_statec_cb) (); /* Port state change */
1048 1051 /* callback routine */
1049 1052 void (*ulp_unsol_cb) (); /* unsolicited event */
1050 1053 /* callback routine */
1051 1054 opaque_t ulp_handle;
1052 1055
1053 1056 /* ULP unsolicited buffers */
1054 1057 kmutex_t ub_lock;
1055 1058 uint32_t ub_count;
1056 1059 emlxs_unsol_buf_t *ub_pool;
1057 1060 uint32_t ub_post[MAX_CHANNEL];
1058 1061 uint32_t ub_timer;
1059 1062
1060 1063 emlxs_ub_priv_t *ub_wait_head; /* Unsolicited IO received */
1061 1064 /* before link up */
1062 1065 emlxs_ub_priv_t *ub_wait_tail; /* Unsolicited IO received */
1063 1066 /* before link up */
1064 1067
1065 1068
1066 1069 #ifdef DHCHAP_SUPPORT
1067 1070 emlxs_port_dhc_t port_dhc;
1068 1071 #endif /* DHCHAP_SUPPORT */
1069 1072
1070 1073 uint16_t ini_mode;
1071 1074 uint16_t tgt_mode;
1072 1075
1073 1076 #ifdef SFCT_SUPPORT
1074 1077
1075 1078 #define FCT_BUF_COUNT_512 256
1076 1079 #define FCT_BUF_COUNT_8K 128
1077 1080 #define FCT_BUF_COUNT_64K 64
1078 1081 #define FCT_BUF_COUNT_128K 64
1079 1082 #define FCT_MAX_BUCKETS 16
1080 1083 #define FCT_DMEM_MAX_BUF_SIZE 131072 /* 128K */
1081 1084 #define FCT_DMEM_MAX_BUF_SEGMENT 8388608 /* 8M */
1082 1085
1083 1086 struct emlxs_fct_dmem_bucket dmem_bucket[FCT_MAX_BUCKETS];
1084 1087
1085 1088 char cfd_name[24];
1086 1089 stmf_port_provider_t *port_provider;
1087 1090 fct_local_port_t *fct_port;
1088 1091 uint32_t fct_flags;
1089 1092
1090 1093 #define FCT_STATE_PORT_ONLINE 0x00000001
1091 1094 #define FCT_STATE_NOT_ACKED 0x00000002
1092 1095 #define FCT_STATE_LINK_UP 0x00000010
1093 1096 #define FCT_STATE_LINK_UP_ACKED 0x00000020
1094 1097
1095 1098 emlxs_tgtport_stat_t fct_stat;
1096 1099
1097 1100 /* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
1098 1101 emlxs_buf_t *fct_wait_head;
1099 1102 emlxs_buf_t *fct_wait_tail;
1100 1103
1101 1104 /* Used to save context for deferred unsol FLOGIs */
1102 1105 fct_flogi_xchg_t fx;
1103 1106
1104 1107 #ifdef FCT_IO_TRACE
1105 1108 emlxs_iotrace_t *iotrace;
1106 1109 uint16_t iotrace_cnt;
1107 1110 uint16_t iotrace_index;
1108 1111 kmutex_t iotrace_mtx;
1109 1112 #endif /* FCT_IO_TRACE */
1110 1113
1111 1114 #endif /* SFCT_SUPPORT */
1112 1115
1113 1116 #ifdef SAN_DIAG_SUPPORT
1114 1117 uint8_t sd_io_latency_state;
1115 1118 #define SD_INVALID 0x00
1116 1119 #define SD_COLLECTING 0x01
1117 1120 #define SD_STOPPED 0x02
1118 1121
1119 1122 /* SD event management list */
1120 1123 uint32_t sd_event_mask; /* bit-mask */
1121 1124 emlxs_dfc_event_t sd_events[MAX_DFC_EVENTS];
1122 1125 #endif
1123 1126
1124 1127 } emlxs_port_t;
1125 1128
1126 1129
1127 1130 /* Host Attn reg */
1128 1131 #define FC_HA_REG(_hba) ((volatile uint32_t *) \
1129 1132 ((_hba)->sli.sli3.ha_reg_addr))
1130 1133
1131 1134 /* Chip Attn reg */
1132 1135 #define FC_CA_REG(_hba) ((volatile uint32_t *) \
1133 1136 ((_hba)->sli.sli3.ca_reg_addr))
1134 1137
1135 1138 /* Host Status reg */
1136 1139 #define FC_HS_REG(_hba) ((volatile uint32_t *) \
1137 1140 ((_hba)->sli.sli3.hs_reg_addr))
1138 1141
1139 1142 /* Host Cntl reg */
1140 1143 #define FC_HC_REG(_hba) ((volatile uint32_t *) \
1141 1144 ((_hba)->sli.sli3.hc_reg_addr))
1142 1145
1143 1146 /* BIU Configuration reg */
1144 1147 #define FC_BC_REG(_hba) ((volatile uint32_t *) \
1145 1148 ((_hba)->sli.sli3.bc_reg_addr))
1146 1149
1147 1150 /* Used by SBUS adapter */
1148 1151 /* TITAN Cntl reg */
1149 1152 #define FC_SHC_REG(_hba) ((volatile uint32_t *) \
1150 1153 ((_hba)->sli.sli3.shc_reg_addr))
1151 1154
1152 1155 /* TITAN Status reg */
1153 1156 #define FC_SHS_REG(_hba) ((volatile uint32_t *) \
1154 1157 ((_hba)->sli.sli3.shs_reg_addr))
1155 1158
1156 1159 /* TITAN Update reg */
1157 1160 #define FC_SHU_REG(_hba) ((volatile uint32_t *) \
1158 1161 ((_hba)->sli.sli3.shu_reg_addr))
1159 1162
1160 1163 /* MPU Semaphore reg */
1161 1164 #define FC_SEMA_REG(_hba) ((volatile uint32_t *)\
1162 1165 ((_hba)->sli.sli4.MPUEPSemaphore_reg_addr))
1163 1166
1164 1167 /* Bootstrap Mailbox Doorbell reg */
1165 1168 #define FC_MBDB_REG(_hba) ((volatile uint32_t *) \
1166 1169 ((_hba)->sli.sli4.MBDB_reg_addr))
1167 1170
1168 1171 /* MQ Doorbell reg */
1169 1172 #define FC_MQDB_REG(_hba) ((volatile uint32_t *) \
1170 1173 ((_hba)->sli.sli4.MQDB_reg_addr))
1171 1174
1172 1175 /* CQ Doorbell reg */
1173 1176 #define FC_CQDB_REG(_hba) ((volatile uint32_t *) \
1174 1177 ((_hba)->sli.sli4.CQDB_reg_addr))
1175 1178
1176 1179 /* WQ Doorbell reg */
1177 1180 #define FC_WQDB_REG(_hba) ((volatile uint32_t *) \
1178 1181 ((_hba)->sli.sli4.WQDB_reg_addr))
1179 1182
1180 1183 /* RQ Doorbell reg */
1181 1184 #define FC_RQDB_REG(_hba) ((volatile uint32_t *) \
1182 1185 ((_hba)->sli.sli4.RQDB_reg_addr))
1183 1186
1184 1187
1185 1188 #define FC_SLIM2_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim2.virt)
1186 1189
1187 1190 #define FC_SLIM1_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim_addr)
1188 1191
1189 1192 #define FC_MAILBOX(_hba) (((_hba)->flag & FC_SLIM2_MODE) ? \
1190 1193 FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba))
1191 1194
1192 1195 #define WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\
1193 1196 (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp), \
1194 1197 (uint32_t)(_value))
1195 1198
1196 1199 #define READ_CSR_REG(_hba, _regp) ddi_get32(\
1197 1200 (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp))
1198 1201
1199 1202 #define WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\
1200 1203 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp), \
1201 1204 (uint32_t)(_value))
1202 1205
1203 1206 #define READ_SLIM_ADDR(_hba, _regp) ddi_get32(\
1204 1207 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp))
1205 1208
1206 1209 #define WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\
1207 1210 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1208 1211 (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1209 1212
1210 1213 #define READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\
1211 1214 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1212 1215 (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1213 1216
1214 1217 /* Used by SBUS adapter */
1215 1218 #define WRITE_SBUS_CSR_REG(_hba, _regp, _value) ddi_put32(\
1216 1219 (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp), \
1217 1220 (uint32_t)(_value))
1218 1221
1219 1222 #define READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\
1220 1223 (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp))
1221 1224
1222 1225 #define SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\
1223 1226 (_hba)->sli.sli3.sbus_flash_acc_handle, \
1224 1227 (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1225 1228 (_offset)), (uint8_t)(_value))
1226 1229
1227 1230 #define SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\
1228 1231 (_hba)->sli.sli3.sbus_flash_acc_handle, \
1229 1232 (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1230 1233 (_offset)))
1231 1234
1232 1235 /* SLI4 registers */
1233 1236 #define WRITE_BAR1_REG(_hba, _regp, _value) ddi_put32(\
1234 1237 (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp), \
1235 1238 (uint32_t)(_value))
1236 1239
1237 1240 #define READ_BAR1_REG(_hba, _regp) ddi_get32(\
1238 1241 (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp))
1239 1242
1240 1243 #define WRITE_BAR2_REG(_hba, _regp, _value) ddi_put32(\
1241 1244 (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp), \
1242 1245 (uint32_t)(_value))
1243 1246
1244 1247 #define READ_BAR2_REG(_hba, _regp) ddi_get32(\
1245 1248 (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp))
1246 1249
1247 1250
1248 1251 #define EMLXS_STATE_CHANGE(_hba, _state)\
1249 1252 { \
1250 1253 mutex_enter(&EMLXS_PORT_LOCK); \
1251 1254 EMLXS_STATE_CHANGE_LOCKED((_hba), (_state)); \
1252 1255 mutex_exit(&EMLXS_PORT_LOCK); \
1253 1256 }
1254 1257
1255 1258 /* Used when EMLXS_PORT_LOCK is already held */
1256 1259 #define EMLXS_STATE_CHANGE_LOCKED(_hba, _state) \
1257 1260 { \
1258 1261 if ((_hba)->state != (_state)) \
1259 1262 { \
1260 1263 uint32_t _st = _state; \
1261 1264 EMLXS_MSGF(EMLXS_CONTEXT, \
1262 1265 &emlxs_state_msg, "%s --> %s", \
1263 1266 emlxs_ffstate_xlate((_hba)->state), \
1264 1267 emlxs_ffstate_xlate(_state)); \
1265 1268 (_hba)->state = (_state); \
1266 1269 if ((_st) == FC_ERROR) \
1267 1270 { \
1268 1271 (_hba)->flag |= FC_HARDWARE_ERROR; \
1269 1272 } \
1270 1273 } \
1271 1274 }
1272 1275
1273 1276 #ifdef FMA_SUPPORT
1274 1277 #define EMLXS_CHK_ACC_HANDLE(_hba, _acc) \
1275 1278 if (emlxs_fm_check_acc_handle(_hba, _acc) != DDI_FM_OK) { \
1276 1279 EMLXS_MSGF(EMLXS_CONTEXT, \
1277 1280 &emlxs_invalid_access_handle_msg, NULL); \
1278 1281 }
1279 1282 #endif /* FMA_SUPPORT */
1280 1283
1281 1284 /*
1282 1285 * This is the HBA control area for the adapter
1283 1286 */
1284 1287
1285 1288 #ifdef MODSYM_SUPPORT
1286 1289
1287 1290 typedef struct emlxs_modsym
1288 1291 {
1289 1292 ddi_modhandle_t mod_fctl; /* For Leadville */
1290 1293
1291 1294 /* Leadville (fctl) */
1292 1295 int (*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *);
1293 1296 int (*fc_fca_detach)(dev_info_t *);
1294 1297 int (*fc_fca_init)(struct dev_ops *);
1295 1298
1296 1299 #ifdef SFCT_SUPPORT
1297 1300 uint32_t fct_modopen;
1298 1301 uint32_t reserved; /* Padding for alignment */
1299 1302
1300 1303 ddi_modhandle_t mod_fct; /* For Comstar */
1301 1304 ddi_modhandle_t mod_stmf; /* For Comstar */
1302 1305
1303 1306 /* Comstar (fct) */
1304 1307 void* (*fct_alloc)(fct_struct_id_t, int, int);
1305 1308 void (*fct_free)(void *);
1306 1309 void* (*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *,
1307 1310 uint16_t, uint16_t);
1308 1311 int (*fct_register_local_port)(fct_local_port_t *);
1309 1312 void (*fct_deregister_local_port)(fct_local_port_t *);
1310 1313 void (*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t);
1311 1314 void (*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *);
1312 1315 void (*fct_ctl)(void *, int, void *);
1313 1316 void (*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t);
1314 1317 void (*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t);
1315 1318 void (*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t);
1316 1319 void (*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *,
1317 1320 uint32_t);
1318 1321 fct_status_t (*fct_port_shutdown)
1319 1322 (fct_local_port_t *, uint32_t, char *);
1320 1323 fct_status_t (*fct_port_initialize)
1321 1324 (fct_local_port_t *, uint32_t, char *);
1322 1325 void (*fct_cmd_fca_aborted)
1323 1326 (fct_cmd_t *, fct_status_t, int);
1324 1327 fct_status_t (*fct_handle_rcvd_flogi)
1325 1328 (fct_local_port_t *, fct_flogi_xchg_t *);
1326 1329
1327 1330 /* Comstar (stmf) */
1328 1331 void* (*stmf_alloc)(stmf_struct_id_t, int, int);
1329 1332 void (*stmf_free)(void *);
1330 1333 void (*stmf_deregister_port_provider) (stmf_port_provider_t *);
1331 1334 int (*stmf_register_port_provider) (stmf_port_provider_t *);
1332 1335 #endif /* SFCT_SUPPORT */
1333 1336 } emlxs_modsym_t;
1334 1337 extern emlxs_modsym_t emlxs_modsym;
1335 1338
1336 1339 #define MODSYM(_f) emlxs_modsym._f
1337 1340
1338 1341 #else
1339 1342
1340 1343 #define MODSYM(_f) _f
1341 1344
1342 1345 #endif /* MODSYM_SUPPORT */
1343 1346
1344 1347
1345 1348
1346 1349 typedef struct RPIHdrTmplate
1347 1350 {
1348 1351 uint32_t Word[16]; /* 64 bytes */
1349 1352 } RPIHdrTmplate_t;
1350 1353
1351 1354
1352 1355 typedef struct EQ_DESC
1353 1356 {
1354 1357 uint16_t host_index;
1355 1358 uint16_t max_index;
1356 1359 uint16_t qid;
1357 1360 uint16_t msix_vector;
1358 1361 kmutex_t lastwq_lock;
1359 1362 uint16_t lastwq;
1360 1363 MBUF_INFO addr;
1361 1364 } EQ_DESC_t;
1362 1365
1363 1366
1364 1367 typedef struct CQ_DESC
1365 1368 {
1366 1369 uint16_t host_index;
1367 1370 uint16_t max_index;
1368 1371 uint16_t qid;
1369 1372 uint16_t eqid;
1370 1373 uint16_t type;
1371 1374 #define EMLXS_CQ_TYPE_GROUP1 1 /* associated with a MQ and async events */
1372 1375 #define EMLXS_CQ_TYPE_GROUP2 2 /* associated with a WQ and RQ */
1373 1376 uint16_t rsvd;
1374 1377
1375 1378 MBUF_INFO addr;
1376 1379 CHANNEL *channelp; /* ptr to CHANNEL associated with CQ */
1377 1380
1378 1381 } CQ_DESC_t;
1379 1382
1380 1383
1381 1384 typedef struct WQ_DESC
1382 1385 {
1383 1386 uint16_t host_index;
1384 1387 uint16_t max_index;
1385 1388 uint16_t port_index;
1386 1389 uint16_t release_depth;
1387 1390 #define WQE_RELEASE_DEPTH (8 * EMLXS_NUM_WQ_PAGES)
1388 1391 uint16_t qid;
1389 1392 uint16_t cqid;
1390 1393 MBUF_INFO addr;
1391 1394 } WQ_DESC_t;
1392 1395
1393 1396
1394 1397 typedef struct RQ_DESC
1395 1398 {
1396 1399 uint16_t host_index;
1397 1400 uint16_t max_index;
1398 1401 uint16_t qid;
1399 1402 uint16_t cqid;
1400 1403
1401 1404 MBUF_INFO addr;
1402 1405 MBUF_INFO rqb[RQ_DEPTH];
1403 1406
1404 1407 kmutex_t lock;
1405 1408
1406 1409 } RQ_DESC_t;
1407 1410
1408 1411
1409 1412 typedef struct RXQ_DESC
1410 1413 {
1411 1414 kmutex_t lock;
1412 1415 emlxs_queue_t active;
1413 1416
1414 1417 } RXQ_DESC_t;
1415 1418
1416 1419
1417 1420 typedef struct MQ_DESC
1418 1421 {
1419 1422 uint16_t host_index;
1420 1423 uint16_t max_index;
1421 1424 uint16_t qid;
1422 1425 uint16_t cqid;
1423 1426 MBUF_INFO addr;
1424 1427 } MQ_DESC_t;
1425 1428
1426 1429
1427 1430 /* Define the number of queues the driver will be using */
1428 1431 #define EMLXS_MAX_EQS EMLXS_MSI_MAX_INTRS
1429 1432 #define EMLXS_MAX_WQS EMLXS_MSI_MAX_INTRS
1430 1433 #define EMLXS_MAX_RQS 2 /* ONLY 1 pair is allowed */
1431 1434 #define EMLXS_MAX_MQS 1
1432 1435
1433 1436 /* One CQ for each WQ & (RQ pair) plus one for the MQ */
1434 1437 #define EMLXS_MAX_CQS (EMLXS_MAX_WQS + (EMLXS_MAX_RQS/2) + 1)
1435 1438
1436 1439 /* The First CQ created is ALWAYS for mbox / event handling */
1437 1440 #define EMLXS_CQ_MBOX 0
1438 1441
1439 1442 /* The Second CQ created is ALWAYS for unsol rcv handling */
1440 1443 /* At this time we are allowing ONLY 1 pair of RQs */
1441 1444 #define EMLXS_CQ_RCV 1
1442 1445
1443 1446 /* The remaining CQs are for WQ completions */
1444 1447 #define EMLXS_CQ_OFFSET_WQ 2
1445 1448
1446 1449
1447 1450 /* FCFI RQ Configuration */
1448 1451 #define EMLXS_FCFI_RQ0_INDEX 0
1449 1452 #define EMLXS_FCFI_RQ0_RMASK 0 /* match all */
1450 1453 #define EMLXS_FCFI_RQ0_RCTL 0 /* match all */
1451 1454 #define EMLXS_FCFI_RQ0_TMASK 0 /* match all */
1452 1455 #define EMLXS_FCFI_RQ0_TYPE 0 /* match all */
1453 1456
1454 1457 /* Define the maximum value for a Queue Id */
1455 1458 #define EMLXS_MAX_EQ_IDS 256
1456 1459 #define EMLXS_MAX_CQ_IDS 1024
1457 1460 #define EMLXS_MAX_WQ_IDS 1024
1458 1461 #define EMLXS_MAX_RQ_IDS 4
1459 1462
1460 1463 #define EMLXS_RXQ_ELS 0
1461 1464 #define EMLXS_RXQ_CT 1
1462 1465 #define EMLXS_MAX_RXQS 2
1463 1466
1464 1467 #define PCI_CONFIG_SIZE 0x80
1465 1468
1466 1469 typedef struct emlxs_sli3
1467 1470 {
1468 1471 /* SLIM management */
1469 1472 MATCHMAP slim2;
1470 1473
1471 1474 /* HBQ management */
1472 1475 uint32_t hbq_count; /* Total number of HBQs */
1473 1476 /* configured */
1474 1477 HBQ_INIT_t hbq_table[EMLXS_NUM_HBQ];
1475 1478
1476 1479 /* Adapter memory management */
1477 1480 caddr_t csr_addr;
1478 1481 caddr_t slim_addr;
1479 1482 ddi_acc_handle_t csr_acc_handle;
1480 1483 ddi_acc_handle_t slim_acc_handle;
1481 1484
1482 1485 /* SBUS adapter management */
1483 1486 caddr_t sbus_flash_addr; /* Virt addr of R/W */
1484 1487 /* Flash */
1485 1488 caddr_t sbus_core_addr; /* Virt addr of TITAN */
1486 1489 /* CORE */
1487 1490 caddr_t sbus_csr_addr; /* Virt addr of TITAN */
1488 1491 /* CSR */
1489 1492 ddi_acc_handle_t sbus_flash_acc_handle;
1490 1493 ddi_acc_handle_t sbus_core_acc_handle;
1491 1494 ddi_acc_handle_t sbus_csr_handle;
1492 1495
1493 1496 /* SLI 2/3 Adapter register management */
1494 1497 uint32_t *bc_reg_addr; /* virtual offset for BIU */
1495 1498 /* config reg */
1496 1499 uint32_t *ha_reg_addr; /* virtual offset for host */
1497 1500 /* attn reg */
1498 1501 uint32_t *hc_reg_addr; /* virtual offset for host */
1499 1502 /* ctl reg */
1500 1503 uint32_t *ca_reg_addr; /* virtual offset for FF */
1501 1504 /* attn reg */
1502 1505 uint32_t *hs_reg_addr; /* virtual offset for */
1503 1506 /* status reg */
1504 1507 uint32_t *shc_reg_addr; /* virtual offset for SBUS */
1505 1508 /* Ctrl reg */
1506 1509 uint32_t *shs_reg_addr; /* virtual offset for SBUS */
1507 1510 /* Status reg */
1508 1511 uint32_t *shu_reg_addr; /* virtual offset for SBUS */
1509 1512 /* Update reg */
1510 1513 uint16_t hgp_ring_offset;
1511 1514 uint16_t hgp_hbq_offset;
1512 1515 uint16_t iocb_cmd_size;
1513 1516 uint16_t iocb_rsp_size;
1514 1517 uint32_t hc_copy; /* local copy of HC register */
1515 1518
1516 1519 /* Ring management */
1517 1520 uint32_t ring_count;
1518 1521 emlxs_ring_t ring[MAX_RINGS];
1519 1522 kmutex_t ring_cmd_lock[MAX_RINGS];
1520 1523 uint8_t ring_masks[4]; /* number of masks/rings used */
1521 1524 uint8_t ring_rval[6];
1522 1525 uint8_t ring_rmask[6];
1523 1526 uint8_t ring_tval[6];
1524 1527 uint8_t ring_tmask[6];
1525 1528
1526 1529 /* Protected by EMLXS_FCTAB_LOCK */
1527 1530 #ifdef EMLXS_SPARC
1528 1531 MEMSEG fcp_bpl_seg;
1529 1532 MATCHMAP **fcp_bpl_table; /* iotag table for */
1530 1533 /* bpl buffers */
1531 1534 #endif /* EMLXS_SPARC */
1532 1535 uint32_t mem_bpl_size;
1533 1536 } emlxs_sli3_t;
1534 1537
1535 1538 typedef struct emlxs_sli4
1536 1539 {
1537 1540 MATCHMAP bootstrapmb;
1538 1541 caddr_t bar1_addr;
1539 1542 caddr_t bar2_addr;
1540 1543 ddi_acc_handle_t bar1_acc_handle;
1541 1544 ddi_acc_handle_t bar2_acc_handle;
1542 1545
1543 1546 /* SLI4 Adapter register management */
1544 1547 uint32_t *MPUEPSemaphore_reg_addr;
1545 1548 uint32_t *MBDB_reg_addr;
1546 1549
1547 1550 uint32_t *CQDB_reg_addr;
1548 1551 uint32_t *MQDB_reg_addr;
1549 1552 uint32_t *WQDB_reg_addr;
1550 1553 uint32_t *RQDB_reg_addr;
1551 1554
1552 1555 uint32_t flag;
1553 1556 #define EMLXS_SLI4_INTR_ENABLED 0x00000001
1554 1557 #define EMLXS_SLI4_HW_ERROR 0x00000002
1555 1558 #define EMLXS_SLI4_DOWN_LINK 0x00000004
1556 1559
1557 1560 uint16_t XRICount;
1558 1561 uint16_t XRIBase;
1559 1562 uint16_t RPICount;
1560 1563 uint16_t RPIBase;
1561 1564 uint16_t VPICount;
1562 1565 uint16_t VPIBase;
1563 1566 uint16_t VFICount;
1564 1567 uint16_t VFIBase;
1565 1568 uint16_t FCFICount;
1566 1569
1567 1570 kmutex_t fcf_lock;
1568 1571 FCFTable_t fcftab;
1569 1572 VFIobj_t *VFI_table;
1570 1573
1571 1574 /* Save Config Region 23 info */
1572 1575 tlv_fcoe_t cfgFCOE;
1573 1576 tlv_fcfconnectlist_t cfgFCF;
1574 1577
1575 1578 MBUF_INFO slim2;
1576 1579 MBUF_INFO dump_region;
1577 1580 #define EMLXS_DUMP_REGION_SIZE 1024
1578 1581
1579 1582 RPIobj_t *RPIp;
1580 1583 MBUF_INFO HeaderTmplate;
1581 1584 XRIobj_t *XRIp;
1582 1585
1583 1586 /* Double linked list for available XRIs */
1584 1587 XRIobj_t *XRIfree_f;
1585 1588 XRIobj_t *XRIfree_b;
1586 1589 uint32_t xrif_count;
1587 1590 uint32_t mem_sgl_size;
1588 1591
1589 1592 /* Double linked list for XRIs in use */
1590 1593 XRIobj_t *XRIinuse_f;
1591 1594 XRIobj_t *XRIinuse_b;
1592 1595 uint32_t xria_count;
1593 1596
1594 1597 kmutex_t que_lock[EMLXS_MAX_WQS];
1595 1598 EQ_DESC_t eq[EMLXS_MAX_EQS];
1596 1599 CQ_DESC_t cq[EMLXS_MAX_CQS];
1597 1600 WQ_DESC_t wq[EMLXS_MAX_WQS];
1598 1601 RQ_DESC_t rq[EMLXS_MAX_RQS];
1599 1602 MQ_DESC_t mq;
1600 1603
1601 1604 /* Used to map a queue ID to a queue DESC_t */
1602 1605 uint16_t eq_map[EMLXS_MAX_EQ_IDS];
1603 1606 uint16_t cq_map[EMLXS_MAX_CQ_IDS];
1604 1607 uint16_t wq_map[EMLXS_MAX_WQ_IDS];
1605 1608 uint16_t rq_map[EMLXS_MAX_RQ_IDS];
1606 1609
1607 1610 RXQ_DESC_t rxq[EMLXS_MAX_RXQS];
1608 1611
1609 1612 uint32_t ue_mask_lo;
1610 1613 uint32_t ue_mask_hi;
1611 1614
1612 1615 } emlxs_sli4_t;
1613 1616
1614 1617
1615 1618 typedef struct emlxs_sli_api
1616 1619 {
1617 1620 int (*sli_map_hdw)();
1618 1621 void (*sli_unmap_hdw)();
1619 1622 int32_t (*sli_online)();
1620 1623 void (*sli_offline)();
1621 1624 uint32_t (*sli_hba_reset)();
1622 1625 void (*sli_hba_kill)();
1623 1626 void (*sli_issue_iocb_cmd)();
1624 1627 uint32_t (*sli_issue_mbox_cmd)();
1625 1628 uint32_t (*sli_prep_fct_iocb)();
1626 1629 uint32_t (*sli_prep_fcp_iocb)();
1627 1630 uint32_t (*sli_prep_ip_iocb)();
1628 1631 uint32_t (*sli_prep_els_iocb)();
1629 1632 uint32_t (*sli_prep_ct_iocb)();
1630 1633 void (*sli_poll_intr)();
1631 1634 int32_t (*sli_intx_intr)();
1632 1635 uint32_t (*sli_msi_intr)();
1633 1636 void (*sli_disable_intr)();
1634 1637 void (*sli_timer)();
1635 1638 void (*sli_poll_erratt)();
1636 1639
1637 1640 } emlxs_sli_api_t;
1638 1641
1639 1642
1640 1643 typedef struct emlxs_hba
1641 1644 {
1642 1645 dev_info_t *dip;
1643 1646 int32_t emlxinst;
1644 1647 int32_t ddiinst;
1645 1648 uint8_t pci_function_number;
1646 1649 uint8_t pci_device_number;
1647 1650 uint8_t pci_bus_number;
1648 1651 uint8_t pci_cap_offset[PCI_CAP_MAX_PTR];
1649 1652
1650 1653 #ifdef FMA_SUPPORT
1651 1654 int32_t fm_caps; /* FMA capabilities */
1652 1655 #endif /* FMA_SUPPORT */
1653 1656 fc_fca_tran_t *fca_tran;
1654 1657
1655 1658 /* DMA attributes */
1656 1659 ddi_dma_attr_t dma_attr;
1657 1660 ddi_dma_attr_t dma_attr_ro;
1658 1661 ddi_dma_attr_t dma_attr_1sg;
1659 1662 ddi_dma_attr_t dma_attr_fcip_rsp;
1660 1663
1661 1664 /* HBA Info */
1662 1665 emlxs_model_t model_info;
1663 1666 emlxs_vpd_t vpd; /* vital product data */
1664 1667 NAME_TYPE wwnn;
1665 1668 NAME_TYPE wwpn;
1666 1669 char snn[256];
1667 1670 char spn[256];
1668 1671 PROG_ID load_list[MAX_LOAD_ENTRY];
1669 1672 WAKE_UP_PARMS wakeup_parms;
1670 1673 uint32_t max_nodes;
1671 1674 uint32_t io_throttle;
1672 1675 uint32_t io_active;
1673 1676 uint32_t bus_type;
1674 1677 #define PCI_FC 0
1675 1678 #define SBUS_FC 1
1676 1679
1677 1680 /* Link management */
1678 1681 uint32_t link_event_tag;
1679 1682 uint8_t topology;
1680 1683 uint8_t linkspeed;
1681 1684 uint16_t qos_linkspeed;
1682 1685 uint32_t linkup_wait_flag;
1683 1686 kcondvar_t linkup_lock_cv;
1684 1687 kmutex_t linkup_lock;
1685 1688
1686 1689 /* Memory Pool management */
1687 1690 emlxs_memseg_t memseg[FC_MAX_SEG]; /* memory for buffer */
1688 1691 /* structures */
1689 1692 kmutex_t memget_lock; /* locks all memory pools get */
1690 1693 kmutex_t memput_lock; /* locks all memory pools put */
1691 1694
1692 1695 /* Fibre Channel Service Parameters */
1693 1696 SERV_PARM sparam;
1694 1697 uint32_t fc_edtov; /* E_D_TOV timer value */
1695 1698 uint32_t fc_arbtov; /* ARB_TOV timer value */
1696 1699 uint32_t fc_ratov; /* R_A_TOV timer value */
1697 1700 uint32_t fc_rttov; /* R_T_TOV timer value */
1698 1701 uint32_t fc_altov; /* AL_TOV timer value */
1699 1702 uint32_t fc_crtov; /* C_R_TOV timer value */
1700 1703 uint32_t fc_citov; /* C_I_TOV timer value */
1701 1704
1702 1705 /* Adapter State management */
1703 1706 int32_t state;
1704 1707 #define FC_ERROR 0x01 /* Adapter shutdown */
1705 1708 #define FC_KILLED 0x02 /* Adapter interlocked/killed */
1706 1709 #define FC_WARM_START 0x03 /* Adapter reset, but not restarted */
1707 1710 #define FC_INIT_START 0x10 /* Adapter restarted */
1708 1711 #define FC_INIT_NVPARAMS 0x11
1709 1712 #define FC_INIT_REV 0x12
1710 1713 #define FC_INIT_CFGPORT 0x13
1711 1714 #define FC_INIT_CFGRING 0x14
1712 1715 #define FC_INIT_INITLINK 0x15
1713 1716 #define FC_LINK_DOWN 0x20
1714 1717 #define FC_LINK_DOWN_PERSIST 0x21
1715 1718 #define FC_LINK_UP 0x30
1716 1719 #define FC_CLEAR_LA 0x31
1717 1720 #define FC_READY 0x40
1718 1721
1719 1722 uint32_t flag;
1720 1723 #define FC_ONLINING_MODE 0x00000001
1721 1724 #define FC_ONLINE_MODE 0x00000002
1722 1725 #define FC_OFFLINING_MODE 0x00000004
1723 1726 #define FC_OFFLINE_MODE 0x00000008
1724 1727
1725 1728 #define FC_NPIV_ENABLED 0x00000010 /* NPIV enabled on adapter */
1726 1729 #define FC_NPIV_SUPPORTED 0x00000020 /* NPIV supported on fabric */
1727 1730 #define FC_NPIV_UNSUPPORTED 0x00000040 /* NPIV unsupported on fabric */
1728 1731 #define FC_NPIV_LINKUP 0x00000100 /* NPIV enabled, supported, */
1729 1732 /* and link is ready */
1730 1733 #define FC_NPIV_DELAY_REQUIRED 0x00000200 /* Delay issuing FLOGI/FDISC */
1731 1734 /* and NameServer cmds */
1732 1735
1733 1736 #define FC_BOOTSTRAPMB_INIT 0x00000400
1734 1737 #define FC_FIP_SUPPORTED 0x00000800 /* FIP supported */
1735 1738
1736 1739 #define FC_FABRIC_ATTACHED 0x00001000
1737 1740 #define FC_PT_TO_PT 0x00002000
1738 1741 #define FC_BYPASSED_MODE 0x00004000
1739 1742 #define FC_MENLO_MODE 0x00008000 /* Menlo maintenance mode */
1740 1743
1741 1744 #define FC_DUMP_SAFE 0x00010000 /* Safe to DUMP */
1742 1745 #define FC_DUMP_ACTIVE 0x00020000 /* DUMP in progress */
1743 1746 #define FC_NEW_FABRIC 0x00040000
1744 1747
1745 1748 #define FC_SLIM2_MODE 0x00100000 /* SLIM in host memory */
1746 1749 #define FC_INTERLOCKED 0x00200000
1747 1750 #define FC_HBQ_ENABLED 0x00400000
1748 1751 #define FC_ASYNC_EVENTS 0x00800000
1749 1752
1750 1753 #define FC_ILB_MODE 0x01000000
1751 1754 #define FC_ELB_MODE 0x02000000
1752 1755 #define FC_LOOPBACK_MODE 0x03000000 /* Loopback Mode Mask */
1753 1756 #define FC_DUMP 0x04000000 /* DUMP in progress */
1754 1757 #define FC_SHUTDOWN 0x08000000 /* SHUTDOWN in progress */
1755 1758
1756 1759 #define FC_OVERTEMP_EVENT 0x10000000 /* FC_ERROR reason: */
1757 1760 /* over temperature event */
1758 1761 #define FC_MBOX_TIMEOUT 0x20000000 /* FC_ERROR reason: */
1759 1762 /* mailbox timeout event */
1760 1763 #define FC_DMA_CHECK_ERROR 0x40000000 /* Shared memory (slim,..) */
1761 1764 /* DMA handle went bad */
1762 1765 #define FC_HARDWARE_ERROR 0x80000000 /* FC_ERROR state triggered */
1763 1766
1764 1767 #define FC_RESET_MASK 0x00030C1F /* Bits to protect during */
1765 1768 /* a hard reset */
1766 1769 #define FC_LINKDOWN_MASK 0xFFF30C1F /* Bits to protect during */
1767 1770 /* a linkdown */
1768 1771
1769 1772 uint32_t fw_timer;
1770 1773 uint32_t fw_flag;
1771 1774 #define FW_UPDATE_NEEDED 0x00000001
1772 1775 #define FW_UPDATE_KERNEL 0x00000002
1773 1776
1774 1777 uint32_t temperature; /* Last reported temperature */
1775 1778
1776 1779 /* SBUS adapter management */
1777 1780 caddr_t sbus_pci_addr; /* Virt addr of TITAN */
1778 1781 /* pci config */
1779 1782 ddi_acc_handle_t sbus_pci_handle;
1780 1783
1781 1784 /* PCI BUS adapter management */
1782 1785 caddr_t pci_addr;
1783 1786 ddi_acc_handle_t pci_acc_handle;
1784 1787
1785 1788 uint32_t sli_mode;
1786 1789 #define EMLXS_HBA_SLI1_MODE 1
1787 1790 #define EMLXS_HBA_SLI2_MODE 2
1788 1791 #define EMLXS_HBA_SLI3_MODE 3
1789 1792 #define EMLXS_HBA_SLI4_MODE 4
1790 1793
1791 1794 /* SLI private data */
1792 1795 union {
1793 1796 emlxs_sli3_t sli3;
1794 1797 emlxs_sli4_t sli4;
1795 1798 } sli;
1796 1799
1797 1800 /* SLI API entry point routines */
1798 1801 emlxs_sli_api_t sli_api;
1799 1802
1800 1803 uint32_t io_poll_count; /* Number of poll commands */
1801 1804 /* in progress */
1802 1805
1803 1806 /* IO Completion management */
1804 1807 uint32_t iodone_count; /* Number of IO's on done Q */
1805 1808 /* Protected by EMLXS_PORT_LOCK */
1806 1809 emlxs_buf_t *iodone_list; /* fc_packet being deferred */
1807 1810 emlxs_buf_t *iodone_tail; /* fc_packet being deferred */
1808 1811 emlxs_thread_t iodone_thread;
1809 1812 emlxs_thread_t *spawn_thread_head;
1810 1813 emlxs_thread_t *spawn_thread_tail;
1811 1814 kmutex_t spawn_lock;
1812 1815 uint32_t spawn_open;
1813 1816
1814 1817 /* IO Channel management */
1815 1818 int32_t chan_count;
1816 1819 emlxs_channel_t chan[MAX_CHANNEL];
1817 1820 kmutex_t channel_tx_lock;
1818 1821 uint8_t channel_fcp; /* Default channel to use for FCP IO */
1819 1822 #define CHANNEL_FCT channel_fcp
1820 1823 uint8_t channel_ip; /* Default channel to use for IP IO */
1821 1824 uint8_t channel_els; /* Default channel to use for ELS IO */
1822 1825 uint8_t channel_ct; /* Default channel to use for CT IO */
1823 1826
1824 1827 /* IOTag management */
1825 1828 emlxs_buf_t **fc_table; /* sc_buf pointers indexed by */
1826 1829 /* iotag */
1827 1830 uint16_t fc_iotag; /* used to identify I/Os */
1828 1831 uint16_t fc_oor_iotag; /* OutOfRange (fc_table) iotags */
1829 1832 /* typically used for Abort/close */
1830 1833 #define EMLXS_MAX_ABORT_TAG 0x7fff
1831 1834 uint16_t max_iotag; /* ALL IOCBs except aborts */
1832 1835 kmutex_t iotag_lock;
1833 1836 uint32_t io_count; /* No of IO holding */
1834 1837 /* regular iotag */
1835 1838 uint32_t channel_tx_count; /* No of IO on tx Q */
1836 1839
1837 1840 /* Mailbox Management */
1838 1841 uint32_t mbox_queue_flag;
1839 1842 emlxs_queue_t mbox_queue;
1840 1843 void *mbox_mqe; /* active mbox mqe */
1841 1844 void *mbox_mbq; /* active MAILBOXQ */
1842 1845 kcondvar_t mbox_lock_cv; /* MBX_SLEEP */
1843 1846 kmutex_t mbox_lock; /* MBX_SLEEP */
1844 1847 uint32_t mbox_timer;
1845 1848
1846 1849 /* Interrupt management */
1847 1850 void *intr_arg;
1848 1851 uint32_t intr_unclaimed;
1849 1852 uint32_t intr_autoClear;
1850 1853 uint32_t intr_flags;
1851 1854 #define EMLXS_INTX_INITED 0x0001
1852 1855 #define EMLXS_INTX_ADDED 0x0002
1853 1856 #define EMLXS_MSI_ENABLED 0x0010
1854 1857 #define EMLXS_MSI_INITED 0x0020
1855 1858 #define EMLXS_MSI_ADDED 0x0040
1856 1859 #define EMLXS_INTR_INITED (EMLXS_INTX_INITED|EMLXS_MSI_INITED)
1857 1860 #define EMLXS_INTR_ADDED (EMLXS_INTX_ADDED|EMLXS_MSI_ADDED)
1858 1861
1859 1862 #ifdef MSI_SUPPORT
1860 1863 ddi_intr_handle_t *intr_htable;
1861 1864 uint32_t *intr_pri;
1862 1865 int32_t *intr_cap;
1863 1866 uint32_t intr_count;
1864 1867 uint32_t intr_type;
1865 1868 uint32_t intr_cond;
1866 1869 uint32_t intr_map[EMLXS_MSI_MAX_INTRS];
1867 1870 uint32_t intr_mask;
1868 1871
1869 1872 kmutex_t msiid_lock; /* for last_msiid */
1870 1873 int last_msiid;
1871 1874
1872 1875 kmutex_t intr_lock[EMLXS_MSI_MAX_INTRS];
1873 1876 int chan2msi[MAX_CHANNEL];
1874 1877 /* Index is the channel id */
1875 1878 int msi2chan[EMLXS_MSI_MAX_INTRS];
1876 1879 /* Index is the MSX-X msg id */
1877 1880 #endif /* MSI_SUPPORT */
1878 1881
1879 1882 uint32_t heartbeat_timer;
1880 1883 uint32_t heartbeat_flag;
1881 1884 uint32_t heartbeat_active;
1882 1885
1883 1886 /* IOCTL management */
1884 1887 kmutex_t ioctl_lock;
1885 1888 uint32_t ioctl_flags;
1886 1889 #define EMLXS_OPEN 0x00000001
1887 1890 #define EMLXS_OPEN_EXCLUSIVE 0x00000002
1888 1891
1889 1892 /* Timer management */
1890 1893 kcondvar_t timer_lock_cv;
1891 1894 kmutex_t timer_lock;
1892 1895 timeout_id_t timer_id;
1893 1896 uint32_t timer_tics;
1894 1897 uint32_t timer_flags;
1895 1898 #define EMLXS_TIMER_STARTED 0x0000001
1896 1899 #define EMLXS_TIMER_BUSY 0x0000002
1897 1900 #define EMLXS_TIMER_KILL 0x0000004
1898 1901 #define EMLXS_TIMER_ENDED 0x0000008
1899 1902
1900 1903 /* Misc Timers */
1901 1904 uint32_t linkup_timer;
1902 1905 uint32_t discovery_timer;
1903 1906 uint32_t pkt_timer;
1904 1907
1905 1908 /* Power Management */
1906 1909 uint32_t pm_state;
1907 1910 /* pm_state */
1908 1911 #define EMLXS_PM_IN_ATTACH 0x00000001
1909 1912 #define EMLXS_PM_IN_DETACH 0x00000002
1910 1913 #define EMLXS_PM_IN_SOL_CB 0x00000010
1911 1914 #define EMLXS_PM_IN_UNSOL_CB 0x00000020
1912 1915 #define EMLXS_PM_IN_LINK_RESET 0x00000100
1913 1916 #define EMLXS_PM_IN_HARD_RESET 0x00000200
1914 1917 #define EMLXS_PM_SUSPENDED 0x01000000
1915 1918
1916 1919 uint32_t pm_level;
1917 1920 /* pm_level */
1918 1921 #define EMLXS_PM_ADAPTER_DOWN 0
1919 1922 #define EMLXS_PM_ADAPTER_UP 1
1920 1923
1921 1924 uint32_t pm_busy;
1922 1925 kmutex_t pm_lock;
1923 1926 uint8_t pm_config[PCI_CONFIG_SIZE];
1924 1927 #ifdef IDLE_TIMER
1925 1928 uint32_t pm_idle_timer;
1926 1929 uint32_t pm_active; /* Only used by timer */
1927 1930 #endif /* IDLE_TIMER */
1928 1931
1929 1932 /* Loopback management */
1930 1933 uint32_t loopback_tics;
1931 1934 void *loopback_pkt;
1932 1935
1933 1936 /* Event management */
1934 1937 emlxs_event_queue_t event_queue;
1935 1938 uint32_t event_mask;
1936 1939 uint32_t event_timer;
1937 1940 emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS];
1938 1941 emlxs_hba_event_t hba_event;
1939 1942
1940 1943 /* Parameter management */
1941 1944 emlxs_config_t config[NUM_CFG_PARAM];
1942 1945
1943 1946 /* Driver stat management */
1944 1947 kstat_t *kstat;
1945 1948 emlxs_stats_t stats;
1946 1949
1947 1950 /* Log management */
1948 1951 emlxs_msg_log_t log;
1949 1952
1950 1953 /* Port managment */
1951 1954 uint32_t vpi_base;
1952 1955 uint32_t vpi_max;
1953 1956 uint32_t vpi_high;
1954 1957 uint32_t num_of_ports;
1955 1958
1956 1959 kmutex_t port_lock; /* locks port, nodes, rings */
1957 1960 emlxs_port_t port[MAX_VPORTS + 1]; /* port specific info */
1958 1961 /* Last one is for */
1959 1962 /* NPIV ready test */
1960 1963
1961 1964 #ifdef DHCHAP_SUPPORT
1962 1965 kmutex_t dhc_lock;
1963 1966 kmutex_t auth_lock;
1964 1967 emlxs_auth_cfg_t auth_cfg; /* Default auth_cfg. */
1965 1968 /* Points to list of entries. */
1966 1969 /* Protected by auth_lock */
1967 1970 uint32_t auth_cfg_count;
1968 1971 emlxs_auth_key_t auth_key; /* Default auth_key. */
1969 1972 /* Points to list of entries. */
1970 1973 /* Protected by auth_lock */
1971 1974 uint32_t auth_key_count;
1972 1975 uint32_t rdn_flag;
1973 1976 #endif /* DHCHAP_SUPPORT */
1974 1977
1975 1978 uint16_t ini_mode;
1976 1979 uint16_t tgt_mode;
1977 1980
1978 1981 #ifdef TEST_SUPPORT
1979 1982 uint32_t underrun_counter;
1980 1983 #endif /* TEST_SUPPORT */
1981 1984
1982 1985 #ifdef MODFW_SUPPORT
1983 1986 ddi_modhandle_t fw_modhandle;
1984 1987 #endif /* MODFW_SUPPORT */
1985 1988
1986 1989 #ifdef DUMP_SUPPORT
1987 1990 emlxs_file_t dump_txtfile;
1988 1991 emlxs_file_t dump_dmpfile;
1989 1992 emlxs_file_t dump_ceefile;
1990 1993 kmutex_t dump_lock;
1991 1994 #define EMLXS_DUMP_LOCK hba->dump_lock
1992 1995 #define EMLXS_TXT_FILE 1
1993 1996 #define EMLXS_DMP_FILE 2
1994 1997 #define EMLXS_CEE_FILE 3
1995 1998
1996 1999 #define EMLXS_DRV_DUMP 0
1997 2000 #define EMLXS_TEMP_DUMP 1
1998 2001 #define EMLXS_USER_DUMP 2
1999 2002
2000 2003 #endif /* DUMP_SUPPORT */
2001 2004
2002 2005 } emlxs_hba_t;
2003 2006
2004 2007 #define EMLXS_SLI_MAP_HDW (hba->sli_api.sli_map_hdw)
2005 2008 #define EMLXS_SLI_UNMAP_HDW (hba->sli_api.sli_unmap_hdw)
2006 2009 #define EMLXS_SLI_ONLINE (hba->sli_api.sli_online)
2007 2010 #define EMLXS_SLI_OFFLINE (hba->sli_api.sli_offline)
2008 2011 #define EMLXS_SLI_HBA_RESET (hba->sli_api.sli_hba_reset)
2009 2012 #define EMLXS_SLI_HBA_KILL (hba->sli_api.sli_hba_kill)
2010 2013 #define EMLXS_SLI_ISSUE_IOCB_CMD (hba->sli_api.sli_issue_iocb_cmd)
2011 2014 #define EMLXS_SLI_ISSUE_MBOX_CMD (hba->sli_api.sli_issue_mbox_cmd)
2012 2015 #define EMLXS_SLI_PREP_FCT_IOCB (hba->sli_api.sli_prep_fct_iocb)
2013 2016 #define EMLXS_SLI_PREP_FCP_IOCB (hba->sli_api.sli_prep_fcp_iocb)
2014 2017 #define EMLXS_SLI_PREP_IP_IOCB (hba->sli_api.sli_prep_ip_iocb)
2015 2018 #define EMLXS_SLI_PREP_ELS_IOCB (hba->sli_api.sli_prep_els_iocb)
2016 2019 #define EMLXS_SLI_PREP_CT_IOCB (hba->sli_api.sli_prep_ct_iocb)
2017 2020 #define EMLXS_SLI_POLL_INTR (hba->sli_api.sli_poll_intr)
2018 2021 #define EMLXS_SLI_INTX_INTR (hba->sli_api.sli_intx_intr)
2019 2022 #define EMLXS_SLI_MSI_INTR (hba->sli_api.sli_msi_intr)
2020 2023 #define EMLXS_SLI_DISABLE_INTR (hba->sli_api.sli_disable_intr)
2021 2024 #define EMLXS_SLI_TIMER (hba->sli_api.sli_timer)
2022 2025 #define EMLXS_SLI_POLL_ERRATT (hba->sli_api.sli_poll_erratt)
2023 2026
2024 2027 #define EMLXS_HBA_T 1 /* flag emlxs_hba_t is already typedefed */
2025 2028
2026 2029 #ifdef MSI_SUPPORT
2027 2030 #define EMLXS_INTR_INIT(_hba, _m) emlxs_msi_init(_hba, _m)
2028 2031 #define EMLXS_INTR_UNINIT(_hba) emlxs_msi_uninit(_hba)
2029 2032 #define EMLXS_INTR_ADD(_hba) emlxs_msi_add(_hba)
2030 2033 #define EMLXS_INTR_REMOVE(_hba) emlxs_msi_remove(_hba)
2031 2034 #else
2032 2035 #define EMLXS_INTR_INIT(_hba, _m) emlxs_intx_init(_hba, _m)
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2033 2036 #define EMLXS_INTR_UNINIT(_hba) emlxs_intx_uninit(_hba)
2034 2037 #define EMLXS_INTR_ADD(_hba) emlxs_intx_add(_hba)
2035 2038 #define EMLXS_INTR_REMOVE(_hba) emlxs_intx_remove(_hba)
2036 2039 #endif /* MSI_SUPPORT */
2037 2040
2038 2041
2039 2042 /* Power Management Component */
2040 2043 #define EMLXS_PM_ADAPTER 0
2041 2044
2042 2045
2043 -#define DRV_TIME (uint32_t)(ddi_get_time() - emlxs_device.drv_timestamp)
2046 +#define DRV_TIME (uint32_t)((gethrtime() - emlxs_device.drv_timestamp) / NANOSEC)
2044 2047
2045 2048 #define HBA port->hba
2046 2049 #define PPORT hba->port[0]
2047 2050 #define VPORT(x) hba->port[x]
2048 2051 #define EMLXS_TIMER_LOCK hba->timer_lock
2049 2052 #define VPD hba->vpd
2050 2053 #define CFG hba->config[0]
2051 2054 #define LOG hba->log
2052 2055 #define EVENTQ hba->event_queue
2053 2056 #define EMLXS_MBOX_LOCK hba->mbox_lock
2054 2057 #define EMLXS_MBOX_CV hba->mbox_lock_cv
2055 2058 #define EMLXS_LINKUP_LOCK hba->linkup_lock
2056 2059 #define EMLXS_LINKUP_CV hba->linkup_lock_cv
2057 2060 #define EMLXS_TX_CHANNEL_LOCK hba->channel_tx_lock /* ring txq lock */
2058 2061 #define EMLXS_MEMGET_LOCK hba->memget_lock /* mempool get lock */
2059 2062 #define EMLXS_MEMPUT_LOCK hba->memput_lock /* mempool put lock */
2060 2063 #define EMLXS_IOCTL_LOCK hba->ioctl_lock /* ioctl lock */
2061 2064 #define EMLXS_SPAWN_LOCK hba->spawn_lock /* spawn lock */
2062 2065 #define EMLXS_PM_LOCK hba->pm_lock /* pm lock */
2063 2066 #define HBASTATS hba->stats
2064 2067 #define EMLXS_CMD_RING_LOCK(n) hba->sli.sli3.ring_cmd_lock[n]
2065 2068
2066 2069 #define EMLXS_QUE_LOCK(n) hba->sli.sli4.que_lock[n]
2067 2070 #define EMLXS_MSIID_LOCK hba->msiid_lock
2068 2071
2069 2072 #define EMLXS_FCTAB_LOCK hba->iotag_lock
2070 2073
2071 2074 #define EMLXS_FCF_LOCK hba->sli.sli4.fcf_lock
2072 2075
2073 2076 #define EMLXS_PORT_LOCK hba->port_lock /* locks ports, */
2074 2077 /* nodes, rings */
2075 2078 #define EMLXS_INTR_LOCK(_id) hba->intr_lock[_id] /* locks intr threads */
2076 2079
2077 2080 #define EMLXS_PKT_LOCK port->pkt_lock /* used for pkt */
2078 2081 /* polling */
2079 2082 #define EMLXS_PKT_CV port->pkt_lock_cv /* Used for pkt */
2080 2083 /* polling */
2081 2084 #define EMLXS_UB_LOCK port->ub_lock /* locks unsolicited */
2082 2085 /* buffer pool */
2083 2086
2084 2087 /* These SWAPs will swap on any platform */
2085 2088 #define SWAP32_BUFFER(_b, _c) emlxs_swap32_buffer(_b, _c)
2086 2089 #define SWAP32_BCOPY(_s, _d, _c) emlxs_swap32_bcopy(_s, _d, _c)
2087 2090
2088 2091 #define SWAP64(_x) ((((uint64_t)(_x) & 0xFF)<<56) | \
2089 2092 (((uint64_t)(_x) & 0xFF00)<<40) | \
2090 2093 (((uint64_t)(_x) & 0xFF0000)<<24) | \
2091 2094 (((uint64_t)(_x) & 0xFF000000)<<8) | \
2092 2095 (((uint64_t)(_x) & 0xFF00000000)>>8) | \
2093 2096 (((uint64_t)(_x) & 0xFF0000000000)>>24) | \
2094 2097 (((uint64_t)(_x) & 0xFF000000000000)>>40) | \
2095 2098 (((uint64_t)(_x) & 0xFF00000000000000)>>56))
2096 2099
2097 2100 #define SWAP32(_x) ((((uint32_t)(_x) & 0xFF)<<24) | \
2098 2101 (((uint32_t)(_x) & 0xFF00)<<8) | \
2099 2102 (((uint32_t)(_x) & 0xFF0000)>>8) | \
2100 2103 (((uint32_t)(_x) & 0xFF000000)>>24))
2101 2104
2102 2105 #define SWAP16(_x) ((((uint16_t)(_x) & 0xFF)<<8) | \
2103 2106 (((uint16_t)(_x) & 0xFF00)>>8))
2104 2107
2105 2108 #define SWAP24_LO(_x) ((((uint32_t)(_x) & 0xFF)<<16) | \
2106 2109 ((uint32_t)(_x) & 0xFF00FF00) | \
2107 2110 (((uint32_t)(_x) & 0x00FF0000)>>16))
2108 2111
2109 2112 #define SWAP24_HI(_x) (((uint32_t)(_x) & 0x00FF00FF) | \
2110 2113 (((uint32_t)(_x) & 0x0000FF00)<<16) | \
2111 2114 (((uint32_t)(_x) & 0xFF000000)>>16))
2112 2115
2113 2116 /* These LE_SWAPs will only swap on a LE platform */
2114 2117 #ifdef EMLXS_LITTLE_ENDIAN
2115 2118 #define LE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c)
2116 2119 #define LE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c)
2117 2120 #define LE_SWAP64(_x) SWAP64(_x)
2118 2121 #define LE_SWAP32(_x) SWAP32(_x)
2119 2122 #define LE_SWAP16(_x) SWAP16(_x)
2120 2123 #define LE_SWAP24_LO(_x) SWAP24_LO(X)
2121 2124 #define LE_SWAP24_HI(_x) SWAP24_HI(X)
2122 2125
2123 2126 #if (EMLXS_MODREVX == EMLXS_MODREV2X)
2124 2127 #undef LE_SWAP24_LO
2125 2128 #define LE_SWAP24_LO(_x) (_x)
2126 2129 #undef LE_SWAP24_HI
2127 2130 #define LE_SWAP24_HI(_x) (_x)
2128 2131 #endif /* EMLXS_MODREV2X */
2129 2132
2130 2133 #else /* BIG ENDIAN */
2131 2134 #define LE_SWAP32_BUFFER(_b, _c)
2132 2135 #define LE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c)
2133 2136 #define LE_SWAP64(_x) (_x)
2134 2137 #define LE_SWAP32(_x) (_x)
2135 2138 #define LE_SWAP16(_x) (_x)
2136 2139 #define LE_SWAP24_LO(_x) (_x)
2137 2140 #define LE_SWAP24_HI(_x) (_x)
2138 2141 #endif /* EMLXS_LITTLE_ENDIAN */
2139 2142
2140 2143 /* These BE_SWAPs will only swap on a BE platform */
2141 2144 #ifdef EMLXS_BIG_ENDIAN
2142 2145 #define BE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c)
2143 2146 #define BE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c)
2144 2147 #define BE_SWAP64(_x) SWAP64(_x)
2145 2148 #define BE_SWAP32(_x) SWAP32(_x)
2146 2149 #define BE_SWAP16(_x) SWAP16(_x)
2147 2150 #else /* LITTLE ENDIAN */
2148 2151 #define BE_SWAP32_BUFFER(_b, _c)
2149 2152 #define BE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c)
2150 2153 #define BE_SWAP64(_x) (_x)
2151 2154 #define BE_SWAP32(_x) (_x)
2152 2155 #define BE_SWAP16(_x) (_x)
2153 2156 #endif /* EMLXS_BIG_ENDIAN */
2154 2157
2155 2158 #ifdef __cplusplus
2156 2159 }
2157 2160 #endif
2158 2161
2159 2162 #endif /* _EMLXS_FC_H */
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