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5045 use atomic_{inc,dec}_* instead of atomic_add_*
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--- old/usr/src/uts/i86pc/io/psm/uppc.c
+++ new/usr/src/uts/i86pc/io/psm/uppc.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26 #define PSMI_1_7
27 27
28 28 #include <sys/mutex.h>
29 29 #include <sys/types.h>
30 30 #include <sys/time.h>
31 31 #include <sys/machlock.h>
32 32 #include <sys/smp_impldefs.h>
33 33 #include <sys/uadmin.h>
34 34 #include <sys/promif.h>
35 35 #include <sys/psm.h>
36 36 #include <sys/pit.h>
37 37 #include <sys/apic.h>
38 38 #include <sys/psm_common.h>
39 39 #include <sys/atomic.h>
40 40 #include <sys/archsystm.h>
41 41
42 42 #define NSEC_IN_SEC 1000000000
43 43
44 44 /*
45 45 * Local Function Prototypes
46 46 */
47 47 static void uppc_softinit(void);
48 48 static void uppc_picinit();
49 49 static int uppc_post_cpu_start(void);
50 50 static int uppc_clkinit(int);
51 51 static int uppc_addspl(int irqno, int ipl, int min_ipl, int max_ipl);
52 52 static int uppc_delspl(int irqno, int ipl, int min_ipl, int max_ipl);
53 53 static processorid_t uppc_get_next_processorid(processorid_t cpu_id);
54 54 static int uppc_get_clockirq(int ipl);
55 55 static int uppc_probe(void);
56 56 static int uppc_translate_irq(dev_info_t *dip, int irqno);
57 57 static void uppc_shutdown(int cmd, int fcn);
58 58 static void uppc_preshutdown(int cmd, int fcn);
59 59 static int uppc_state(psm_state_request_t *request);
60 60 static int uppc_init_acpi(void);
61 61 static void uppc_setspl(int);
62 62 static int uppc_intr_enter(int, int *);
63 63 static void uppc_intr_exit(int, int);
64 64 static hrtime_t uppc_gethrtime();
65 65
66 66 static int uppc_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
67 67 int *pci_irqp, iflag_t *intr_flagp);
68 68
69 69 /*
70 70 * Global Data
71 71 */
72 72 static struct standard_pic pics0;
73 73 int uppc_use_acpi = 1; /* Use ACPI by default */
74 74 int uppc_enable_acpi = 0;
75 75
76 76
77 77 /*
78 78 * For interrupt link devices, if uppc_unconditional_srs is set, an irq resource
79 79 * will be assigned (via _SRS). If it is not set, use the current
80 80 * irq setting (via _CRS), but only if that irq is in the set of possible
81 81 * irqs (returned by _PRS) for the device.
82 82 */
83 83 int uppc_unconditional_srs = 1;
84 84
85 85 /*
86 86 * For interrupt link devices, if uppc_prefer_crs is set when we are
87 87 * assigning an IRQ resource to a device, prefer the current IRQ setting
88 88 * over other possible irq settings under same conditions.
89 89 */
90 90 int uppc_prefer_crs = 1;
91 91
92 92 int uppc_verbose = 0;
93 93
94 94 /* flag definitions for uppc_verbose */
95 95 #define UPPC_VERBOSE_IRQ_FLAG 0x00000001
96 96 #define UPPC_VERBOSE_POWEROFF_FLAG 0x00000002
97 97 #define UPPC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000004
98 98
99 99
100 100 #define UPPC_VERBOSE_IRQ(fmt) \
101 101 if (uppc_verbose & UPPC_VERBOSE_IRQ_FLAG) \
102 102 cmn_err fmt;
103 103
104 104 #define UPPC_VERBOSE_POWEROFF(fmt) \
105 105 if (uppc_verbose & UPPC_VERBOSE_POWEROFF_FLAG) \
106 106 prom_printf fmt;
107 107
108 108 uchar_t uppc_reserved_irqlist[MAX_ISA_IRQ + 1];
109 109
110 110 static uint16_t uppc_irq_shared_table[MAX_ISA_IRQ + 1];
111 111
112 112 /*
113 113 * Contains SCI irqno from FADT after initialization
114 114 */
115 115 static int uppc_sci = -1;
116 116
117 117 /*
118 118 * Local Static Data
119 119 */
120 120
121 121 static lock_t uppc_gethrtime_lock;
122 122 static hrtime_t uppc_lasthrtime;
123 123
124 124
125 125 #ifdef UPPC_DEBUG
126 126 #define DENT 0x0001
127 127
128 128 static int uppc_debug = 0;
129 129
130 130
131 131 #endif
132 132
133 133
134 134 static struct psm_ops uppc_ops = {
135 135 uppc_probe, /* psm_probe */
136 136
137 137 uppc_softinit, /* psm_init */
138 138 uppc_picinit, /* psm_picinit */
139 139 uppc_intr_enter, /* psm_intr_enter */
140 140 uppc_intr_exit, /* psm_intr_exit */
141 141 uppc_setspl, /* psm_setspl */
142 142 uppc_addspl, /* psm_addspl */
143 143 uppc_delspl, /* psm_delspl */
144 144 (int (*)(processorid_t))NULL, /* psm_disable_intr */
145 145 (void (*)(processorid_t))NULL, /* psm_enable_intr */
146 146 (int (*)(int))NULL, /* psm_softlvl_to_irq */
147 147 (void (*)(int))NULL, /* psm_set_softintr */
148 148 (void (*)(processorid_t))NULL, /* psm_set_idlecpu */
149 149 (void (*)(processorid_t))NULL, /* psm_unset_idlecpu */
150 150
151 151 uppc_clkinit, /* psm_clkinit */
152 152 uppc_get_clockirq, /* psm_get_clockirq */
153 153 (void (*)(void))NULL, /* psm_hrtimeinit */
154 154 uppc_gethrtime, /* psm_gethrtime */
155 155
156 156 uppc_get_next_processorid, /* psm_get_next_processorid */
157 157 (int (*)(processorid_t, caddr_t))NULL, /* psm_cpu_start */
158 158 uppc_post_cpu_start, /* psm_post_cpu_start */
159 159 uppc_shutdown, /* psm_shutdown */
160 160 (int (*)(int, int))NULL, /* psm_get_ipivect */
161 161 (void (*)(processorid_t, int))NULL, /* psm_send_ipi */
162 162
163 163 uppc_translate_irq, /* psm_translate_irq */
164 164
165 165 (void (*)(int, char *))NULL, /* psm_notify_error */
166 166 (void (*)(int msg))NULL, /* psm_notify_func */
167 167 (void (*)(hrtime_t time))NULL, /* psm_timer_reprogram */
168 168 (void (*)(void))NULL, /* psm_timer_enable */
169 169 (void (*)(void))NULL, /* psm_timer_disable */
170 170 (void (*)(void *arg))NULL, /* psm_post_cyclic_setup */
171 171 uppc_preshutdown, /* psm_preshutdown */
172 172
173 173 (int (*)(dev_info_t *, ddi_intr_handle_impl_t *,
174 174 psm_intr_op_t, int *))NULL, /* psm_intr_ops */
175 175
176 176 uppc_state, /* psm_state */
177 177 (int (*)(psm_cpu_request_t *))NULL /* psm_cpu_ops */
178 178 };
179 179
180 180
181 181 static struct psm_info uppc_info = {
182 182 PSM_INFO_VER01_7, /* version */
183 183 PSM_OWN_SYS_DEFAULT, /* ownership */
184 184 (struct psm_ops *)&uppc_ops, /* operation */
185 185 "uppc", /* machine name */
186 186 "UniProcessor PC", /* machine descriptions */
187 187 };
188 188
189 189 /*
190 190 * Configuration Data
191 191 */
192 192
193 193 /*
194 194 * This is the loadable module wrapper.
195 195 */
196 196 #include <sys/modctl.h>
197 197
198 198 static void *uppc_hdlp;
199 199
200 200 int
201 201 _init(void)
202 202 {
203 203 return (psm_mod_init(&uppc_hdlp, &uppc_info));
204 204 }
205 205
206 206 int
207 207 _fini(void)
208 208 {
209 209 return (psm_mod_fini(&uppc_hdlp, &uppc_info));
210 210 }
211 211
212 212 int
213 213 _info(struct modinfo *modinfop)
214 214 {
215 215 return (psm_mod_info(&uppc_hdlp, &uppc_info, modinfop));
216 216 }
217 217
218 218 /*
219 219 * Autoconfiguration Routines
220 220 */
221 221
222 222 static int
223 223 uppc_probe(void)
224 224 {
225 225
226 226
227 227 return (PSM_SUCCESS);
228 228 }
229 229
230 230 static void
231 231 uppc_softinit(void)
232 232 {
233 233 struct standard_pic *pp;
234 234 int i;
235 235
236 236 pp = &pics0;
237 237
238 238
239 239 if (uppc_use_acpi && uppc_init_acpi()) {
240 240 build_reserved_irqlist((uchar_t *)uppc_reserved_irqlist);
241 241 for (i = 0; i <= MAX_ISA_IRQ; i++)
242 242 uppc_irq_shared_table[i] = 0;
243 243 uppc_enable_acpi = 1;
244 244 }
245 245
246 246 /*
247 247 * initialize the ipl mask
248 248 */
249 249 for (i = 0; i < (MAXIPL << 1); i += 2) {
250 250 /* enable slave lines on master */
251 251 pp->c_iplmask[i] = 0xff;
252 252 pp->c_iplmask[i+1] = (0xff & ~(1 << MASTERLINE));
253 253 }
254 254 }
255 255
256 256 /*ARGSUSED*/
257 257 static int
258 258 uppc_clkinit(int hertz)
259 259 {
260 260 ulong_t clkticks = PIT_HZ / hz;
261 261
262 262 if (hertz == 0)
263 263 return (0); /* One shot mode not supported */
264 264
265 265 /*
266 266 * program timer 0
267 267 */
268 268 outb(PITCTL_PORT, (PIT_C0|PIT_NDIVMODE|PIT_READMODE));
269 269 outb(PITCTR0_PORT, (uchar_t)clkticks);
270 270 outb(PITCTR0_PORT, (uchar_t)(clkticks>>8));
271 271
272 272 return (NSEC_IN_SEC / hertz);
273 273 }
274 274
275 275 static void
276 276 uppc_picinit()
277 277 {
278 278 picsetup();
279 279
280 280 /*
281 281 * If a valid SCI is present, manually addspl()
282 282 * since we're not set-up early enough in boot
283 283 * to do it "conventionally" (via add_avintr)
284 284 */
285 285 if (uppc_sci >= 0)
286 286 (void) uppc_addspl(uppc_sci, SCI_IPL, SCI_IPL, SCI_IPL);
287 287 }
288 288
289 289 static int
290 290 uppc_post_cpu_start(void)
291 291 {
292 292 /*
293 293 * On uppc machines psm_post_cpu_start is called during S3 resume
294 294 * on the boot cpu from assembly, using the ap_mlsetup vector.
295 295 */
296 296
297 297 /*
298 298 * Init master and slave pic
299 299 */
300 300 picsetup();
301 301
302 302 /*
303 303 * program timer 0
304 304 */
305 305 (void) uppc_clkinit(hz);
306 306
307 307 return (PSM_SUCCESS);
308 308 }
309 309
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310 310 /*ARGSUSED3*/
311 311 static int
312 312 uppc_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
313 313 {
314 314 struct standard_pic *pp;
315 315 int i;
316 316 int startidx;
317 317 uchar_t vectmask;
318 318
319 319 if (irqno <= MAX_ISA_IRQ)
320 - atomic_add_16(&uppc_irq_shared_table[irqno], 1);
320 + atomic_inc_16(&uppc_irq_shared_table[irqno]);
321 321
322 322 if (ipl != min_ipl)
323 323 return (0);
324 324
325 325 if (irqno > 7) {
326 326 vectmask = 1 << (irqno - 8);
327 327 startidx = (ipl << 1);
328 328 } else {
329 329 vectmask = 1 << irqno;
330 330 startidx = (ipl << 1) + 1;
331 331 }
332 332
333 333 /*
334 334 * mask intr same or above ipl
335 335 * level MAXIPL has all intr off as init. default
336 336 */
337 337 pp = &pics0;
338 338 for (i = startidx; i < (MAXIPL << 1); i += 2) {
339 339 if (pp->c_iplmask[i] & vectmask)
340 340 break;
341 341 pp->c_iplmask[i] |= vectmask;
342 342 }
343 343
344 344 /*
345 345 * unmask intr below ipl
346 346 */
347 347 for (i = startidx-2; i >= 0; i -= 2) {
348 348 if (!(pp->c_iplmask[i] & vectmask))
349 349 break;
350 350 pp->c_iplmask[i] &= ~vectmask;
351 351 }
352 352 return (0);
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353 353 }
354 354
355 355 static int
356 356 uppc_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
357 357 {
358 358 struct standard_pic *pp;
359 359 int i;
360 360 uchar_t vectmask;
361 361
362 362 if (irqno <= MAX_ISA_IRQ)
363 - atomic_add_16(&uppc_irq_shared_table[irqno], -1);
363 + atomic_dec_16(&uppc_irq_shared_table[irqno]);
364 364
365 365 /*
366 366 * skip if we are not deleting the last handler
367 367 * and the ipl is higher than minimum
368 368 */
369 369 if ((max_ipl != PSM_INVALID_IPL) && (ipl >= min_ipl))
370 370 return (0);
371 371
372 372 if (irqno > 7) {
373 373 vectmask = 1 << (irqno - 8);
374 374 i = 0;
375 375 } else {
376 376 vectmask = 1 << irqno;
377 377 i = 1;
378 378 }
379 379
380 380 pp = &pics0;
381 381
382 382 /*
383 383 * check any handlers left for this irqno
384 384 */
385 385 if (max_ipl != PSM_INVALID_IPL) {
386 386 /*
387 387 * unmasks all levels below the lowest priority
388 388 */
389 389 i += ((min_ipl - 1) << 1);
390 390 for (; i >= 0; i -= 2) {
391 391 if (!(pp->c_iplmask[i] & vectmask))
392 392 break;
393 393 pp->c_iplmask[i] &= ~vectmask;
394 394 }
395 395 } else {
396 396 /*
397 397 * set mask to all levels
398 398 */
399 399 for (; i < (MAXIPL << 1); i += 2) {
400 400 if (pp->c_iplmask[i] & vectmask)
401 401 break;
402 402 pp->c_iplmask[i] |= vectmask;
403 403 }
404 404 }
405 405 return (0);
406 406 }
407 407
408 408 static processorid_t
409 409 uppc_get_next_processorid(processorid_t cpu_id)
410 410 {
411 411 if (cpu_id == -1)
412 412 return (0);
413 413 return (-1);
414 414 }
415 415
416 416 /*ARGSUSED*/
417 417 static int
418 418 uppc_get_clockirq(int ipl)
419 419 {
420 420 return (CLOCK_VECTOR);
421 421 }
422 422
423 423
424 424 static int
425 425 uppc_init_acpi(void)
426 426 {
427 427 int verboseflags = 0;
428 428 int sci;
429 429 iflag_t sci_flags;
430 430
431 431 /*
432 432 * Process SCI configuration here; this may return
433 433 * an error if acpi-user-options has specified
434 434 * legacy mode (use ACPI without ACPI mode or SCI)
435 435 */
436 436 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
437 437 sci = -1;
438 438
439 439 /*
440 440 * Initialize sub-system - if error is returns, ACPI is not
441 441 * used.
442 442 */
443 443 if (acpica_init() != AE_OK)
444 444 return (0);
445 445
446 446 /*
447 447 * uppc implies system is in PIC mode; set edge/level
448 448 * via ELCR based on return value from get_sci; this
449 449 * will default to level/low if no override present,
450 450 * as recommended by Intel ACPI CA team.
451 451 */
452 452 if (sci >= 0) {
453 453 ASSERT((sci_flags.intr_el == INTR_EL_LEVEL) ||
454 454 (sci_flags.intr_el == INTR_EL_EDGE));
455 455
456 456 psm_set_elcr(sci, sci_flags.intr_el == INTR_EL_LEVEL);
457 457 }
458 458
459 459 /*
460 460 * Remember SCI for later use
461 461 */
462 462 uppc_sci = sci;
463 463
464 464 if (uppc_verbose & UPPC_VERBOSE_IRQ_FLAG)
465 465 verboseflags |= PSM_VERBOSE_IRQ_FLAG;
466 466
467 467 if (uppc_verbose & UPPC_VERBOSE_POWEROFF_FLAG)
468 468 verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
469 469
470 470 if (uppc_verbose & UPPC_VERBOSE_POWEROFF_PAUSE_FLAG)
471 471 verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
472 472
473 473 if (acpi_psm_init(uppc_info.p_mach_idstring, verboseflags) ==
474 474 ACPI_PSM_FAILURE) {
475 475 return (0);
476 476 }
477 477
478 478 return (1);
479 479 }
480 480
481 481
482 482 static void
483 483 uppc_preshutdown(int cmd, int fcn)
484 484 {
485 485 UPPC_VERBOSE_POWEROFF(("uppc_preshutdown(%d,%d);\n", cmd, fcn));
486 486
487 487 }
488 488
489 489 static void
490 490 uppc_shutdown(int cmd, int fcn)
491 491 {
492 492 UPPC_VERBOSE_POWEROFF(("uppc_shutdown(%d,%d);\n", cmd, fcn));
493 493
494 494 /*
495 495 * Return if passed a command other than A_SHUTDOWN or
496 496 * if we're not using ACPI.
497 497 */
498 498 if ((cmd != A_SHUTDOWN) || (!uppc_enable_acpi))
499 499 return;
500 500
501 501 /*
502 502 * Switch system back into Legacy-Mode if using ACPI and
503 503 * not powering-off. Some BIOSes need to remain in ACPI-mode
504 504 * for power-off to succeed (Dell Dimension 4600)
505 505 */
506 506 if (fcn != AD_POWEROFF) {
507 507 (void) AcpiDisable();
508 508 return;
509 509 }
510 510
511 511 (void) acpi_poweroff();
512 512 }
513 513
514 514
515 515 static int
516 516 uppc_acpi_enter_picmode(void)
517 517 {
518 518 ACPI_OBJECT_LIST arglist;
519 519 ACPI_OBJECT arg;
520 520 ACPI_STATUS status;
521 521
522 522 /* Setup parameter object */
523 523 arglist.Count = 1;
524 524 arglist.Pointer = &arg;
525 525 arg.Type = ACPI_TYPE_INTEGER;
526 526 arg.Integer.Value = ACPI_PIC_MODE;
527 527
528 528 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
529 529 if (ACPI_FAILURE(status))
530 530 return (PSM_FAILURE);
531 531 else
532 532 return (PSM_SUCCESS);
533 533 }
534 534
535 535
536 536 struct pic_state {
537 537 int8_t mmask;
538 538 int8_t smask;
539 539 uint16_t elcr;
540 540 };
541 541
542 542
543 543 static void
544 544 pic_save_state(struct pic_state *sp)
545 545 {
546 546 struct standard_pic *pp;
547 547 int vecno;
548 548
549 549 /*
550 550 * Only the PIC masks and the ELCR can be saved;
551 551 * other 8259 state is write-only
552 552 */
553 553
554 554 /*
555 555 * save current master and slave interrupt mask
556 556 */
557 557 pp = &pics0;
558 558 sp->smask = pp->c_curmask[0];
559 559 sp->mmask = pp->c_curmask[1];
560 560
561 561 /*
562 562 * save edge/level configuration for isa interrupts
563 563 */
564 564 sp->elcr = 0;
565 565 for (vecno = 0; vecno <= MAX_ISA_IRQ; vecno++)
566 566 sp->elcr |= psm_get_elcr(vecno) << vecno;
567 567 }
568 568
569 569 static void
570 570 pic_restore_state(struct pic_state *sp)
571 571 {
572 572 int vecno;
573 573
574 574 /* Restore master and slave interrupt masks */
575 575 outb(SIMR_PORT, sp->smask);
576 576 outb(MIMR_PORT, sp->mmask);
577 577
578 578 /* Read master to allow pics to settle */
579 579 (void) inb(MIMR_PORT);
580 580
581 581 /* Restore edge/level configuration for isa interupts */
582 582 for (vecno = 0; vecno <= MAX_ISA_IRQ; vecno++)
583 583 psm_set_elcr(vecno, sp->elcr & (1 << vecno));
584 584
585 585 /* Reenter PIC mode before restoring LNK devices */
586 586 (void) uppc_acpi_enter_picmode();
587 587
588 588 /* Restore ACPI link device mappings */
589 589 acpi_restore_link_devices();
590 590 }
591 591
592 592 static int
593 593 uppc_state(psm_state_request_t *rp)
594 594 {
595 595 switch (rp->psr_cmd) {
596 596 case PSM_STATE_ALLOC:
597 597 rp->req.psm_state_req.psr_state =
598 598 kmem_zalloc(sizeof (struct pic_state), KM_NOSLEEP);
599 599 if (rp->req.psm_state_req.psr_state == NULL)
600 600 return (ENOMEM);
601 601 rp->req.psm_state_req.psr_state_size =
602 602 sizeof (struct pic_state);
603 603 return (0);
604 604 case PSM_STATE_FREE:
605 605 kmem_free(rp->req.psm_state_req.psr_state,
606 606 rp->req.psm_state_req.psr_state_size);
607 607 return (0);
608 608 case PSM_STATE_SAVE:
609 609 pic_save_state(rp->req.psm_state_req.psr_state);
610 610 return (0);
611 611 case PSM_STATE_RESTORE:
612 612 pic_restore_state(rp->req.psm_state_req.psr_state);
613 613 return (0);
614 614 default:
615 615 return (EINVAL);
616 616 }
617 617 }
618 618
619 619
620 620 static int
621 621 uppc_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
622 622 int ipin, int *pci_irqp, iflag_t *intr_flagp)
623 623 {
624 624 int status;
625 625 acpi_psm_lnk_t acpipsmlnk;
626 626
627 627 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
628 628 intr_flagp)) == ACPI_PSM_SUCCESS) {
629 629 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Found irqno %d "
630 630 "from cache for device %s, instance #%d\n", *pci_irqp,
631 631 ddi_get_name(dip), ddi_get_instance(dip)));
632 632 return (status);
633 633 }
634 634
635 635 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
636 636
637 637 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp,
638 638 intr_flagp, &acpipsmlnk)) == ACPI_PSM_FAILURE) {
639 639 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: "
640 640 " acpi_translate_pci_irq failed for device %s, instance"
641 641 " #%d\n", ddi_get_name(dip), ddi_get_instance(dip)));
642 642
643 643 return (status);
644 644 }
645 645
646 646 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
647 647 status = uppc_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
648 648 intr_flagp);
649 649 if (status != ACPI_PSM_SUCCESS) {
650 650 status = acpi_get_current_irq_resource(&acpipsmlnk,
651 651 pci_irqp, intr_flagp);
652 652 }
653 653 }
654 654
655 655 if (status == ACPI_PSM_SUCCESS) {
656 656 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
657 657 intr_flagp, &acpipsmlnk);
658 658 psm_set_elcr(*pci_irqp, 1); /* set IRQ to PCI mode */
659 659
660 660 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: [ACPI] "
661 661 "new irq %d for device %s, instance #%d\n",
662 662 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
663 663 }
664 664
665 665 return (status);
666 666 }
667 667
668 668 /*
669 669 * Configures the irq for the interrupt link device identified by
670 670 * acpipsmlnkp.
671 671 *
672 672 * Gets the current and the list of possible irq settings for the
673 673 * device. If uppc_unconditional_srs is not set, and the current
674 674 * resource setting is in the list of possible irq settings,
675 675 * current irq resource setting is passed to the caller.
676 676 *
677 677 * Otherwise, picks an irq number from the list of possible irq
678 678 * settings, and sets the irq of the device to this value.
679 679 * If prefer_crs is set, among a set of irq numbers in the list that have
680 680 * the least number of devices sharing the interrupt, we pick current irq
681 681 * resource setting if it is a member of this set.
682 682 *
683 683 * Passes the irq number in the value pointed to by pci_irqp, and
684 684 * polarity and sensitivity in the structure pointed to by dipintrflagp
685 685 * to the caller.
686 686 *
687 687 * Note that if setting the irq resource failed, but successfuly obtained
688 688 * the current irq resource settings, passes the current irq resources
689 689 * and considers it a success.
690 690 *
691 691 * Returns:
692 692 * ACPI_PSM_SUCCESS on success.
693 693 *
694 694 * ACPI_PSM_FAILURE if an error occured during the configuration or
695 695 * if a suitable irq was not found for this device, or if setting the
696 696 * irq resource and obtaining the current resource fails.
697 697 *
698 698 */
699 699 static int
700 700 uppc_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
701 701 int *pci_irqp, iflag_t *dipintr_flagp)
702 702 {
703 703 int i, min_share, foundnow, done = 0;
704 704 int32_t irq;
705 705 int32_t share_irq = -1;
706 706 int32_t chosen_irq = -1;
707 707 int cur_irq = -1;
708 708 acpi_irqlist_t *irqlistp;
709 709 acpi_irqlist_t *irqlistent;
710 710
711 711 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
712 712 == ACPI_PSM_FAILURE) {
713 713 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: Unable to determine "
714 714 "or assign IRQ for device %s, instance #%d: The system was "
715 715 "unable to get the list of potential IRQs from ACPI.",
716 716 ddi_get_name(dip), ddi_get_instance(dip)));
717 717
718 718 return (ACPI_PSM_FAILURE);
719 719 }
720 720
721 721 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
722 722 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!uppc_unconditional_srs) &&
723 723 (cur_irq > 0)) {
724 724
725 725 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
726 726 == ACPI_PSM_SUCCESS) {
727 727
728 728 acpi_free_irqlist(irqlistp);
729 729 ASSERT(pci_irqp != NULL);
730 730 *pci_irqp = cur_irq;
731 731 return (ACPI_PSM_SUCCESS);
732 732 }
733 733 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: Could not find the "
734 734 "current irq %d for device %s, instance #%d in ACPI's "
735 735 "list of possible irqs for this device. Picking one from "
736 736 " the latter list.", cur_irq, ddi_get_name(dip),
737 737 ddi_get_instance(dip)));
738 738
739 739 }
740 740
741 741 irqlistent = irqlistp;
742 742 min_share = 255;
743 743
744 744 while (irqlistent != NULL) {
745 745
746 746 for (foundnow = 0, i = 0; i < irqlistent->num_irqs; i++) {
747 747
748 748 irq = irqlistp->irqs[i];
749 749
750 750 if ((irq > MAX_ISA_IRQ) ||
751 751 (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) ||
752 752 (irq == 0))
753 753 continue;
754 754
755 755 if (uppc_reserved_irqlist[irq])
756 756 continue;
757 757
758 758 if (uppc_irq_shared_table[irq] == 0) {
759 759 chosen_irq = irq;
760 760 foundnow = 1;
761 761 if (!(uppc_prefer_crs) || (irq == cur_irq)) {
762 762 done = 1;
763 763 break;
764 764 }
765 765 }
766 766
767 767 if ((uppc_irq_shared_table[irq] < min_share) ||
768 768 ((uppc_irq_shared_table[irq] == min_share) &&
769 769 (cur_irq == irq) && (uppc_prefer_crs))) {
770 770 min_share = uppc_irq_shared_table[irq];
771 771 share_irq = irq;
772 772 foundnow = 1;
773 773 }
774 774 }
775 775
776 776 /* If we found an IRQ in the inner loop, save the details */
777 777 if (foundnow && ((chosen_irq != -1) || (share_irq != -1))) {
778 778 /*
779 779 * Copy the acpi_prs_private_t and flags from this
780 780 * irq list entry, since we found an irq from this
781 781 * entry.
782 782 */
783 783 acpipsmlnkp->acpi_prs_prv = irqlistent->acpi_prs_prv;
784 784 *dipintr_flagp = irqlistent->intr_flags;
785 785 }
786 786
787 787 if (done)
788 788 break;
789 789
790 790 /* Load the next entry in the irqlist */
791 791 irqlistent = irqlistent->next;
792 792 }
793 793
794 794 acpi_free_irqlist(irqlistp);
795 795
796 796 if (chosen_irq != -1)
797 797 irq = chosen_irq;
798 798 else if (share_irq != -1)
799 799 irq = share_irq;
800 800 else {
801 801 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Could not find a "
802 802 "suitable irq from the list of possible irqs for device "
803 803 "%s, instance #%d in ACPI's list of possible\n",
804 804 ddi_get_name(dip), ddi_get_instance(dip)));
805 805
806 806 return (ACPI_PSM_FAILURE);
807 807 }
808 808
809 809
810 810 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Setting irq %d for device %s "
811 811 "instance #%d\n", irq, ddi_get_name(dip), ddi_get_instance(dip)));
812 812
813 813 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) == ACPI_PSM_SUCCESS) {
814 814 /*
815 815 * setting irq was successful, check to make sure CRS
816 816 * reflects that. If CRS does not agree with what we
817 817 * set, return the irq that was set.
818 818 */
819 819
820 820 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
821 821 dipintr_flagp) == ACPI_PSM_SUCCESS) {
822 822
823 823 if (cur_irq != irq)
824 824 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: "
825 825 "IRQ resource set (irqno %d) for device %s "
826 826 "instance #%d, differs from current "
827 827 "setting irqno %d",
828 828 irq, ddi_get_name(dip),
829 829 ddi_get_instance(dip), cur_irq));
830 830 }
831 831 /*
832 832 * return the irq that was set, and not what CRS reports,
833 833 * since CRS has been seen to be bogus on some systems
834 834 */
835 835 cur_irq = irq;
836 836 } else {
837 837 UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: set resource irq %d "
838 838 "failed for device %s instance #%d",
839 839 irq, ddi_get_name(dip), ddi_get_instance(dip)));
840 840 if (cur_irq == -1)
841 841 return (ACPI_PSM_FAILURE);
842 842 }
843 843
844 844 ASSERT(pci_irqp != NULL);
845 845 *pci_irqp = cur_irq;
846 846 return (ACPI_PSM_SUCCESS);
847 847 }
848 848
849 849
850 850 /*ARGSUSED*/
851 851 static int
852 852 uppc_translate_irq(dev_info_t *dip, int irqno)
853 853 {
854 854 char dev_type[16];
855 855 int dev_len, pci_irq, devid, busid;
856 856 ddi_acc_handle_t cfg_handle;
857 857 uchar_t ipin, iline;
858 858 iflag_t intr_flag;
859 859
860 860 if (dip == NULL) {
861 861 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: irqno = %d"
862 862 " dip = NULL\n", irqno));
863 863 return (irqno);
864 864 }
865 865
866 866 if (!uppc_enable_acpi) {
867 867 return (irqno);
868 868 }
869 869
870 870 dev_len = sizeof (dev_type);
871 871 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
872 872 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
873 873 &dev_len) != DDI_PROP_SUCCESS) {
874 874 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: irqno %d"
875 875 "device %s instance %d no device_type\n", irqno,
876 876 ddi_get_name(dip), ddi_get_instance(dip)));
877 877 return (irqno);
878 878 }
879 879
880 880 if ((strcmp(dev_type, "pci") == 0) ||
881 881 (strcmp(dev_type, "pciex") == 0)) {
882 882
883 883 /* pci device */
884 884 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
885 885 return (irqno);
886 886
887 887 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
888 888 return (irqno);
889 889
890 890 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
891 891 iline = pci_config_get8(cfg_handle, PCI_CONF_ILINE);
892 892 if (uppc_acpi_translate_pci_irq(dip, busid, devid,
893 893 ipin, &pci_irq, &intr_flag) == ACPI_PSM_SUCCESS) {
894 894
895 895 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: [ACPI] new irq "
896 896 "%d old irq %d device %s, instance %d\n", pci_irq,
897 897 irqno, ddi_get_name(dip), ddi_get_instance(dip)));
898 898
899 899 /*
900 900 * Make sure pci_irq is within range.
901 901 * Otherwise, fall through and return irqno.
902 902 */
903 903 if (pci_irq <= MAX_ISA_IRQ) {
904 904 if (iline != pci_irq) {
905 905 /*
906 906 * Update the device's ILINE byte,
907 907 * in case uppc_acpi_translate_pci_irq
908 908 * has choosen a different pci_irq
909 909 * than the BIOS has configured.
910 910 * Some chipsets use the value in
911 911 * ILINE to control interrupt routing,
912 912 * in conflict with the PCI spec.
913 913 */
914 914 pci_config_put8(cfg_handle,
915 915 PCI_CONF_ILINE, pci_irq);
916 916 }
917 917 pci_config_teardown(&cfg_handle);
918 918 return (pci_irq);
919 919 }
920 920 }
921 921 pci_config_teardown(&cfg_handle);
922 922
923 923 /* FALLTHRU to common case - returning irqno */
924 924 } else {
925 925 /* non-PCI; assumes ISA-style edge-triggered */
926 926 psm_set_elcr(irqno, 0); /* set IRQ to ISA mode */
927 927
928 928 UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: non-pci,"
929 929 "irqno %d device %s instance %d\n", irqno,
930 930 ddi_get_name(dip), ddi_get_instance(dip)));
931 931 }
932 932
933 933 return (irqno);
934 934 }
935 935
936 936 /*
937 937 * uppc_intr_enter() raises the ipl to the level of the current interrupt,
938 938 * and sends EOI to the pics.
939 939 * If interrupt is 7 or 15 and not spurious interrupt, send specific EOI
940 940 * else send non-specific EOI
941 941 * uppc_intr_enter() returns the new priority level,
942 942 * or -1 for spurious interrupt
943 943 */
944 944 static int
945 945 uppc_intr_enter(int ipl, int *vector)
946 946 {
947 947 int newipl;
948 948 int intno;
949 949
950 950 intno = (*vector);
951 951
952 952 ASSERT(intno < 256);
953 953
954 954 newipl = autovect[intno].avh_hi_pri;
955 955
956 956 /*
957 957 * During wait_till_seen() periods when interrupt vector is being
958 958 * removed in remove_av(), the removed hardware interrupt could
959 959 * trigger and got here with newipl 0. It has to send EOI
960 960 * as usual but no need to call setspl and returns -1 like spurious.
961 961 */
962 962 if ((intno & 7) != 7) {
963 963 if (newipl)
964 964 uppc_setspl(newipl);
965 965 outb(MCMD_PORT, PIC_NSEOI);
966 966 if (intno >= 8) {
967 967 outb(SCMD_PORT, PIC_NSEOI);
968 968 }
969 969 } else { /* int was 7 or 15 */
970 970 if (newipl && newipl <= ipl) { /* Check for spurious int */
971 971 if (intno != 7)
972 972 outb(MCMD_PORT, PIC_NSEOI);
973 973 return (-1); /* Spurious int */
974 974 } else {
975 975 if (newipl)
976 976 uppc_setspl(newipl);
977 977 if (intno != 7) {
978 978 outb(MCMD_PORT, PIC_NSEOI);
979 979 outb(SCMD_PORT, PIC_SEOI_LVL7);
980 980 } else {
981 981 outb(MCMD_PORT, PIC_SEOI_LVL7);
982 982 }
983 983 }
984 984 }
985 985
986 986 if (newipl)
987 987 return (newipl);
988 988 else
989 989 return (-1); /* not real spurious int */
990 990 }
991 991
992 992 /*
993 993 * uppc_intr_exit() restores the old interrupt
994 994 * priority level after processing an interrupt.
995 995 * It is called with interrupts disabled, and does not enable interrupts.
996 996 */
997 997 /* ARGSUSED */
998 998 static void
999 999 uppc_intr_exit(int ipl, int vector)
1000 1000 {
1001 1001 uppc_setspl(ipl);
1002 1002 }
1003 1003
1004 1004 /*
1005 1005 * uppc_setspl() loads new interrupt masks into the pics
1006 1006 * based on input ipl.
1007 1007 */
1008 1008 /* ARGSUSED */
1009 1009 static void
1010 1010 uppc_setspl(int ipl)
1011 1011 {
1012 1012 struct standard_pic *pp;
1013 1013 uint8_t smask, mmask;
1014 1014 uint8_t cursmask, curmmask;
1015 1015
1016 1016 pp = &pics0;
1017 1017 smask = pp->c_iplmask[ipl * 2];
1018 1018 mmask = pp->c_iplmask[ipl * 2 + 1];
1019 1019 cursmask = pp->c_curmask[0];
1020 1020 curmmask = pp->c_curmask[1];
1021 1021 if (cursmask == smask && curmmask == mmask)
1022 1022 return;
1023 1023 pp->c_curmask[0] = smask;
1024 1024 pp->c_curmask[1] = mmask;
1025 1025
1026 1026 if (cursmask != smask) {
1027 1027 /*
1028 1028 * program new slave pic mask
1029 1029 */
1030 1030 outb(SIMR_PORT, smask);
1031 1031 }
1032 1032 if (curmmask != mmask) {
1033 1033 /*
1034 1034 * program new master pic mask
1035 1035 */
1036 1036 outb(MIMR_PORT, mmask);
1037 1037 }
1038 1038 /*
1039 1039 * read master to allow pics to settle
1040 1040 */
1041 1041 (void) inb(MIMR_PORT);
1042 1042 }
1043 1043
1044 1044 /*
1045 1045 * uppc_gethrtime() returns high resolution timer value
1046 1046 */
1047 1047 static hrtime_t
1048 1048 uppc_gethrtime()
1049 1049 {
1050 1050 hrtime_t timeval, temp;
1051 1051 unsigned int ctr0;
1052 1052 ulong_t oflags;
1053 1053
1054 1054 oflags = intr_clear(); /* disable ints */
1055 1055 lock_set(&uppc_gethrtime_lock);
1056 1056 retry:
1057 1057 temp = hrtime_base;
1058 1058 outb(PITCTL_PORT, 0); /* latch counter 0 */
1059 1059 /*
1060 1060 * read counter 0
1061 1061 */
1062 1062 ctr0 = inb(PITCTR0_PORT);
1063 1063 ctr0 |= inb(PITCTR0_PORT) << 8;
1064 1064 timeval = (hrtime_t)ctr0 * (NANOSEC / PIT_HZ);
1065 1065 if (temp != hrtime_base)
1066 1066 goto retry;
1067 1067 timeval -= temp;
1068 1068 if (timeval < uppc_lasthrtime)
1069 1069 timeval = uppc_lasthrtime;
1070 1070 uppc_lasthrtime = timeval;
1071 1071 lock_clear(&uppc_gethrtime_lock);
1072 1072 intr_restore(oflags);
1073 1073 return (timeval);
1074 1074 }
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