Print this page
5253 kmem_alloc/kmem_zalloc won't fail with KM_SLEEP
5254 getrbuf won't fail with KM_SLEEP
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_flash.c
+++ new/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_flash.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2010 QLogic Corporation. All rights reserved.
24 24 */
25 25
26 26 #include <qlge.h>
27 27 /*
28 28 * Local Function Prototypes.
29 29 */
30 30 static int ql_read_flash(qlge_t *, uint32_t, uint32_t *);
31 31 static int ql_write_flash(qlge_t *, uint32_t, uint32_t);
32 32 static int ql_protect_flash(qlge_t *);
33 33 static int ql_unprotect_flash(qlge_t *);
34 34
35 35 /*
36 36 * ql_flash_id
37 37 * The flash memory chip exports 3 ID bytes in the order of manufacturer, id,
38 38 * capability
39 39 */
40 40 int
41 41 ql_flash_id(qlge_t *qlge)
42 42 {
43 43 int rval;
44 44 uint32_t fdata = 0;
45 45
46 46 /*
47 47 * Send Restore command (0xAB) to release Flash from
48 48 * possible deep power down state
49 49 */
50 50 rval = ql_read_flash(qlge, FLASH_CONF_ADDR | 0x300 | FLASH_RES_CMD,
51 51 &fdata);
52 52 QL_PRINT(DBG_FLASH, ("%s(%d) flash electronic signature is %x \n",
53 53 __func__, qlge->instance, fdata));
54 54 fdata = 0;
55 55
56 56 /* 0x9F */
57 57 rval = ql_read_flash(qlge, FLASH_CONF_ADDR | 0x0400 | FLASH_RDID_CMD,
58 58 &fdata);
59 59
60 60 if ((rval != DDI_SUCCESS) || (fdata == 0)) {
61 61 cmn_err(CE_WARN, "%s(%d) read_flash failed 0x%x.",
62 62 __func__, qlge->instance, fdata);
63 63 } else {
64 64 qlge->flash_info.flash_manuf = LSB(LSW(fdata));
65 65 qlge->flash_info.flash_id = MSB(LSW(fdata));
66 66 qlge->flash_info.flash_cap = LSB(MSW(fdata));
67 67 QL_PRINT(DBG_FLASH, ("%s(%d) flash manufacturer 0x%x,"
68 68 " flash id 0x%x, flash cap 0x%x\n",
69 69 __func__, qlge->instance,
70 70 qlge->flash_info.flash_manuf, qlge->flash_info.flash_id,
71 71 qlge->flash_info.flash_cap));
72 72 }
73 73 return (rval);
74 74 }
75 75
76 76 /*
77 77 * qlge_dump_fcode
78 78 * Dumps fcode from flash.
79 79 */
80 80 int
81 81 qlge_dump_fcode(qlge_t *qlge, uint8_t *dp, uint32_t size, uint32_t startpos)
82 82 {
83 83 uint32_t cnt, data, addr;
84 84 int rval = DDI_SUCCESS;
85 85
86 86 QL_PRINT(DBG_FLASH, ("%s(%d) entered to read address %x, %x bytes\n",
87 87 __func__, qlge->instance, startpos, size));
88 88
89 89 /* make sure startpos+size doesn't exceed flash */
90 90 if (size + startpos > qlge->fdesc.flash_size) {
91 91 cmn_err(CE_WARN, "%s(%d) exceeded flash range, sz=%xh, stp=%xh,"
92 92 " flsz=%xh", __func__, qlge->instance,
93 93 size, startpos, qlge->fdesc.flash_size);
94 94 return (DDI_FAILURE);
95 95 }
96 96
97 97 /* check start addr is 32 bit or 4 byte aligned for M25Pxx */
98 98 if ((startpos & 0x3) != 0) {
99 99 cmn_err(CE_WARN, "%s(%d) incorrect buffer size alignment",
100 100 __func__, qlge->instance);
101 101 return (DDI_FAILURE);
102 102 }
103 103
104 104 /* adjust flash start addr for 32 bit words */
105 105 addr = startpos / 4;
106 106
107 107 /* Read fcode data from flash. */
108 108 cnt = startpos;
109 109 size += startpos;
110 110 while (cnt < size) {
111 111 /* Allow other system activity. */
112 112 if (cnt % 0x1000 == 0) {
113 113 drv_usecwait(1);
114 114 }
115 115 rval = ql_read_flash(qlge, addr++, &data);
116 116 if (rval != DDI_SUCCESS) {
117 117 break;
118 118 }
119 119 *dp++ = LSB(LSW(data));
120 120 *dp++ = MSB(LSW(data));
121 121 *dp++ = LSB(MSW(data));
122 122 *dp++ = MSB(MSW(data));
123 123 cnt += 4;
124 124 }
125 125
126 126 if (rval != DDI_SUCCESS) {
127 127 cmn_err(CE_WARN, "failed, rval = %xh", rval);
128 128 }
129 129 return (rval);
130 130 }
131 131
132 132 int
133 133 ql_erase_and_write_to_flash(qlge_t *qlge, uint8_t *dp, uint32_t size,
134 134 uint32_t faddr)
135 135 {
136 136 int rval = DDI_FAILURE;
137 137 uint32_t cnt, rest_addr, fdata;
138 138
139 139 QL_PRINT(DBG_FLASH, ("%s(%d) entered to write addr %x, %d bytes\n",
140 140 __func__, qlge->instance, faddr, size));
141 141
142 142 /* start address must be 32 bit word aligned */
143 143 if ((faddr & 0x3) != 0) {
144 144 cmn_err(CE_WARN, "%s(%d) incorrect buffer size alignment",
145 145 __func__, qlge->instance);
146 146 return (DDI_FAILURE);
147 147 }
148 148
149 149 /* setup mask of address range within a sector */
150 150 rest_addr = (qlge->fdesc.block_size - 1) >> 2;
151 151
152 152 faddr = faddr >> 2; /* flash gets 32 bit words */
153 153
154 154 /*
155 155 * Write data to flash.
156 156 */
157 157 cnt = 0;
158 158 size = (size + 3) >> 2; /* Round up & convert to dwords */
159 159 while (cnt < size) {
160 160 /* Beginning of a sector? do a sector erase */
161 161 if ((faddr & rest_addr) == 0) {
162 162 fdata = (faddr & ~rest_addr) << 2;
163 163 fdata = (fdata & 0xff00) |
164 164 (fdata << 16 & 0xff0000) |
165 165 (fdata >> 16 & 0xff);
166 166 /* 64k bytes sector erase */
167 167 rval = ql_write_flash(qlge, /* 0xd8 */
168 168 FLASH_CONF_ADDR | 0x0300 | qlge->fdesc.erase_cmd,
169 169 fdata);
170 170
171 171 if (rval != DDI_SUCCESS) {
172 172 cmn_err(CE_WARN, "Unable to flash sector: "
173 173 "address=%xh", faddr);
174 174 goto out;
175 175 }
176 176 }
177 177 /* Write data */
178 178 fdata = *dp++;
179 179 fdata |= *dp++ << 8;
180 180 fdata |= *dp++ << 16;
181 181 fdata |= *dp++ << 24;
182 182
183 183 rval = ql_write_flash(qlge, faddr, fdata);
184 184 if (rval != DDI_SUCCESS) {
185 185 cmn_err(CE_WARN, "Unable to program flash "
186 186 "address=%xh data=%xh", faddr,
187 187 *dp);
188 188 goto out;
189 189 }
190 190 cnt++;
191 191 faddr++;
192 192
193 193 /* Allow other system activity. */
194 194 if (cnt % 0x1000 == 0) {
195 195 qlge_delay(10000);
196 196 }
197 197 }
198 198 rval = DDI_SUCCESS;
199 199 out:
200 200 if (rval != DDI_SUCCESS) {
201 201 cmn_err(CE_WARN, "%s(%d failed=%xh",
202 202 __func__, qlge->instance, rval);
203 203 }
204 204 return (rval);
205 205 }
206 206
207 207 void
208 208 get_sector_number(qlge_t *qlge, uint32_t faddr, uint32_t *psector)
209 209 {
210 210 *psector = faddr / qlge->fdesc.block_size; /* 0x10000 */
211 211 }
212 212
213 213 /*
214 214 * qlge_load_flash
215 215 * Write "size" bytes from memory "dp" to flash address "faddr".
216 216 * faddr = 32bit word flash address.
217 217 */
218 218 int
219 219 qlge_load_flash(qlge_t *qlge, uint8_t *dp, uint32_t len, uint32_t faddr)
220 220 {
221 221 int rval = DDI_FAILURE;
222 222 uint32_t start_block, end_block;
223 223 uint32_t start_byte, end_byte;
224 224 uint32_t num;
225 225 uint32_t sector_size, addr_src, addr_desc;
226 226 uint8_t *temp;
227 227 caddr_t bp, bdesc;
228 228
229 229 QL_PRINT(DBG_FLASH, ("%s(%d) entered to write addr %x, %d bytes\n",
230 230 __func__, qlge->instance, faddr, len));
231 231
232 232 sector_size = qlge->fdesc.block_size;
233 233
↓ open down ↓ |
233 lines elided |
↑ open up ↑ |
234 234 if (faddr > qlge->fdesc.flash_size) {
235 235 cmn_err(CE_WARN, "%s(%d): invalid flash write address %x",
236 236 __func__, qlge->instance, faddr);
237 237 return (DDI_FAILURE);
238 238 }
239 239 /* Get semaphore to access Flash Address and Flash Data Registers */
240 240 if (ql_sem_spinlock(qlge, QL_FLASH_SEM_MASK) != DDI_SUCCESS) {
241 241 return (DDI_FAILURE);
242 242 }
243 243 temp = kmem_zalloc(sector_size, KM_SLEEP);
244 - if (temp == NULL) {
245 - cmn_err(CE_WARN, "%s(%d): Unable to allocate buffer",
246 - __func__, qlge->instance);
247 - ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
248 - return (DDI_FAILURE);
249 - }
250 244
251 245 (void) ql_unprotect_flash(qlge);
252 246
253 247 get_sector_number(qlge, faddr, &start_block);
254 248 get_sector_number(qlge, faddr + len - 1, &end_block);
255 249
256 250 QL_PRINT(DBG_FLASH, ("%s(%d) start_block %x, end_block %x\n",
257 251 __func__, qlge->instance, start_block, end_block));
258 252
259 253 for (num = start_block; num <= end_block; num++) {
260 254 QL_PRINT(DBG_FLASH,
261 255 ("%s(%d) sector_size 0x%x, sector read addr %x\n",
262 256 __func__, qlge->instance, sector_size, num * sector_size));
263 257 /* read one whole sector flash data to buffer */
264 258 rval = qlge_dump_fcode(qlge, (uint8_t *)temp, sector_size,
265 259 num * sector_size);
266 260
267 261 start_byte = num * sector_size;
268 262 end_byte = start_byte + sector_size -1;
269 263 if (start_byte < faddr)
270 264 start_byte = faddr;
271 265 if (end_byte > (faddr + len))
272 266 end_byte = (faddr + len - 1);
273 267
274 268 addr_src = start_byte - faddr;
275 269 addr_desc = start_byte - num * sector_size;
276 270 bp = (caddr_t)dp + addr_src;
277 271 bdesc = (caddr_t)temp + addr_desc;
278 272 bcopy(bp, bdesc, (end_byte - start_byte + 1));
279 273
280 274 /* write the whole sector data to flash */
281 275 if (ql_erase_and_write_to_flash(qlge, temp, sector_size,
282 276 num * sector_size) != DDI_SUCCESS)
283 277 goto out;
284 278 }
285 279 rval = DDI_SUCCESS;
286 280 out:
287 281 (void) ql_protect_flash(qlge);
288 282 kmem_free(temp, sector_size);
289 283
290 284 ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
291 285
292 286 if (rval != DDI_SUCCESS) {
293 287 cmn_err(CE_WARN, "%s(%d failed=%xh",
294 288 __func__, qlge->instance, rval);
295 289 }
296 290
297 291 return (rval);
298 292 }
299 293
300 294
301 295 /*
302 296 * ql_check_pci
303 297 * checks the passed buffer for a valid pci signature and
304 298 * expected (and in range) pci length values.
305 299 * On successful pci check, nextpos adjusted to next pci header.
306 300 */
307 301 static int
308 302 ql_check_pci(qlge_t *qlge, uint8_t *buf, uint32_t *nextpos)
309 303 {
310 304 pci_header_t *pcih;
311 305 pci_data_t *pcid;
312 306 uint32_t doff;
313 307 uint8_t *pciinfo;
314 308 uint32_t image_size = 0;
315 309 int rval = CONTINUE_SEARCH;
316 310
317 311 QL_PRINT(DBG_FLASH, ("%s(%d) check image at 0x%x\n",
318 312 __func__, qlge->instance, *nextpos));
319 313
320 314 if (buf != NULL) {
321 315 pciinfo = buf;
322 316 } else {
323 317 cmn_err(CE_WARN, "%s(%d) failed, null buf ptr passed",
324 318 __func__, qlge->instance);
325 319 return (STOP_SEARCH);
326 320 }
327 321
328 322 /* get the pci header image length */
329 323 pcih = (pci_header_t *)pciinfo;
330 324
331 325 doff = pcih->dataoffset[1];
332 326 doff <<= 8;
333 327 doff |= pcih->dataoffset[0];
334 328
335 329 /* some header section sanity check */
336 330 if (pcih->signature[0] != PCI_HEADER0 /* '55' */ ||
337 331 pcih->signature[1] != PCI_HEADER1 /* 'AA' */ || doff > 50) {
338 332 cmn_err(CE_WARN, "%s(%d) image format error: s0=%xh, s1=%xh,"
339 333 "off=%xh\n", __func__, qlge->instance,
340 334 pcih->signature[0], pcih->signature[1], doff);
341 335 return (STOP_SEARCH);
342 336 }
343 337
344 338 pcid = (pci_data_t *)(pciinfo + doff);
345 339
346 340 /* a slight sanity data section check */
347 341 if (pcid->signature[0] != 'P' || pcid->signature[1] != 'C' ||
348 342 pcid->signature[2] != 'I' || pcid->signature[3] != 'R') {
349 343 cmn_err(CE_WARN, "%s(%d) failed, data sig mismatch!",
350 344 __func__, qlge->instance);
351 345 return (STOP_SEARCH);
352 346 }
353 347 image_size =
354 348 (pcid->imagelength[0] | (pcid->imagelength[1] << 8))*
355 349 PCI_SECTOR_SIZE /* 512 */;
356 350
357 351 switch (pcid->codetype) {
358 352 case PCI_CODE_X86PC:
359 353 QL_PRINT(DBG_FLASH, ("%s(%d) boot image is FTYPE_BIOS \n",
360 354 __func__, qlge->instance));
361 355 break;
362 356 case PCI_CODE_FCODE:
363 357 QL_PRINT(DBG_FLASH, ("%s(%d) boot image is FTYPE_FCODE \n",
364 358 __func__, qlge->instance));
365 359 break;
366 360 case PCI_CODE_EFI:
367 361 QL_PRINT(DBG_FLASH, ("%s(%d) boot image is FTYPE_EFI \n",
368 362 __func__, qlge->instance));
369 363 break;
370 364 case PCI_CODE_HPPA:
371 365 QL_PRINT(DBG_FLASH, ("%s(%d) boot image is PCI_CODE_HPPA \n",
372 366 __func__, qlge->instance));
373 367 break;
374 368 default:
375 369 QL_PRINT(DBG_FLASH, ("%s(%d) boot image is FTYPE_UNKNOWN \n",
376 370 __func__, qlge->instance));
377 371 break;
378 372 }
379 373
380 374 QL_PRINT(DBG_FLASH, ("%s(%d) image size %x at %x\n",
381 375 __func__, qlge->instance, image_size, *nextpos));
382 376
383 377 if (pcid->indicator == PCI_IND_LAST_IMAGE) {
384 378 QL_PRINT(DBG_FLASH, ("%s(%d) last boot image found \n",
385 379 __func__, qlge->instance));
386 380 rval = LAST_IMAGE_FOUND;
387 381 } else {
388 382 rval = CONTINUE_SEARCH;
389 383 }
390 384 /* Get the next flash image address */
391 385 *nextpos += image_size;
392 386
393 387 return (rval);
394 388 }
395 389
396 390 /*
397 391 * ql_find_flash_layout_table_data_structure
398 392 * Find Flash Layout Table Data Structure (FLTDS) that
399 393 * is located at the end of last boot image.
400 394 * Assume FLTDS is located with first 2M bytes.
401 395 * Note:
402 396 * Driver must be in stalled state prior to entering or
403 397 * add code to this function prior to calling ql_setup_flash()
404 398 */
405 399 int
406 400 ql_find_flash_layout_table_data_structure_addr(qlge_t *qlge)
407 401 {
408 402 int rval = DDI_FAILURE;
409 403 int result = CONTINUE_SEARCH;
410 404 uint32_t freadpos = 0;
411 405 uint8_t buf[FBUFSIZE];
412 406
413 407 if (qlge->flash_fltds_addr != 0) {
414 408 QL_PRINT(DBG_FLASH, ("%s(%d) done already\n",
415 409 __func__, qlge->instance));
416 410 return (DDI_SUCCESS);
417 411 }
418 412 /*
419 413 * Temporarily set the fdesc.flash_size to
420 414 * 1M flash size to avoid failing of ql_dump_focde.
421 415 */
422 416 qlge->fdesc.flash_size = FLASH_FIRMWARE_IMAGE_ADDR;
423 417
424 418 while (result == CONTINUE_SEARCH) {
425 419
426 420 if ((rval = qlge_dump_fcode(qlge, buf, FBUFSIZE, freadpos))
427 421 != DDI_SUCCESS) {
428 422 cmn_err(CE_WARN, "%s(%d) qlge_dump_fcode failed"
429 423 " pos=%xh rval=%xh",
430 424 __func__, qlge->instance, freadpos, rval);
431 425 break;
432 426 }
433 427 /*
434 428 * checkout the pci boot image format
435 429 * and get next read address
436 430 */
437 431 result = ql_check_pci(qlge, buf, &freadpos);
438 432 /*
439 433 * find last image? If so, then the freadpos
440 434 * is the address of FLTDS
441 435 */
442 436 if (result == LAST_IMAGE_FOUND) {
443 437 QL_PRINT(DBG_FLASH,
444 438 ("%s(%d) flash layout table data structure "
445 439 "(FLTDS) address is at %x \n", __func__,
446 440 qlge->instance, freadpos));
447 441 qlge->flash_fltds_addr = freadpos;
448 442 rval = DDI_SUCCESS;
449 443 break;
450 444 } else if (result == STOP_SEARCH) {
451 445 cmn_err(CE_WARN, "%s(%d) flash header incorrect,"
452 446 "stop searching",
453 447 __func__, qlge->instance);
454 448 break;
455 449 }
456 450 }
457 451 return (rval);
458 452 }
459 453
460 454 /*
461 455 * ql_flash_fltds
462 456 * Get flash layout table data structure table.
463 457 */
464 458 static int
465 459 ql_flash_fltds(qlge_t *qlge)
466 460 {
467 461 uint32_t cnt;
468 462 uint16_t chksum, *bp, data;
469 463 int rval;
470 464
471 465 rval = qlge_dump_fcode(qlge, (uint8_t *)&qlge->fltds,
472 466 sizeof (ql_fltds_t), qlge->flash_fltds_addr);
473 467 if (rval != DDI_SUCCESS) {
474 468 cmn_err(CE_WARN, "%s(%d)read error",
475 469 __func__, qlge->instance);
476 470 bzero(&qlge->fltds, sizeof (ql_fltds_t));
477 471 return (rval);
478 472 }
479 473
480 474 QL_DUMP(DBG_FLASH, "flash layout table data structure:\n",
481 475 &qlge->fltds, 8, sizeof (ql_fltds_t));
482 476
483 477 chksum = 0;
484 478 data = 0;
485 479 bp = (uint16_t *)&qlge->fltds;
486 480 for (cnt = 0; cnt < (sizeof (ql_fltds_t)) / 2; cnt++) {
487 481 data = *bp;
488 482 LITTLE_ENDIAN_16(&data);
489 483 chksum += data;
490 484 bp++;
491 485 }
492 486
493 487 LITTLE_ENDIAN_32(&qlge->fltds.signature);
494 488 LITTLE_ENDIAN_16(&qlge->fltds.flt_addr_lo);
495 489 LITTLE_ENDIAN_16(&qlge->fltds.flt_addr_hi);
496 490 LITTLE_ENDIAN_16(&qlge->fltds.checksum);
497 491
498 492 QL_PRINT(DBG_FLASH, ("%s(%d) signature %xh\n",
499 493 __func__, qlge->instance, qlge->fltds.signature));
500 494 QL_PRINT(DBG_FLASH, ("%s(%d) flt_addr_lo %xh\n",
501 495 __func__, qlge->instance, qlge->fltds.flt_addr_lo));
502 496 QL_PRINT(DBG_FLASH, ("%s(%d) flt_addr_hi %xh\n",
503 497 __func__, qlge->instance, qlge->fltds.flt_addr_hi));
504 498 QL_PRINT(DBG_FLASH, ("%s(%d) version %xh\n",
505 499 __func__, qlge->instance, qlge->fltds.version));
506 500 QL_PRINT(DBG_FLASH, ("%s(%d) checksum %xh\n",
507 501 __func__, qlge->instance, qlge->fltds.checksum));
508 502 /* QFLT */
509 503 if (chksum != 0 || qlge->fltds.signature != FLASH_FLTDS_SIGNATURE) {
510 504 cmn_err(CE_WARN, "%s(%d) invalid flash layout table data"
511 505 " structure", __func__, qlge->instance);
512 506 bzero(&qlge->fltds, sizeof (ql_fltds_t));
513 507 return (DDI_FAILURE);
514 508 }
515 509 return (DDI_SUCCESS);
516 510 }
517 511
518 512 /*
519 513 * ql_flash_flt
520 514 * Get flash layout table.
521 515 */
522 516 int
523 517 ql_flash_flt(qlge_t *qlge)
524 518 {
525 519 uint32_t addr, cnt;
526 520 int rval = DDI_FAILURE;
527 521 ql_flt_entry_t *entry;
528 522 uint8_t region;
529 523
530 524 addr = qlge->fltds.flt_addr_hi;
531 525 addr <<= 16;
532 526 addr |= qlge->fltds.flt_addr_lo;
533 527
534 528 /* first read flt header to know how long the table is */
535 529 rval = qlge_dump_fcode(qlge, (uint8_t *)&qlge->flt.header,
536 530 sizeof (ql_flt_header_t), addr);
537 531 if (rval != DDI_SUCCESS) {
538 532 cmn_err(CE_WARN, "%s(%d) read flt header at %x error",
539 533 __func__, qlge->instance, addr);
540 534 bzero(&qlge->flt, sizeof (ql_flt_header_t));
541 535 return (rval);
542 536 }
543 537
544 538 LITTLE_ENDIAN_16(&qlge->flt.header.version);
545 539 LITTLE_ENDIAN_16(&qlge->flt.header.length);
546 540 LITTLE_ENDIAN_16(&qlge->flt.header.checksum);
547 541 LITTLE_ENDIAN_16(&qlge->flt.header.reserved);
548 542
549 543 if ((qlge->flt.header.version != 1) &&
550 544 (qlge->flt.header.version != 0)) {
551 545 cmn_err(CE_WARN, "%s(%d) flt header version %x unsupported",
552 546 __func__, qlge->instance, qlge->flt.header.version);
553 547 bzero(&qlge->flt, sizeof (ql_flt_header_t));
554 548 return (DDI_FAILURE);
555 549 }
556 550 /* 2.allocate memory to save all flt table entries */
557 551 if ((qlge->flt.ql_flt_entry_ptr = (ql_flt_entry_t *)
558 552 (kmem_zalloc(qlge->flt.header.length, KM_SLEEP))) == NULL) {
559 553 cmn_err(CE_WARN, "%s(%d) flt table alloc failed",
560 554 __func__, qlge->instance);
561 555 goto err;
562 556 }
563 557 /* how many tables? */
564 558 qlge->flt.num_entries = (uint16_t)(qlge->flt.header.length /
565 559 sizeof (ql_flt_entry_t));
566 560
567 561 /* 3. read the rest of flt table */
568 562 addr += (uint32_t)sizeof (ql_flt_header_t);
569 563 QL_PRINT(DBG_FLASH, ("%s(%d) flt has %x entries \n",
570 564 __func__, qlge->instance, qlge->flt.num_entries));
571 565 rval = qlge_dump_fcode(qlge,
572 566 (uint8_t *)qlge->flt.ql_flt_entry_ptr, qlge->flt.header.length,
573 567 addr);
574 568 if (rval != DDI_SUCCESS) {
575 569 cmn_err(CE_WARN, "read flt table entry error");
576 570 goto err;
577 571 }
578 572
579 573 entry = (ql_flt_entry_t *)qlge->flt.ql_flt_entry_ptr;
580 574 for (cnt = 0; cnt < qlge->flt.num_entries; cnt++) {
581 575 LITTLE_ENDIAN_32(&entry->size);
582 576 LITTLE_ENDIAN_32(&entry->begin_addr);
583 577 LITTLE_ENDIAN_32(&entry->end_addr);
584 578 entry++;
585 579 }
586 580 /* TO Do :4. Checksum verification */
587 581
588 582 /* 5.search index of Flash Descriptor Table in the Flash Layout Table */
589 583 entry = (ql_flt_entry_t *)qlge->flt.ql_flt_entry_ptr;
590 584 qlge->flash_fdt_addr = 0;
591 585 for (cnt = 0; cnt < qlge->flt.num_entries; cnt++) {
592 586 if (entry->region == FLT_REGION_FDT) {
593 587 qlge->flash_flt_fdt_index = cnt;
594 588 qlge->flash_fdt_addr = entry->begin_addr;
595 589 qlge->flash_fdt_size = entry->size;
596 590 QL_PRINT(DBG_FLASH, ("%s(%d) flash_flt_fdt_index is"
597 591 " %x, addr %x,size %x \n", __func__,
598 592 qlge->instance,
599 593 cnt, entry->begin_addr, entry->size));
600 594 break;
601 595 }
602 596 entry++;
603 597 }
604 598
605 599 if (qlge->flash_fdt_addr == 0) {
606 600 cmn_err(CE_WARN, "%s(%d) flash descriptor table not found",
607 601 __func__, qlge->instance);
608 602 goto err;
609 603 }
610 604 /* 6.search index of Nic Config. Table in the Flash Layout Table */
611 605 entry = (ql_flt_entry_t *)qlge->flt.ql_flt_entry_ptr;
612 606 if (qlge->func_number == qlge->fn0_net)
613 607 region = FLT_REGION_NIC_PARAM0;
614 608 else
615 609 region = FLT_REGION_NIC_PARAM1;
616 610 qlge->flash_nic_config_table_addr = 0;
617 611 for (cnt = 0; cnt < qlge->flt.num_entries; cnt++) {
618 612 if (entry->region == region) {
619 613 qlge->flash_flt_nic_config_table_index = cnt;
620 614 qlge->flash_nic_config_table_addr = entry->begin_addr;
621 615 qlge->flash_nic_config_table_size = entry->size;
622 616 QL_PRINT(DBG_FLASH, ("%s(%d) "
623 617 "flash_flt_nic_config_table_index "
624 618 "is %x, address %x, size %x \n",
625 619 __func__, qlge->instance,
626 620 cnt, entry->begin_addr, entry->size));
627 621 break;
628 622 }
629 623 entry++;
630 624 }
631 625 if (qlge->flash_nic_config_table_addr == 0) {
632 626 cmn_err(CE_WARN, "%s(%d) NIC Configuration Table not found",
633 627 __func__, qlge->instance);
634 628 goto err;
635 629 }
636 630
637 631 return (DDI_SUCCESS);
638 632 err:
639 633 bzero(&qlge->flt, sizeof (ql_flt_header_t));
640 634 if (qlge->flt.ql_flt_entry_ptr != NULL) {
641 635 bzero(&qlge->flt.ql_flt_entry_ptr, qlge->flt.header.length);
642 636 kmem_free(qlge->flt.ql_flt_entry_ptr, qlge->flt.header.length);
643 637 qlge->flt.ql_flt_entry_ptr = NULL;
644 638 }
645 639 cmn_err(CE_WARN, "%s(%d) read FLT failed", __func__, qlge->instance);
646 640 return (DDI_FAILURE);
647 641 }
648 642
649 643 /*
650 644 * ql_flash_desc
651 645 * Get flash descriptor table.
652 646 */
653 647 static int
654 648 ql_flash_desc(qlge_t *qlge)
655 649 {
656 650 uint8_t w8;
657 651 uint32_t cnt, addr;
658 652 uint16_t chksum, *bp, data;
659 653 int rval;
660 654
661 655 addr = qlge->flash_fdt_addr;
662 656
663 657 rval = qlge_dump_fcode(qlge, (uint8_t *)&qlge->fdesc,
664 658 sizeof (flash_desc_t), addr);
665 659 if (rval != DDI_SUCCESS) {
666 660 cmn_err(CE_WARN, "%s(%d) read Flash Descriptor Table error",
667 661 __func__, qlge->instance);
668 662 bzero(&qlge->fdesc, sizeof (flash_desc_t));
669 663 return (rval);
670 664 }
671 665
672 666 chksum = 0;
673 667 data = 0;
674 668 bp = (uint16_t *)&qlge->fdesc;
675 669 for (cnt = 0; cnt < (sizeof (flash_desc_t)) / 2; cnt++) {
676 670 data = *bp;
677 671 LITTLE_ENDIAN_16(&data);
678 672 chksum += data;
679 673 bp++;
680 674 }
681 675 /* endian adjustment */
682 676 LITTLE_ENDIAN_32(&qlge->fdesc.flash_valid);
683 677 LITTLE_ENDIAN_16(&qlge->fdesc.flash_version);
684 678 LITTLE_ENDIAN_16(&qlge->fdesc.flash_len);
685 679 LITTLE_ENDIAN_16(&qlge->fdesc.flash_checksum);
686 680 LITTLE_ENDIAN_16(&qlge->fdesc.flash_unused);
687 681 LITTLE_ENDIAN_16(&qlge->fdesc.flash_manuf);
688 682 LITTLE_ENDIAN_16(&qlge->fdesc.flash_id);
689 683 LITTLE_ENDIAN_32(&qlge->fdesc.block_size);
690 684 LITTLE_ENDIAN_32(&qlge->fdesc.alt_block_size);
691 685 LITTLE_ENDIAN_32(&qlge->fdesc.flash_size);
692 686 LITTLE_ENDIAN_32(&qlge->fdesc.write_enable_data);
693 687 LITTLE_ENDIAN_32(&qlge->fdesc.read_timeout);
694 688
695 689 /* flash size in desc table is in 1024 bytes */
696 690 QL_PRINT(DBG_FLASH, ("flash_valid=%xh\n", qlge->fdesc.flash_valid));
697 691 QL_PRINT(DBG_FLASH, ("flash_version=%xh\n", qlge->fdesc.flash_version));
698 692 QL_PRINT(DBG_FLASH, ("flash_len=%xh\n", qlge->fdesc.flash_len));
699 693 QL_PRINT(DBG_FLASH, ("flash_checksum=%xh\n",
700 694 qlge->fdesc.flash_checksum));
701 695
702 696 w8 = qlge->fdesc.flash_model[15];
703 697 qlge->fdesc.flash_model[15] = 0;
704 698 QL_PRINT(DBG_FLASH, ("flash_model=%s\n", qlge->fdesc.flash_model));
705 699 qlge->fdesc.flash_model[15] = w8;
706 700 QL_PRINT(DBG_FLASH, ("flash_size=%xK bytes\n", qlge->fdesc.flash_size));
707 701 qlge->fdesc.flash_size = qlge->fdesc.flash_size * 0x400;
708 702 qlge->flash_info.flash_size = qlge->fdesc.flash_size;
709 703
710 704 if (chksum != 0 || qlge->fdesc.flash_valid != FLASH_DESC_VAILD ||
711 705 qlge->fdesc.flash_version != FLASH_DESC_VERSION) {
712 706 cmn_err(CE_WARN, "invalid descriptor table");
713 707 bzero(&qlge->fdesc, sizeof (flash_desc_t));
714 708 return (DDI_FAILURE);
715 709 }
716 710
717 711 return (DDI_SUCCESS);
718 712 }
719 713
720 714 /*
721 715 * ql_flash_nic_config
722 716 * Get flash NIC Configuration table.
723 717 */
724 718 static int
725 719 ql_flash_nic_config(qlge_t *qlge)
726 720 {
727 721 uint32_t cnt, addr;
728 722 uint16_t chksum, *bp, data;
729 723 int rval;
730 724
731 725 addr = qlge->flash_nic_config_table_addr;
732 726
733 727 rval = qlge_dump_fcode(qlge, (uint8_t *)&qlge->nic_config,
734 728 sizeof (ql_nic_config_t), addr);
735 729
736 730 if (rval != DDI_SUCCESS) {
737 731 cmn_err(CE_WARN, "fail to read nic_cfg image %xh", rval);
738 732 bzero(&qlge->nic_config, sizeof (ql_nic_config_t));
739 733 return (rval);
740 734 }
741 735
742 736 chksum = 0;
743 737 data = 0;
744 738 bp = (uint16_t *)&qlge->nic_config;
745 739 for (cnt = 0; cnt < (sizeof (ql_nic_config_t)) / 2; cnt++) {
746 740 data = *bp;
747 741 LITTLE_ENDIAN_16(&data);
748 742 chksum += data;
749 743 bp++;
750 744 }
751 745
752 746 LITTLE_ENDIAN_32(&qlge->nic_config.signature);
753 747 LITTLE_ENDIAN_16(&qlge->nic_config.version);
754 748 LITTLE_ENDIAN_16(&qlge->nic_config.size);
755 749 LITTLE_ENDIAN_16(&qlge->nic_config.checksum);
756 750 LITTLE_ENDIAN_16(&qlge->nic_config.total_data_size);
757 751 LITTLE_ENDIAN_16(&qlge->nic_config.num_of_entries);
758 752 LITTLE_ENDIAN_16(&qlge->nic_config.vlan_id);
759 753 LITTLE_ENDIAN_16(&qlge->nic_config.last_entry);
760 754 LITTLE_ENDIAN_16(&qlge->nic_config.subsys_vendor_id);
761 755 LITTLE_ENDIAN_16(&qlge->nic_config.subsys_device_id);
762 756
763 757 QL_PRINT(DBG_FLASH, ("(%d): signature=%xh\n",
764 758 qlge->instance, qlge->nic_config.signature));
765 759 QL_PRINT(DBG_FLASH, ("(%d): size=%xh\n",
766 760 qlge->instance, qlge->nic_config.size));
767 761 QL_PRINT(DBG_FLASH, ("(%d): checksum=%xh\n",
768 762 qlge->instance, qlge->nic_config.checksum));
769 763 QL_PRINT(DBG_FLASH, ("(%d): version=%xh\n",
770 764 qlge->instance, qlge->nic_config.version));
771 765 QL_PRINT(DBG_FLASH, ("(%d): total_data_size=%xh\n",
772 766 qlge->instance, qlge->nic_config.total_data_size));
773 767 QL_PRINT(DBG_FLASH, ("(%d): num_of_entries=%xh\n",
774 768 qlge->instance, qlge->nic_config.num_of_entries));
775 769 QL_PRINT(DBG_FLASH, ("(%d): data_type=%xh\n",
776 770 qlge->instance, qlge->nic_config.factory_data_type));
777 771 QL_PRINT(DBG_FLASH, ("(%d): data_type_size=%xh\n",
778 772 qlge->instance, qlge->nic_config.factory_data_type_size));
779 773 QL_PRINT(DBG_FLASH,
780 774 ("(%d): factory mac=%02x %02x %02x %02x %02x %02x h\n",
781 775 qlge->instance,
782 776 qlge->nic_config.factory_MAC[0],
783 777 qlge->nic_config.factory_MAC[1],
784 778 qlge->nic_config.factory_MAC[2],
785 779 qlge->nic_config.factory_MAC[3],
786 780 qlge->nic_config.factory_MAC[4],
787 781 qlge->nic_config.factory_MAC[5]));
788 782
789 783 QL_PRINT(DBG_FLASH, ("(%d): data_type=%xh\n",
790 784 qlge->instance, qlge->nic_config.clp_data_type));
791 785 QL_PRINT(DBG_FLASH, ("(%d): data_type_size=%xh\n",
792 786 qlge->instance, qlge->nic_config.clp_data_type_size));
793 787 QL_PRINT(DBG_FLASH, ("(%d): clp mac=%x %x %x %x %x %x h\n",
794 788 qlge->instance,
795 789 qlge->nic_config.clp_MAC[0],
796 790 qlge->nic_config.clp_MAC[1],
797 791 qlge->nic_config.clp_MAC[2],
798 792 qlge->nic_config.clp_MAC[3],
799 793 qlge->nic_config.clp_MAC[4],
800 794 qlge->nic_config.clp_MAC[5]));
801 795
802 796 QL_PRINT(DBG_FLASH, ("(%d): data_type=%xh\n",
803 797 qlge->instance, qlge->nic_config.clp_vlan_data_type));
804 798 QL_PRINT(DBG_FLASH, ("(%d): data_type_size=%xh\n",
805 799 qlge->instance, qlge->nic_config.clp_vlan_data_type_size));
806 800 QL_PRINT(DBG_FLASH, ("(%d): vlan_id=%xh\n",
807 801 qlge->instance, qlge->nic_config.vlan_id));
808 802
809 803 QL_PRINT(DBG_FLASH, ("(%d): data_type=%xh\n",
810 804 qlge->instance, qlge->nic_config.last_data_type));
811 805 QL_PRINT(DBG_FLASH, ("(%d): data_type_size=%xh\n",
812 806 qlge->instance, qlge->nic_config.last_data_type_size));
813 807 QL_PRINT(DBG_FLASH, ("(%d): last_entry=%xh\n",
814 808 qlge->instance, qlge->nic_config.last_entry));
815 809
816 810 QL_PRINT(DBG_FLASH, ("(%d): subsys_vendor_id=%xh\n",
817 811 qlge->instance, qlge->nic_config.subsys_vendor_id));
818 812 QL_PRINT(DBG_FLASH, ("(%d): subsys_device_id=%xh\n",
819 813 qlge->instance, qlge->nic_config.subsys_device_id));
820 814
821 815 if (chksum != 0 || qlge->nic_config.signature !=
822 816 FLASH_NIC_CONFIG_SIGNATURE || qlge->nic_config.version != 1) {
823 817 cmn_err(CE_WARN,
824 818 "invalid flash nic configuration table: chksum %x, "
825 819 "signature %x, version %x",
826 820 chksum, qlge->nic_config.signature,
827 821 qlge->nic_config.version);
828 822 return (DDI_FAILURE);
829 823 }
830 824
831 825 return (DDI_SUCCESS);
832 826 }
833 827
834 828 int
835 829 ql_flash_vpd(qlge_t *qlge, uint8_t *buf)
836 830 {
837 831 uint32_t cnt;
838 832 uint16_t chksum, *bp, data;
839 833 int rval;
840 834 uint32_t vpd_size;
841 835
842 836 if (buf == NULL) {
843 837 cmn_err(CE_WARN, "%s(%d) buffer is not available.",
844 838 __func__, qlge->instance);
845 839 return (DDI_FAILURE);
846 840 }
847 841
848 842 if (!qlge->flash_vpd_addr) {
849 843 if (qlge->func_number == qlge->fn0_net)
850 844 qlge->flash_vpd_addr = ISP_8100_VPD0_ADDR;
851 845 else
852 846 qlge->flash_vpd_addr = ISP_8100_VPD1_ADDR;
853 847 vpd_size = ISP_8100_VPD0_SIZE;
854 848 }
855 849 rval = qlge_dump_fcode(qlge, buf, vpd_size, qlge->flash_vpd_addr);
856 850
857 851 if (rval != DDI_SUCCESS) {
858 852 cmn_err(CE_WARN, "%s(%d)read error",
859 853 __func__, qlge->instance);
860 854 bzero(buf, vpd_size);
861 855 return (rval);
862 856 }
863 857
864 858 QL_DUMP(DBG_FLASH, "flash vpd table raw data:\n", buf, 8, vpd_size);
865 859
866 860 chksum = 0;
867 861 data = 0;
868 862 bp = (uint16_t *)(void *)buf;
869 863 for (cnt = 0; cnt < (vpd_size/2); cnt++) {
870 864 data = *bp;
871 865 LITTLE_ENDIAN_16(&data);
872 866 chksum += data;
873 867 bp++;
874 868 }
875 869 if (chksum != 0) {
876 870 cmn_err(CE_WARN, "%s(%d) invalid flash vpd table",
877 871 __func__, qlge->instance);
878 872 return (DDI_FAILURE);
879 873 }
880 874 return (DDI_SUCCESS);
881 875 }
882 876
883 877 int
884 878 ql_get_flash_params(qlge_t *qlge)
885 879 {
886 880 int rval = DDI_SUCCESS;
887 881
888 882 /* Get semaphore to access Flash Address and Flash Data Registers */
889 883 if (ql_sem_spinlock(qlge, QL_FLASH_SEM_MASK)) {
890 884 rval = DDI_FAILURE;
891 885 goto out;
892 886 }
893 887 /* do test read of flash ID */
894 888 rval = ql_flash_id(qlge);
895 889 if (rval != DDI_SUCCESS)
896 890 goto out;
897 891
898 892 /*
899 893 * Temporarily set the fdesc.flash_size to
900 894 * 4M flash size to avoid failing of ql_dump_focde.
901 895 */
902 896 qlge->fdesc.flash_size = 4096 * 1024; /* ie. 4M bytes */
903 897
904 898 /* Default flash descriptor table. */
905 899 qlge->fdesc.write_statusreg_cmd = 1;
906 900 qlge->fdesc.write_enable_bits = 0;
907 901 qlge->fdesc.unprotect_sector_cmd = 0;
908 902 qlge->fdesc.protect_sector_cmd = 0;
909 903 qlge->fdesc.write_disable_bits = 0x9c;
910 904 qlge->fdesc.block_size = 0x10000;
911 905 qlge->fdesc.erase_cmd = 0xd8;
912 906
913 907 /* ! todo : should read from fltds! */
914 908 /* !ql_get_flash_params(qlge); */
915 909 qlge->fltds.flt_addr_hi = 0x36;
916 910 qlge->fltds.flt_addr_lo = 0x1000;
917 911 /* read all other tables from Flash memory */
918 912 if (ql_flash_flt(qlge) != DDI_SUCCESS) {
919 913 if (CFG_IST(qlge, CFG_CHIP_8100)) {
920 914 qlge->flash_fdt_addr = ISP_8100_FDT_ADDR; /* 0x360000 */
921 915 if (qlge->func_number == qlge->fn0_net)
922 916 /* 0x140200 */
923 917 qlge->flash_nic_config_table_addr =
924 918 ISP_8100_NIC_PARAM0_ADDR;
925 919 else
926 920 /* 0x140600 */
927 921 qlge->flash_nic_config_table_addr =
928 922 ISP_8100_NIC_PARAM1_ADDR;
929 923 }
930 924 }
931 925 (void) ql_flash_desc(qlge);
932 926 (void) ql_flash_nic_config(qlge);
933 927
934 928 out:
935 929 ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
936 930
937 931 return (rval);
938 932 }
939 933
940 934 /*
941 935 * ql_setup_flash
942 936 * Gets the manufacturer and id number of the flash chip,
943 937 * and sets up the size parameter.
944 938 */
945 939 int
946 940 ql_setup_flash(qlge_t *qlge)
947 941 {
948 942 int rval = DDI_SUCCESS;
949 943
950 944 if (qlge->flash_fltds_addr != 0) {
951 945 return (rval);
952 946 }
953 947 if (ql_sem_spinlock(qlge, QL_FLASH_SEM_MASK)) {
954 948 rval = DDI_FAILURE;
955 949 goto out;
956 950 }
957 951 /* try reading flash ID */
958 952 rval = ql_flash_id(qlge);
959 953 if (rval != DDI_SUCCESS)
960 954 goto out;
961 955
962 956 /* Default flash descriptor table. */
963 957 qlge->fdesc.write_statusreg_cmd = 1;
964 958 qlge->fdesc.write_enable_bits = 0;
965 959 qlge->fdesc.unprotect_sector_cmd = 0;
966 960 qlge->fdesc.protect_sector_cmd = 0;
967 961 qlge->fdesc.write_disable_bits = 0x9c;
968 962 qlge->fdesc.block_size = 0x10000;
969 963 qlge->fdesc.erase_cmd = 0xd8;
970 964 /* 1 Get the location of Flash Layout Table Data Structure (FLTDS) */
971 965 if (ql_find_flash_layout_table_data_structure_addr(qlge)
972 966 == DDI_SUCCESS) {
973 967 /* 2,read fltds */
974 968 if (ql_flash_fltds(qlge) == DDI_SUCCESS) {
975 969 /*
976 970 * 3,search for flash descriptor table (FDT)
977 971 * and Nic Configuration Table indices
978 972 */
979 973 if ((qlge->flash_fdt_addr == 0) ||
980 974 (qlge->flash_nic_config_table_addr == 0)) {
981 975 rval = ql_flash_flt(qlge);
982 976 if (rval == DDI_SUCCESS) {
983 977 (void) ql_flash_desc(qlge);
984 978 (void) ql_flash_nic_config(qlge);
985 979 } else {
986 980 rval = DDI_FAILURE;
987 981 goto out;
988 982 }
989 983 }
990 984 } else {
991 985 rval = DDI_FAILURE;
992 986 goto out;
993 987 }
994 988 } else {
995 989 rval = DDI_FAILURE;
996 990 goto out;
997 991 }
998 992 out:
999 993 ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
1000 994
1001 995 return (rval);
1002 996
1003 997 }
1004 998
1005 999 /*
1006 1000 * ql_change_endian
1007 1001 * Change endianess of byte array.
1008 1002 */
1009 1003 void
1010 1004 ql_change_endian(uint8_t buf[], size_t size)
1011 1005 {
1012 1006 uint8_t byte;
1013 1007 size_t cnt1;
1014 1008 size_t cnt;
1015 1009
1016 1010 cnt1 = size - 1;
1017 1011 for (cnt = 0; cnt < size / 2; cnt++) {
1018 1012 byte = buf[cnt1];
1019 1013 buf[cnt1] = buf[cnt];
1020 1014 buf[cnt] = byte;
1021 1015 cnt1--;
1022 1016 }
1023 1017 }
1024 1018
1025 1019 static int
1026 1020 ql_wait_flash_reg_ready(qlge_t *qlge, uint32_t wait_bit)
1027 1021 {
1028 1022 uint32_t reg_status;
1029 1023 int rtn_val = DDI_SUCCESS;
1030 1024 uint32_t delay = 300000;
1031 1025
1032 1026 do {
1033 1027 reg_status = ql_read_reg(qlge, REG_FLASH_ADDRESS);
1034 1028 if (reg_status & FLASH_ERR_FLAG) {
1035 1029 cmn_err(CE_WARN,
1036 1030 "%s(%d) flash address register error bit set!",
1037 1031 __func__, qlge->instance);
1038 1032 rtn_val = DDI_FAILURE;
1039 1033 break;
1040 1034 }
1041 1035 if (reg_status & wait_bit) {
1042 1036 break;
1043 1037 }
1044 1038 drv_usecwait(10);
1045 1039 } while (--delay);
1046 1040
1047 1041 if (delay == 0) {
1048 1042 cmn_err(CE_WARN,
1049 1043 "%s(%d) timeout error!", __func__, qlge->instance);
1050 1044 if (qlge->fm_enable) {
1051 1045 ql_fm_ereport(qlge, DDI_FM_DEVICE_NO_RESPONSE);
1052 1046 atomic_or_32(&qlge->flags, ADAPTER_ERROR);
1053 1047 ddi_fm_service_impact(qlge->dip, DDI_SERVICE_LOST);
1054 1048 }
1055 1049 rtn_val = DDI_FAILURE;
1056 1050 }
1057 1051 return (rtn_val);
1058 1052 }
1059 1053
1060 1054 /*
1061 1055 * ql_read_flash
1062 1056 * Reads a 32bit word from FLASH.
1063 1057 */
1064 1058 static int
1065 1059 ql_read_flash(qlge_t *qlge, uint32_t faddr, uint32_t *bp)
1066 1060 {
1067 1061 int rval = DDI_SUCCESS;
1068 1062
1069 1063 ql_write_reg(qlge, REG_FLASH_ADDRESS, faddr | FLASH_R_FLAG);
1070 1064
1071 1065 /* Wait for READ cycle to complete. */
1072 1066 rval = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG);
1073 1067
1074 1068 if (rval == DDI_SUCCESS) {
1075 1069 *bp = ql_read_reg(qlge, REG_FLASH_DATA);
1076 1070 }
1077 1071 return (rval);
1078 1072 }
1079 1073
1080 1074 static int
1081 1075 ql_read_flash_status(qlge_t *qlge, uint8_t *value)
1082 1076 {
1083 1077 int rtn_val = DDI_SUCCESS;
1084 1078 uint32_t data, cmd = FLASH_CONF_ADDR | FLASH_R_FLAG;
1085 1079
1086 1080 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1087 1081 != DDI_SUCCESS) {
1088 1082 return (rtn_val);
1089 1083 }
1090 1084 cmd |= FLASH_RDSR_CMD /* 0x05 */;
1091 1085 ql_write_reg(qlge, REG_FLASH_ADDRESS, cmd);
1092 1086 if ((rtn_val = ql_wait_flash_reg_ready(qlge,
1093 1087 FLASH_RDY_FLAG | FLASH_R_FLAG)) != DDI_SUCCESS) {
1094 1088 return (rtn_val);
1095 1089 }
1096 1090 data = ql_read_reg(qlge, REG_FLASH_DATA);
1097 1091 *value = (uint8_t)(data & 0xff);
1098 1092 return (rtn_val);
1099 1093 }
1100 1094
1101 1095 static int
1102 1096 ql_flash_write_enable(qlge_t *qlge)
1103 1097 {
1104 1098 uint8_t reg_status;
1105 1099 int rtn_val = DDI_SUCCESS;
1106 1100 uint32_t cmd = FLASH_CONF_ADDR;
1107 1101 uint32_t delay = 300000;
1108 1102
1109 1103 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1110 1104 != DDI_SUCCESS) {
1111 1105 cmn_err(CE_WARN,
1112 1106 "%s(%d) timeout!", __func__, qlge->instance);
1113 1107 rtn_val = DDI_FAILURE;
1114 1108 return (rtn_val);
1115 1109 }
1116 1110 cmd |= qlge->fdesc.write_enable_cmd;
1117 1111 ql_write_reg(qlge, REG_FLASH_ADDRESS, cmd);
1118 1112 /* wait for WEL bit set */
1119 1113 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1120 1114 == DDI_SUCCESS) {
1121 1115 do {
1122 1116 (void) ql_read_flash_status(qlge, ®_status);
1123 1117 if (reg_status & BIT_1)
1124 1118 break;
1125 1119 drv_usecwait(10);
1126 1120 } while (--delay);
1127 1121 }
1128 1122 if (delay == 0) {
1129 1123 cmn_err(CE_WARN,
1130 1124 "%s(%d) timeout error! flash status reg: %x",
1131 1125 __func__, qlge->instance, reg_status);
1132 1126 rtn_val = DDI_FAILURE;
1133 1127 }
1134 1128 return (rtn_val);
1135 1129 }
1136 1130
1137 1131 static int
1138 1132 ql_flash_erase_sector(qlge_t *qlge, uint32_t sectorAddr)
1139 1133 {
1140 1134 int rtn_val = DDI_SUCCESS;
1141 1135 uint32_t data, cmd = FLASH_CONF_ADDR;
1142 1136 uint32_t delay = 300000;
1143 1137 uint8_t flash_status;
1144 1138
1145 1139 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1146 1140 != DDI_SUCCESS) {
1147 1141 return (rtn_val);
1148 1142 }
1149 1143
1150 1144 cmd |= (0x0300 | qlge->fdesc.erase_cmd);
1151 1145 data = ((sectorAddr & 0xff) << 16) | (sectorAddr & 0xff00) |
1152 1146 ((sectorAddr & 0xff0000) >> 16);
1153 1147
1154 1148 ql_write_reg(qlge, REG_FLASH_DATA, data);
1155 1149 ql_write_reg(qlge, REG_FLASH_ADDRESS, cmd);
1156 1150
1157 1151 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1158 1152 == DDI_SUCCESS) {
1159 1153 /* wait Write In Progress (WIP) bit to reset */
1160 1154 do {
1161 1155 (void) ql_read_flash_status(qlge, &flash_status);
1162 1156 if ((flash_status & BIT_0 /* WIP */) == 0)
1163 1157 break;
1164 1158 drv_usecwait(10);
1165 1159 } while (--delay);
1166 1160 } else {
1167 1161 return (rtn_val);
1168 1162 }
1169 1163
1170 1164 if (delay == 0) {
1171 1165 cmn_err(CE_WARN,
1172 1166 "%s(%d) timeout error! flash status reg: %x",
1173 1167 __func__, qlge->instance, flash_status);
1174 1168 rtn_val = DDI_FAILURE;
1175 1169 }
1176 1170 return (rtn_val);
1177 1171 }
1178 1172
1179 1173 /*
1180 1174 * ql_write_flash
1181 1175 * Writes a 32bit word to FLASH.
1182 1176 */
1183 1177 static int
1184 1178 ql_write_flash(qlge_t *qlge, uint32_t addr, uint32_t data)
1185 1179 {
1186 1180 int rval = DDI_SUCCESS;
1187 1181 uint32_t delay = 300000;
1188 1182 uint8_t flash_status;
1189 1183
1190 1184 ql_write_reg(qlge, REG_FLASH_DATA, data);
1191 1185 (void) ql_read_reg(qlge, REG_FLASH_DATA);
1192 1186 ql_write_reg(qlge, REG_FLASH_ADDRESS, addr);
1193 1187
1194 1188 if ((rval = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1195 1189 == DDI_SUCCESS) {
1196 1190 if ((addr & FLASH_ADDR_MASK) == FLASH_CONF_ADDR) {
1197 1191 /* wait Write In Progress (WIP) bit to reset */
1198 1192 do {
1199 1193 (void) ql_read_flash_status(qlge,
1200 1194 &flash_status);
1201 1195 if ((flash_status & BIT_0 /* WIP */) == 0)
1202 1196 break;
1203 1197 drv_usecwait(10);
1204 1198 } while (--delay);
1205 1199 }
1206 1200 } else {
1207 1201 return (rval);
1208 1202 }
1209 1203
1210 1204 if (delay == 0) {
1211 1205 cmn_err(CE_WARN,
1212 1206 "%s(%d) timeout error! flash status reg: %x",
1213 1207 __func__, qlge->instance, flash_status);
1214 1208 rval = DDI_FAILURE;
1215 1209 }
1216 1210
1217 1211 return (rval);
1218 1212 }
1219 1213
1220 1214 /*
1221 1215 * ql_unprotect_flash
1222 1216 * Enable writes
1223 1217 */
1224 1218 static int
1225 1219 ql_unprotect_flash(qlge_t *qlge)
1226 1220 {
1227 1221 int fdata, rtn_val;
1228 1222
1229 1223 if ((rtn_val = ql_flash_write_enable(qlge)) != DDI_SUCCESS) {
1230 1224 return (rtn_val);
1231 1225 }
1232 1226
1233 1227 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1234 1228 != DDI_SUCCESS) {
1235 1229 return (rtn_val);
1236 1230 }
1237 1231
1238 1232 /*
1239 1233 * Remove block write protection (SST and ST) and
1240 1234 * Sector/Block Protection Register Lock (SST, ST, ATMEL).
1241 1235 * Unprotect sectors.
1242 1236 */
1243 1237 (void) ql_write_flash(qlge,
1244 1238 FLASH_CONF_ADDR | 0x100 | qlge->fdesc.write_statusreg_cmd,
1245 1239 qlge->fdesc.write_enable_bits);
1246 1240
1247 1241 if (qlge->fdesc.unprotect_sector_cmd != 0) {
1248 1242 for (fdata = 0; fdata < 0x10; fdata++) {
1249 1243 (void) ql_write_flash(qlge, FLASH_CONF_ADDR |
1250 1244 0x300 | qlge->fdesc.unprotect_sector_cmd, fdata);
1251 1245 }
1252 1246
1253 1247 (void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x300 |
1254 1248 qlge->fdesc.unprotect_sector_cmd, 0x00400f);
1255 1249 (void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x300 |
1256 1250 qlge->fdesc.unprotect_sector_cmd, 0x00600f);
1257 1251 (void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x300 |
1258 1252 qlge->fdesc.unprotect_sector_cmd, 0x00800f);
1259 1253 }
1260 1254 rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG);
1261 1255 return (rtn_val);
1262 1256 }
1263 1257
1264 1258 /*
1265 1259 * ql_protect_flash
1266 1260 * Disable writes
1267 1261 */
1268 1262 static int
1269 1263 ql_protect_flash(qlge_t *qlge)
1270 1264 {
1271 1265 int fdata, rtn_val;
1272 1266
1273 1267 if ((rtn_val = ql_flash_write_enable(qlge)) != DDI_SUCCESS) {
1274 1268 return (rtn_val);
1275 1269 }
1276 1270
1277 1271 if ((rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG))
1278 1272 != DDI_SUCCESS) {
1279 1273 return (rtn_val);
1280 1274 }
1281 1275 /*
1282 1276 * Protect sectors.
1283 1277 * Set block write protection (SST and ST) and
1284 1278 * Sector/Block Protection Register Lock (SST, ST, ATMEL).
1285 1279 */
1286 1280
1287 1281 if (qlge->fdesc.protect_sector_cmd != 0) {
1288 1282 for (fdata = 0; fdata < 0x10; fdata++) {
1289 1283 (void) ql_write_flash(qlge, FLASH_CONF_ADDR |
1290 1284 0x330 | qlge->fdesc.protect_sector_cmd, fdata);
1291 1285 }
1292 1286 (void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x330 |
1293 1287 qlge->fdesc.protect_sector_cmd, 0x00400f);
1294 1288 (void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x330 |
1295 1289 qlge->fdesc.protect_sector_cmd, 0x00600f);
1296 1290 (void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x330 |
1297 1291 qlge->fdesc.protect_sector_cmd, 0x00800f);
1298 1292
1299 1293 (void) ql_write_flash(qlge,
1300 1294 FLASH_CONF_ADDR | 0x101, 0x80);
1301 1295 } else {
1302 1296 (void) ql_write_flash(qlge,
1303 1297 FLASH_CONF_ADDR | 0x100 | qlge->fdesc.write_statusreg_cmd,
1304 1298 qlge->fdesc.write_disable_bits /* 0x9c */);
1305 1299 }
1306 1300
1307 1301 rtn_val = ql_wait_flash_reg_ready(qlge, FLASH_RDY_FLAG);
1308 1302 return (rtn_val);
1309 1303 }
1310 1304
1311 1305 /*
1312 1306 * ql_write_flash_test
1313 1307 * test write to a flash sector that is not being used
1314 1308 */
1315 1309 void
1316 1310 ql_write_flash_test(qlge_t *qlge, uint32_t test_addr)
1317 1311 {
1318 1312 uint32_t old_data, data;
1319 1313 uint32_t addr = 0;
1320 1314
1321 1315 addr = (test_addr / 4);
1322 1316 (void) ql_read_flash(qlge, addr, &old_data);
1323 1317 QL_PRINT(DBG_FLASH, ("read addr %x old value %x\n", test_addr,
1324 1318 old_data));
1325 1319
1326 1320 /* enable writing to flash */
1327 1321 (void) ql_unprotect_flash(qlge);
1328 1322
1329 1323 /* erase the sector */
1330 1324 (void) ql_flash_erase_sector(qlge, test_addr);
1331 1325 (void) ql_read_flash(qlge, addr, &data);
1332 1326 QL_PRINT(DBG_FLASH, ("after sector erase, addr %x value %x\n",
1333 1327 test_addr, data));
1334 1328
1335 1329 /* write new value to it and read back to confirm */
1336 1330 data = 0x33445566;
1337 1331 (void) ql_write_flash(qlge, addr, data);
1338 1332 QL_PRINT(DBG_FLASH, ("new value written to addr %x value %x\n",
1339 1333 test_addr, data));
1340 1334 (void) ql_read_flash(qlge, addr, &data);
1341 1335 if (data != 0x33445566) {
1342 1336 cmn_err(CE_WARN, "flash write test failed, get data %x"
1343 1337 " after writing", data);
1344 1338 }
1345 1339
1346 1340 /* write old value to it and read back to restore */
1347 1341 (void) ql_flash_erase_sector(qlge, test_addr);
1348 1342 (void) ql_write_flash(qlge, addr, old_data);
1349 1343 (void) ql_read_flash(qlge, addr, &data);
1350 1344 QL_PRINT(DBG_FLASH, ("write back old value addr %x value %x\n",
1351 1345 test_addr, data));
1352 1346
1353 1347 /* test done, protect the flash to forbid any more flash writting */
1354 1348 (void) ql_protect_flash(qlge);
1355 1349
1356 1350 }
1357 1351
1358 1352
1359 1353 void
1360 1354 ql_write_flash_test2(qlge_t *qlge, uint32_t test_addr)
1361 1355 {
1362 1356 uint32_t data, old_data;
1363 1357
1364 1358 (void) qlge_dump_fcode(qlge, (uint8_t *)&old_data, sizeof (old_data),
1365 1359 test_addr);
1366 1360 QL_PRINT(DBG_FLASH, ("read addr %x old value %x\n",
1367 1361 test_addr, old_data));
1368 1362
1369 1363 data = 0x12345678;
1370 1364
1371 1365 QL_PRINT(DBG_FLASH, ("write new test value %x\n", data));
1372 1366 (void) qlge_load_flash(qlge, (uint8_t *)&data, sizeof (data),
1373 1367 test_addr);
1374 1368 (void) qlge_dump_fcode(qlge, (uint8_t *)&data, sizeof (data),
1375 1369 test_addr);
1376 1370 if (data != 0x12345678) {
1377 1371 cmn_err(CE_WARN,
1378 1372 "flash write test failed, get data %x after writing",
1379 1373 data);
1380 1374 }
1381 1375 /* write old value to it and read back to restore */
1382 1376 (void) qlge_load_flash(qlge, (uint8_t *)&old_data, sizeof (old_data),
1383 1377 test_addr);
1384 1378 (void) qlge_dump_fcode(qlge, (uint8_t *)&data, sizeof (data),
1385 1379 test_addr);
1386 1380 QL_PRINT(DBG_FLASH, ("write back old value addr %x value %x verified\n",
1387 1381 test_addr, data));
1388 1382 }
1389 1383
1390 1384 /*
1391 1385 * ql_sem_flash_lock
1392 1386 * Flash memory is a shared resource amoung various PCI Functions, so,
1393 1387 * anyone wants to access flash memory, it needs to lock it first.
1394 1388 */
1395 1389 int
1396 1390 ql_sem_flash_lock(qlge_t *qlge)
1397 1391 {
1398 1392 int rval = DDI_SUCCESS;
1399 1393
1400 1394 /* Get semaphore to access Flash Address and Flash Data Registers */
1401 1395 if (ql_sem_spinlock(qlge, QL_FLASH_SEM_MASK)) {
1402 1396 rval = DDI_FAILURE;
1403 1397 }
1404 1398 return (rval);
1405 1399 }
1406 1400
1407 1401 void
1408 1402 ql_sem_flash_unlock(qlge_t *qlge)
1409 1403 {
1410 1404 ql_sem_unlock(qlge, QL_FLASH_SEM_MASK);
1411 1405 }
↓ open down ↓ |
1152 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX