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5253 kmem_alloc/kmem_zalloc won't fail with KM_SLEEP
5254 getrbuf won't fail with KM_SLEEP
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--- old/usr/src/uts/common/io/iwh/iwh.c
+++ new/usr/src/uts/common/io/iwh/iwh.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2009, Intel Corporation
8 8 * All rights reserved.
9 9 */
10 10
11 11 /*
12 12 * Copyright (c) 2006
13 13 * Copyright (c) 2007
14 14 * Damien Bergamini <damien.bergamini@free.fr>
15 15 *
16 16 * Permission to use, copy, modify, and distribute this software for any
17 17 * purpose with or without fee is hereby granted, provided that the above
18 18 * copyright notice and this permission notice appear in all copies.
19 19 *
20 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
22 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
23 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
25 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
26 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
27 27 */
28 28
29 29 /*
30 30 * Intel(R) WiFi Link 5100/5300 Driver
31 31 */
32 32
33 33 #include <sys/types.h>
34 34 #include <sys/byteorder.h>
35 35 #include <sys/conf.h>
36 36 #include <sys/cmn_err.h>
37 37 #include <sys/stat.h>
38 38 #include <sys/ddi.h>
39 39 #include <sys/sunddi.h>
40 40 #include <sys/strsubr.h>
41 41 #include <sys/ethernet.h>
42 42 #include <inet/common.h>
43 43 #include <inet/nd.h>
44 44 #include <inet/mi.h>
45 45 #include <sys/note.h>
46 46 #include <sys/stream.h>
47 47 #include <sys/strsun.h>
48 48 #include <sys/modctl.h>
49 49 #include <sys/devops.h>
50 50 #include <sys/dlpi.h>
51 51 #include <sys/mac_provider.h>
52 52 #include <sys/mac_wifi.h>
53 53 #include <sys/net80211.h>
54 54 #include <sys/net80211_proto.h>
55 55 #include <sys/net80211_ht.h>
56 56 #include <sys/varargs.h>
57 57 #include <sys/policy.h>
58 58 #include <sys/pci.h>
59 59
60 60 #include "iwh_calibration.h"
61 61 #include "iwh_hw.h"
62 62 #include "iwh_eeprom.h"
63 63 #include "iwh_var.h"
64 64 #include <inet/wifi_ioctl.h>
65 65
66 66 #ifdef DEBUG
67 67 #define IWH_DEBUG_80211 (1 << 0)
68 68 #define IWH_DEBUG_CMD (1 << 1)
69 69 #define IWH_DEBUG_DMA (1 << 2)
70 70 #define IWH_DEBUG_EEPROM (1 << 3)
71 71 #define IWH_DEBUG_FW (1 << 4)
72 72 #define IWH_DEBUG_HW (1 << 5)
73 73 #define IWH_DEBUG_INTR (1 << 6)
74 74 #define IWH_DEBUG_MRR (1 << 7)
75 75 #define IWH_DEBUG_PIO (1 << 8)
76 76 #define IWH_DEBUG_RX (1 << 9)
77 77 #define IWH_DEBUG_SCAN (1 << 10)
78 78 #define IWH_DEBUG_TX (1 << 11)
79 79 #define IWH_DEBUG_RATECTL (1 << 12)
80 80 #define IWH_DEBUG_RADIO (1 << 13)
81 81 #define IWH_DEBUG_RESUME (1 << 14)
82 82 #define IWH_DEBUG_CALIBRATION (1 << 15)
83 83 #define IWH_DEBUG_BA (1 << 16)
84 84 #define IWH_DEBUG_RXON (1 << 17)
85 85 #define IWH_DEBUG_HWRATE (1 << 18)
86 86 #define IWH_DEBUG_HTRATE (1 << 19)
87 87 #define IWH_DEBUG_QOS (1 << 20)
88 88 /*
89 89 * if want to see debug message of a given section,
90 90 * please set this flag to one of above values
91 91 */
92 92 uint32_t iwh_dbg_flags = 0;
93 93 #define IWH_DBG(x) \
94 94 iwh_dbg x
95 95 #else
96 96 #define IWH_DBG(x)
97 97 #endif
98 98
99 99 #define MS(v, f) (((v) & f) >> f##_S)
100 100
101 101 static void *iwh_soft_state_p = NULL;
102 102
103 103 /*
104 104 * ucode will be compiled into driver image
105 105 */
106 106 static uint8_t iwh_fw_5000_bin[] = {
107 107 #include "fw-iw/fw_5000/iwh_5000.ucode"
108 108 };
109 109
110 110 static uint8_t iwh_fw_5150_bin[] = {
111 111 #include "fw-iw/fw_5150/iwh_5150.ucode"
112 112 };
113 113
114 114 /*
115 115 * DMA attributes for a shared page
116 116 */
117 117 static ddi_dma_attr_t sh_dma_attr = {
118 118 DMA_ATTR_V0, /* version of this structure */
119 119 0, /* lowest usable address */
120 120 0xffffffffU, /* highest usable address */
121 121 0xffffffffU, /* maximum DMAable byte count */
122 122 0x1000, /* alignment in bytes */
123 123 0x1000, /* burst sizes (any?) */
124 124 1, /* minimum transfer */
125 125 0xffffffffU, /* maximum transfer */
126 126 0xffffffffU, /* maximum segment length */
127 127 1, /* maximum number of segments */
128 128 1, /* granularity */
129 129 0, /* flags (reserved) */
130 130 };
131 131
132 132 /*
133 133 * DMA attributes for a keep warm DRAM descriptor
134 134 */
135 135 static ddi_dma_attr_t kw_dma_attr = {
136 136 DMA_ATTR_V0, /* version of this structure */
137 137 0, /* lowest usable address */
138 138 0xffffffffU, /* highest usable address */
139 139 0xffffffffU, /* maximum DMAable byte count */
140 140 0x1000, /* alignment in bytes */
141 141 0x1000, /* burst sizes (any?) */
142 142 1, /* minimum transfer */
143 143 0xffffffffU, /* maximum transfer */
144 144 0xffffffffU, /* maximum segment length */
145 145 1, /* maximum number of segments */
146 146 1, /* granularity */
147 147 0, /* flags (reserved) */
148 148 };
149 149
150 150 /*
151 151 * DMA attributes for a ring descriptor
152 152 */
153 153 static ddi_dma_attr_t ring_desc_dma_attr = {
154 154 DMA_ATTR_V0, /* version of this structure */
155 155 0, /* lowest usable address */
156 156 0xffffffffU, /* highest usable address */
157 157 0xffffffffU, /* maximum DMAable byte count */
158 158 0x100, /* alignment in bytes */
159 159 0x100, /* burst sizes (any?) */
160 160 1, /* minimum transfer */
161 161 0xffffffffU, /* maximum transfer */
162 162 0xffffffffU, /* maximum segment length */
163 163 1, /* maximum number of segments */
164 164 1, /* granularity */
165 165 0, /* flags (reserved) */
166 166 };
167 167
168 168 /*
169 169 * DMA attributes for a cmd
170 170 */
171 171 static ddi_dma_attr_t cmd_dma_attr = {
172 172 DMA_ATTR_V0, /* version of this structure */
173 173 0, /* lowest usable address */
174 174 0xffffffffU, /* highest usable address */
175 175 0xffffffffU, /* maximum DMAable byte count */
176 176 4, /* alignment in bytes */
177 177 0x100, /* burst sizes (any?) */
178 178 1, /* minimum transfer */
179 179 0xffffffffU, /* maximum transfer */
180 180 0xffffffffU, /* maximum segment length */
181 181 1, /* maximum number of segments */
182 182 1, /* granularity */
183 183 0, /* flags (reserved) */
184 184 };
185 185
186 186 /*
187 187 * DMA attributes for a rx buffer
188 188 */
189 189 static ddi_dma_attr_t rx_buffer_dma_attr = {
190 190 DMA_ATTR_V0, /* version of this structure */
191 191 0, /* lowest usable address */
192 192 0xffffffffU, /* highest usable address */
193 193 0xffffffffU, /* maximum DMAable byte count */
194 194 0x100, /* alignment in bytes */
195 195 0x100, /* burst sizes (any?) */
196 196 1, /* minimum transfer */
197 197 0xffffffffU, /* maximum transfer */
198 198 0xffffffffU, /* maximum segment length */
199 199 1, /* maximum number of segments */
200 200 1, /* granularity */
201 201 0, /* flags (reserved) */
202 202 };
203 203
204 204 /*
205 205 * DMA attributes for a tx buffer.
206 206 * the maximum number of segments is 4 for the hardware.
207 207 * now all the wifi drivers put the whole frame in a single
208 208 * descriptor, so we define the maximum number of segments 1,
209 209 * just the same as the rx_buffer. we consider leverage the HW
210 210 * ability in the future, that is why we don't define rx and tx
211 211 * buffer_dma_attr as the same.
212 212 */
213 213 static ddi_dma_attr_t tx_buffer_dma_attr = {
214 214 DMA_ATTR_V0, /* version of this structure */
215 215 0, /* lowest usable address */
216 216 0xffffffffU, /* highest usable address */
217 217 0xffffffffU, /* maximum DMAable byte count */
218 218 4, /* alignment in bytes */
219 219 0x100, /* burst sizes (any?) */
220 220 1, /* minimum transfer */
221 221 0xffffffffU, /* maximum transfer */
222 222 0xffffffffU, /* maximum segment length */
223 223 1, /* maximum number of segments */
224 224 1, /* granularity */
225 225 0, /* flags (reserved) */
226 226 };
227 227
228 228 /*
229 229 * DMA attributes for text and data part in the firmware
230 230 */
231 231 static ddi_dma_attr_t fw_dma_attr = {
232 232 DMA_ATTR_V0, /* version of this structure */
233 233 0, /* lowest usable address */
234 234 0xffffffffU, /* highest usable address */
235 235 0x7fffffff, /* maximum DMAable byte count */
236 236 0x10, /* alignment in bytes */
237 237 0x100, /* burst sizes (any?) */
238 238 1, /* minimum transfer */
239 239 0xffffffffU, /* maximum transfer */
240 240 0xffffffffU, /* maximum segment length */
241 241 1, /* maximum number of segments */
242 242 1, /* granularity */
243 243 0, /* flags (reserved) */
244 244 };
245 245
246 246 /*
247 247 * regs access attributes
248 248 */
249 249 static ddi_device_acc_attr_t iwh_reg_accattr = {
250 250 DDI_DEVICE_ATTR_V0,
251 251 DDI_STRUCTURE_LE_ACC,
252 252 DDI_STRICTORDER_ACC,
253 253 DDI_DEFAULT_ACC
254 254 };
255 255
256 256 /*
257 257 * DMA access attributes for descriptor
258 258 */
259 259 static ddi_device_acc_attr_t iwh_dma_descattr = {
260 260 DDI_DEVICE_ATTR_V0,
261 261 DDI_STRUCTURE_LE_ACC,
262 262 DDI_STRICTORDER_ACC,
263 263 DDI_DEFAULT_ACC
264 264 };
265 265
266 266 /*
267 267 * DMA access attributes
268 268 */
269 269 static ddi_device_acc_attr_t iwh_dma_accattr = {
270 270 DDI_DEVICE_ATTR_V0,
271 271 DDI_NEVERSWAP_ACC,
272 272 DDI_STRICTORDER_ACC,
273 273 DDI_DEFAULT_ACC
274 274 };
275 275
276 276 static int iwh_ring_init(iwh_sc_t *);
277 277 static void iwh_ring_free(iwh_sc_t *);
278 278 static int iwh_alloc_shared(iwh_sc_t *);
279 279 static void iwh_free_shared(iwh_sc_t *);
280 280 static int iwh_alloc_kw(iwh_sc_t *);
281 281 static void iwh_free_kw(iwh_sc_t *);
282 282 static int iwh_alloc_fw_dma(iwh_sc_t *);
283 283 static void iwh_free_fw_dma(iwh_sc_t *);
284 284 static int iwh_alloc_rx_ring(iwh_sc_t *);
285 285 static void iwh_reset_rx_ring(iwh_sc_t *);
286 286 static void iwh_free_rx_ring(iwh_sc_t *);
287 287 static int iwh_alloc_tx_ring(iwh_sc_t *, iwh_tx_ring_t *,
288 288 int, int);
289 289 static void iwh_reset_tx_ring(iwh_sc_t *, iwh_tx_ring_t *);
290 290 static void iwh_free_tx_ring(iwh_tx_ring_t *);
291 291 static ieee80211_node_t *iwh_node_alloc(ieee80211com_t *);
292 292 static void iwh_node_free(ieee80211_node_t *);
293 293 static int iwh_newstate(ieee80211com_t *, enum ieee80211_state, int);
294 294 static void iwh_mac_access_enter(iwh_sc_t *);
295 295 static void iwh_mac_access_exit(iwh_sc_t *);
296 296 static uint32_t iwh_reg_read(iwh_sc_t *, uint32_t);
297 297 static void iwh_reg_write(iwh_sc_t *, uint32_t, uint32_t);
298 298 static int iwh_load_init_firmware(iwh_sc_t *);
299 299 static int iwh_load_run_firmware(iwh_sc_t *);
300 300 static void iwh_tx_intr(iwh_sc_t *, iwh_rx_desc_t *);
301 301 static void iwh_cmd_intr(iwh_sc_t *, iwh_rx_desc_t *);
302 302 static uint_t iwh_intr(caddr_t, caddr_t);
303 303 static int iwh_eep_load(iwh_sc_t *);
304 304 static void iwh_get_mac_from_eep(iwh_sc_t *);
305 305 static int iwh_eep_sem_down(iwh_sc_t *);
306 306 static void iwh_eep_sem_up(iwh_sc_t *);
307 307 static uint_t iwh_rx_softintr(caddr_t, caddr_t);
308 308 static uint8_t iwh_rate_to_plcp(int);
309 309 static int iwh_cmd(iwh_sc_t *, int, const void *, int, int);
310 310 static void iwh_set_led(iwh_sc_t *, uint8_t, uint8_t, uint8_t);
311 311 static int iwh_hw_set_before_auth(iwh_sc_t *);
312 312 static int iwh_scan(iwh_sc_t *);
313 313 static int iwh_config(iwh_sc_t *);
314 314 static void iwh_stop_master(iwh_sc_t *);
315 315 static int iwh_power_up(iwh_sc_t *);
316 316 static int iwh_preinit(iwh_sc_t *);
317 317 static int iwh_init(iwh_sc_t *);
318 318 static void iwh_stop(iwh_sc_t *);
319 319 static int iwh_quiesce(dev_info_t *t);
320 320 static void iwh_amrr_init(iwh_amrr_t *);
321 321 static void iwh_amrr_timeout(iwh_sc_t *);
322 322 static void iwh_amrr_ratectl(void *, ieee80211_node_t *);
323 323 static void iwh_ucode_alive(iwh_sc_t *, iwh_rx_desc_t *);
324 324 static void iwh_rx_phy_intr(iwh_sc_t *, iwh_rx_desc_t *);
325 325 static void iwh_rx_mpdu_intr(iwh_sc_t *, iwh_rx_desc_t *);
326 326 static void iwh_release_calib_buffer(iwh_sc_t *);
327 327 static int iwh_init_common(iwh_sc_t *);
328 328 static uint8_t *iwh_eep_addr_trans(iwh_sc_t *, uint32_t);
329 329 static int iwh_put_seg_fw(iwh_sc_t *, uint32_t, uint32_t, uint32_t);
330 330 static int iwh_alive_common(iwh_sc_t *);
331 331 static void iwh_save_calib_result(iwh_sc_t *, iwh_rx_desc_t *);
332 332 static int iwh_tx_power_table(iwh_sc_t *, int);
333 333 static int iwh_attach(dev_info_t *, ddi_attach_cmd_t);
334 334 static int iwh_detach(dev_info_t *, ddi_detach_cmd_t);
335 335 static void iwh_destroy_locks(iwh_sc_t *);
336 336 static int iwh_send(ieee80211com_t *, mblk_t *, uint8_t);
337 337 static void iwh_thread(iwh_sc_t *);
338 338 static int iwh_run_state_config(iwh_sc_t *);
339 339 static int iwh_fast_recover(iwh_sc_t *);
340 340 static int iwh_wme_update(ieee80211com_t *);
341 341 static int iwh_qosparam_to_hw(iwh_sc_t *, int);
342 342 static int iwh_wme_to_qos_ac(int);
343 343 static uint16_t iwh_cw_e_to_cw(uint8_t);
344 344 static int iwh_wmeparam_check(struct wmeParams *);
345 345 static inline int iwh_wme_tid_qos_ac(int);
346 346 static inline int iwh_qos_ac_to_txq(int);
347 347 static int iwh_wme_tid_to_txq(int);
348 348 static void iwh_init_ht_conf(iwh_sc_t *);
349 349 static void iwh_overwrite_11n_rateset(iwh_sc_t *);
350 350 static void iwh_overwrite_ic_default(iwh_sc_t *);
351 351 static void iwh_config_rxon_chain(iwh_sc_t *);
352 352 static int iwh_add_ap_sta(iwh_sc_t *);
353 353 static int iwh_ap_lq(iwh_sc_t *);
354 354 static void iwh_recv_action(struct ieee80211_node *,
355 355 const uint8_t *, const uint8_t *);
356 356 static int iwh_send_action(struct ieee80211_node *,
357 357 int, int, uint16_t[4]);
358 358 static int iwh_is_max_rate(ieee80211_node_t *);
359 359 static int iwh_is_min_rate(ieee80211_node_t *);
360 360 static void iwh_increase_rate(ieee80211_node_t *);
361 361 static void iwh_decrease_rate(ieee80211_node_t *);
362 362 static int iwh_alloc_dma_mem(iwh_sc_t *, size_t,
363 363 ddi_dma_attr_t *, ddi_device_acc_attr_t *,
364 364 uint_t, iwh_dma_t *);
365 365 static void iwh_free_dma_mem(iwh_dma_t *);
366 366 static int iwh_reset_hw(iwh_sc_t *);
367 367
368 368 /*
369 369 * GLD specific operations
370 370 */
371 371 static int iwh_m_stat(void *, uint_t, uint64_t *);
372 372 static int iwh_m_start(void *);
373 373 static void iwh_m_stop(void *);
374 374 static int iwh_m_unicst(void *, const uint8_t *);
375 375 static int iwh_m_multicst(void *, boolean_t, const uint8_t *);
376 376 static int iwh_m_promisc(void *, boolean_t);
377 377 static mblk_t *iwh_m_tx(void *, mblk_t *);
378 378 static void iwh_m_ioctl(void *, queue_t *, mblk_t *);
379 379 static int iwh_m_setprop(void *arg, const char *pr_name,
380 380 mac_prop_id_t wldp_pr_num, uint_t wldp_length, const void *wldp_buf);
381 381 static int iwh_m_getprop(void *arg, const char *pr_name,
382 382 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
383 383 void *wldp_buf);
384 384 static void iwh_m_propinfo(void *arg, const char *pr_name,
385 385 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t mph);
386 386
387 387 /*
388 388 * Supported rates for 802.11b/g modes (in 500Kbps unit).
389 389 */
390 390 static const struct ieee80211_rateset iwh_rateset_11b =
391 391 { 4, { 2, 4, 11, 22 } };
392 392
393 393 static const struct ieee80211_rateset iwh_rateset_11g =
394 394 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
395 395
396 396 /*
397 397 * Default 11n reates supported by this station.
398 398 */
399 399 extern struct ieee80211_htrateset ieee80211_rateset_11n;
400 400
401 401 /*
402 402 * For mfthread only
403 403 */
404 404 extern pri_t minclsyspri;
405 405
406 406 #define DRV_NAME_SP "iwh"
407 407
408 408 /*
409 409 * Module Loading Data & Entry Points
410 410 */
411 411 DDI_DEFINE_STREAM_OPS(iwh_devops, nulldev, nulldev, iwh_attach,
412 412 iwh_detach, nodev, NULL, D_MP, NULL, iwh_quiesce);
413 413
414 414 static struct modldrv iwh_modldrv = {
415 415 &mod_driverops,
416 416 "Intel(R) ShirleyPeak/EchoPeak driver(N)",
417 417 &iwh_devops
418 418 };
419 419
420 420 static struct modlinkage iwh_modlinkage = {
421 421 MODREV_1,
422 422 &iwh_modldrv,
423 423 NULL
424 424 };
425 425
426 426 int
427 427 _init(void)
428 428 {
429 429 int status;
430 430
431 431 status = ddi_soft_state_init(&iwh_soft_state_p,
432 432 sizeof (iwh_sc_t), 1);
433 433 if (status != DDI_SUCCESS) {
434 434 return (status);
435 435 }
436 436
437 437 mac_init_ops(&iwh_devops, DRV_NAME_SP);
438 438 status = mod_install(&iwh_modlinkage);
439 439 if (status != DDI_SUCCESS) {
440 440 mac_fini_ops(&iwh_devops);
441 441 ddi_soft_state_fini(&iwh_soft_state_p);
442 442 }
443 443
444 444 return (status);
445 445 }
446 446
447 447 int
448 448 _fini(void)
449 449 {
450 450 int status;
451 451
452 452 status = mod_remove(&iwh_modlinkage);
453 453 if (DDI_SUCCESS == status) {
454 454 mac_fini_ops(&iwh_devops);
455 455 ddi_soft_state_fini(&iwh_soft_state_p);
456 456 }
457 457
458 458 return (status);
459 459 }
460 460
461 461 int
462 462 _info(struct modinfo *mip)
463 463 {
464 464 return (mod_info(&iwh_modlinkage, mip));
465 465 }
466 466
467 467 /*
468 468 * Mac Call Back entries
469 469 */
470 470 mac_callbacks_t iwh_m_callbacks = {
471 471 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
472 472 iwh_m_stat,
473 473 iwh_m_start,
474 474 iwh_m_stop,
475 475 iwh_m_promisc,
476 476 iwh_m_multicst,
477 477 iwh_m_unicst,
478 478 iwh_m_tx,
479 479 NULL,
480 480 iwh_m_ioctl,
481 481 NULL,
482 482 NULL,
483 483 NULL,
484 484 iwh_m_setprop,
485 485 iwh_m_getprop,
486 486 iwh_m_propinfo
487 487 };
488 488
489 489 #ifdef DEBUG
490 490 void
491 491 iwh_dbg(uint32_t flags, const char *fmt, ...)
492 492 {
493 493 va_list ap;
494 494
495 495 if (flags & iwh_dbg_flags) {
496 496 va_start(ap, fmt);
497 497 vcmn_err(CE_NOTE, fmt, ap);
498 498 va_end(ap);
499 499 }
500 500 }
501 501 #endif /* DEBUG */
502 502
503 503 /*
504 504 * device operations
505 505 */
506 506 int
507 507 iwh_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
508 508 {
509 509 iwh_sc_t *sc;
510 510 ieee80211com_t *ic;
511 511 int instance, i;
512 512 char strbuf[32];
513 513 wifi_data_t wd = { 0 };
514 514 mac_register_t *macp;
515 515 int intr_type;
516 516 int intr_count;
517 517 int intr_actual;
518 518 int err = DDI_FAILURE;
519 519
520 520 switch (cmd) {
521 521 case DDI_ATTACH:
522 522 break;
523 523
524 524 case DDI_RESUME:
525 525 instance = ddi_get_instance(dip);
526 526 sc = ddi_get_soft_state(iwh_soft_state_p,
527 527 instance);
528 528 ASSERT(sc != NULL);
529 529
530 530 if (sc->sc_flags & IWH_F_RUNNING) {
531 531 (void) iwh_init(sc);
532 532 }
533 533
534 534 atomic_and_32(&sc->sc_flags, ~IWH_F_SUSPEND);
535 535
536 536 IWH_DBG((IWH_DEBUG_RESUME, "iwh_attach(): "
537 537 "resume\n"));
538 538 return (DDI_SUCCESS);
539 539
540 540 default:
541 541 goto attach_fail1;
542 542 }
543 543
544 544 instance = ddi_get_instance(dip);
545 545 err = ddi_soft_state_zalloc(iwh_soft_state_p, instance);
546 546 if (err != DDI_SUCCESS) {
547 547 cmn_err(CE_WARN, "iwh_attach(): "
548 548 "failed to allocate soft state\n");
549 549 goto attach_fail1;
550 550 }
551 551
552 552 sc = ddi_get_soft_state(iwh_soft_state_p, instance);
553 553 ASSERT(sc != NULL);
554 554
555 555 sc->sc_dip = dip;
556 556
557 557 /*
558 558 * map configure space
559 559 */
560 560 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0,
561 561 &iwh_reg_accattr, &sc->sc_cfg_handle);
562 562 if (err != DDI_SUCCESS) {
563 563 cmn_err(CE_WARN, "iwh_attach(): "
564 564 "failed to map config spaces regs\n");
565 565 goto attach_fail2;
566 566 }
567 567
568 568 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle,
569 569 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID));
570 570 if ((sc->sc_dev_id != 0x4232) &&
571 571 (sc->sc_dev_id != 0x4235) &&
572 572 (sc->sc_dev_id != 0x4236) &&
573 573 (sc->sc_dev_id != 0x4237) &&
574 574 (sc->sc_dev_id != 0x423a) &&
575 575 (sc->sc_dev_id != 0x423b) &&
576 576 (sc->sc_dev_id != 0x423c) &&
577 577 (sc->sc_dev_id != 0x423d)) {
578 578 cmn_err(CE_WARN, "iwh_attach(): "
579 579 "Do not support this device\n");
580 580 goto attach_fail3;
581 581 }
582 582
583 583 iwh_init_ht_conf(sc);
584 584 iwh_overwrite_11n_rateset(sc);
585 585
586 586 sc->sc_rev = ddi_get8(sc->sc_cfg_handle,
587 587 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID));
588 588
589 589 /*
590 590 * keep from disturbing C3 state of CPU
591 591 */
592 592 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base +
593 593 PCI_CFG_RETRY_TIMEOUT), 0);
594 594
595 595 /*
596 596 * determine the size of buffer for frame and command to ucode
597 597 */
598 598 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle,
599 599 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
600 600 if (!sc->sc_clsz) {
601 601 sc->sc_clsz = 16;
602 602 }
603 603 sc->sc_clsz = (sc->sc_clsz << 2);
604 604
605 605 sc->sc_dmabuf_sz = roundup(0x2000 + sizeof (struct ieee80211_frame) +
606 606 IEEE80211_MTU + IEEE80211_CRC_LEN +
607 607 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN +
608 608 IEEE80211_WEP_CRCLEN), sc->sc_clsz);
609 609
610 610 /*
611 611 * Map operating registers
612 612 */
613 613 err = ddi_regs_map_setup(dip, 1, &sc->sc_base,
614 614 0, 0, &iwh_reg_accattr, &sc->sc_handle);
615 615 if (err != DDI_SUCCESS) {
616 616 cmn_err(CE_WARN, "iwh_attach(): "
617 617 "failed to map device regs\n");
618 618 goto attach_fail3;
619 619 }
620 620
621 621 /*
622 622 * this is used to differentiate type of hardware
623 623 */
624 624 sc->sc_hw_rev = IWH_READ(sc, CSR_HW_REV);
625 625
626 626 err = ddi_intr_get_supported_types(dip, &intr_type);
627 627 if ((err != DDI_SUCCESS) || (!(intr_type & DDI_INTR_TYPE_FIXED))) {
628 628 cmn_err(CE_WARN, "iwh_attach(): "
629 629 "fixed type interrupt is not supported\n");
630 630 goto attach_fail4;
631 631 }
632 632
633 633 err = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &intr_count);
634 634 if ((err != DDI_SUCCESS) || (intr_count != 1)) {
635 635 cmn_err(CE_WARN, "iwh_attach(): "
636 636 "no fixed interrupts\n");
637 637 goto attach_fail4;
638 638 }
639 639
640 640 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
641 641
642 642 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0,
643 643 intr_count, &intr_actual, 0);
644 644 if ((err != DDI_SUCCESS) || (intr_actual != 1)) {
645 645 cmn_err(CE_WARN, "iwh_attach(): "
646 646 "ddi_intr_alloc() failed 0x%x\n", err);
647 647 goto attach_fail5;
648 648 }
649 649
650 650 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
651 651 if (err != DDI_SUCCESS) {
652 652 cmn_err(CE_WARN, "iwh_attach(): "
653 653 "ddi_intr_get_pri() failed 0x%x\n", err);
654 654 goto attach_fail6;
655 655 }
656 656
657 657 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER,
658 658 DDI_INTR_PRI(sc->sc_intr_pri));
659 659 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER,
660 660 DDI_INTR_PRI(sc->sc_intr_pri));
661 661 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER,
662 662 DDI_INTR_PRI(sc->sc_intr_pri));
663 663
664 664 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL);
665 665 cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL);
666 666 cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL);
667 667
668 668 /*
669 669 * initialize the mfthread
670 670 */
671 671 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL);
672 672 sc->sc_mf_thread = NULL;
673 673 sc->sc_mf_thread_switch = 0;
674 674
675 675 /*
676 676 * Allocate shared buffer for communication between driver and ucode.
677 677 */
678 678 err = iwh_alloc_shared(sc);
679 679 if (err != DDI_SUCCESS) {
680 680 cmn_err(CE_WARN, "iwh_attach(): "
681 681 "failed to allocate shared page\n");
682 682 goto attach_fail7;
683 683 }
684 684
685 685 (void) memset(sc->sc_shared, 0, sizeof (iwh_shared_t));
686 686
687 687 /*
688 688 * Allocate keep warm page.
689 689 */
690 690 err = iwh_alloc_kw(sc);
691 691 if (err != DDI_SUCCESS) {
692 692 cmn_err(CE_WARN, "iwh_attach(): "
693 693 "failed to allocate keep warm page\n");
694 694 goto attach_fail8;
695 695 }
696 696
697 697 err = iwh_reset_hw(sc);
698 698 if (err != IWH_SUCCESS) {
699 699 cmn_err(CE_WARN, "iwh_attach(): "
700 700 "failed to reset hardware\n");
701 701 goto attach_fail9;
702 702 }
703 703
704 704 /*
705 705 * Do some necessary hardware initializations.
706 706 */
707 707 err = iwh_preinit(sc);
708 708 if (err != IWH_SUCCESS) {
709 709 cmn_err(CE_WARN, "iwh_attach(): "
710 710 "failed to initialize hardware\n");
711 711 goto attach_fail9;
712 712 }
713 713
714 714 /*
715 715 * get hardware configurations from eeprom
716 716 */
717 717 err = iwh_eep_load(sc);
718 718 if (err != IWH_SUCCESS) {
719 719 cmn_err(CE_WARN, "iwh_attach(): "
720 720 "failed to load eeprom\n");
721 721 goto attach_fail9;
722 722 }
723 723
724 724 if (IWH_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) {
725 725 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_attach(): "
726 726 "unsupported eeprom detected\n"));
727 727 goto attach_fail9;
728 728 }
729 729
730 730 /*
731 731 * get MAC address of this chipset
732 732 */
733 733 iwh_get_mac_from_eep(sc);
734 734
735 735 /*
736 736 * calibration information from EEPROM
737 737 */
738 738 sc->sc_eep_calib = (struct iwh_eep_calibration *)
739 739 iwh_eep_addr_trans(sc, EEP_CALIBRATION);
740 740
741 741 /*
742 742 * initialize TX and RX ring buffers
743 743 */
744 744 err = iwh_ring_init(sc);
745 745 if (err != DDI_SUCCESS) {
746 746 cmn_err(CE_WARN, "iwh_attach(): "
747 747 "failed to allocate and initialize ring\n");
748 748 goto attach_fail9;
749 749 }
750 750
751 751 if ((0x423c == sc->sc_dev_id) || (0x423d == sc->sc_dev_id)) {
752 752 sc->sc_hdr = (iwh_firmware_hdr_t *)iwh_fw_5150_bin;
753 753 } else {
754 754 sc->sc_hdr = (iwh_firmware_hdr_t *)iwh_fw_5000_bin;
755 755 }
756 756
757 757 /*
758 758 * copy ucode to dma buffer
759 759 */
760 760 err = iwh_alloc_fw_dma(sc);
761 761 if (err != DDI_SUCCESS) {
762 762 cmn_err(CE_WARN, "iwh_attach(): "
763 763 "failed to allocate firmware dma\n");
764 764 goto attach_fail10;
765 765 }
766 766
767 767 /*
768 768 * Initialize the wifi part, which will be used by
769 769 * 802.11 module
770 770 */
771 771 ic = &sc->sc_ic;
772 772 ic->ic_phytype = IEEE80211_T_HT;
773 773 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
774 774 ic->ic_state = IEEE80211_S_INIT;
775 775 ic->ic_maxrssi = 100; /* experimental number */
776 776 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT |
777 777 IEEE80211_C_PMGT | IEEE80211_C_SHSLOT;
778 778
779 779 /*
780 780 * Support WPA/WPA2
781 781 */
782 782 ic->ic_caps |= IEEE80211_C_WPA;
783 783
784 784 /*
785 785 * Support QoS/WME
786 786 */
787 787 ic->ic_caps |= IEEE80211_C_WME;
788 788 ic->ic_wme.wme_update = iwh_wme_update;
789 789
790 790 /*
791 791 * Support 802.11n/HT
792 792 */
793 793 if (sc->sc_ht_conf.ht_support) {
794 794 ic->ic_htcaps = IEEE80211_HTC_HT |
795 795 IEEE80211_HTC_AMSDU;
796 796 ic->ic_htcaps |= IEEE80211_HTCAP_MAXAMSDU_7935;
797 797 }
798 798
799 799 /*
800 800 * set supported .11b and .11g rates
801 801 */
802 802 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwh_rateset_11b;
803 803 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwh_rateset_11g;
804 804
805 805 /*
806 806 * set supported .11b and .11g channels (1 through 11)
807 807 */
808 808 for (i = 1; i <= 11; i++) {
809 809 ic->ic_sup_channels[i].ich_freq =
810 810 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
811 811 ic->ic_sup_channels[i].ich_flags =
812 812 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
813 813 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ |
814 814 IEEE80211_CHAN_PASSIVE;
815 815
816 816 if (sc->sc_ht_conf.cap & HT_CAP_SUP_WIDTH) {
817 817 ic->ic_sup_channels[i].ich_flags |=
818 818 IEEE80211_CHAN_HT40;
819 819 } else {
820 820 ic->ic_sup_channels[i].ich_flags |=
821 821 IEEE80211_CHAN_HT20;
822 822 }
823 823 }
824 824
825 825 ic->ic_ibss_chan = &ic->ic_sup_channels[0];
826 826 ic->ic_xmit = iwh_send;
827 827
828 828 /*
829 829 * attach to 802.11 module
830 830 */
831 831 ieee80211_attach(ic);
832 832
833 833 /*
834 834 * different instance has different WPA door
835 835 */
836 836 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR,
837 837 ddi_driver_name(dip),
838 838 ddi_get_instance(dip));
839 839
840 840 /*
841 841 * Overwrite 80211 default configurations.
842 842 */
843 843 iwh_overwrite_ic_default(sc);
844 844
845 845 /*
846 846 * initialize 802.11 module
847 847 */
848 848 ieee80211_media_init(ic);
849 849
850 850 /*
851 851 * initialize default tx key
852 852 */
853 853 ic->ic_def_txkey = 0;
854 854
855 855 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX,
856 856 iwh_rx_softintr, (caddr_t)sc);
857 857 if (err != DDI_SUCCESS) {
858 858 cmn_err(CE_WARN, "iwh_attach(): "
859 859 "add soft interrupt failed\n");
860 860 goto attach_fail12;
861 861 }
862 862
863 863 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwh_intr,
864 864 (caddr_t)sc, NULL);
865 865 if (err != DDI_SUCCESS) {
866 866 cmn_err(CE_WARN, "iwh_attach(): "
867 867 "ddi_intr_add_handle() failed\n");
868 868 goto attach_fail13;
869 869 }
870 870
871 871 err = ddi_intr_enable(sc->sc_intr_htable[0]);
872 872 if (err != DDI_SUCCESS) {
873 873 cmn_err(CE_WARN, "iwh_attach(): "
874 874 "ddi_intr_enable() failed\n");
875 875 goto attach_fail14;
876 876 }
877 877
878 878 /*
879 879 * Initialize pointer to device specific functions
880 880 */
881 881 wd.wd_secalloc = WIFI_SEC_NONE;
882 882 wd.wd_opmode = ic->ic_opmode;
883 883 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_macaddr);
884 884
885 885 /*
886 886 * create relation to GLD
887 887 */
888 888 macp = mac_alloc(MAC_VERSION);
889 889 if (NULL == macp) {
890 890 cmn_err(CE_WARN, "iwh_attach(): "
891 891 "failed to do mac_alloc()\n");
892 892 goto attach_fail15;
893 893 }
894 894
895 895 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
896 896 macp->m_driver = sc;
897 897 macp->m_dip = dip;
898 898 macp->m_src_addr = ic->ic_macaddr;
899 899 macp->m_callbacks = &iwh_m_callbacks;
900 900 macp->m_min_sdu = 0;
901 901 macp->m_max_sdu = IEEE80211_MTU;
902 902 macp->m_pdata = &wd;
903 903 macp->m_pdata_size = sizeof (wd);
904 904
905 905 /*
906 906 * Register the macp to mac
907 907 */
908 908 err = mac_register(macp, &ic->ic_mach);
909 909 mac_free(macp);
910 910 if (err != DDI_SUCCESS) {
911 911 cmn_err(CE_WARN, "iwh_attach(): "
912 912 "failed to do mac_register()\n");
913 913 goto attach_fail15;
914 914 }
915 915
916 916 /*
917 917 * Create minor node of type DDI_NT_NET_WIFI
918 918 */
919 919 (void) snprintf(strbuf, sizeof (strbuf), DRV_NAME_SP"%d", instance);
920 920 err = ddi_create_minor_node(dip, strbuf, S_IFCHR,
921 921 instance + 1, DDI_NT_NET_WIFI, 0);
922 922 if (err != DDI_SUCCESS) {
923 923 cmn_err(CE_WARN, "iwh_attach(): "
924 924 "failed to do ddi_create_minor_node()\n");
925 925 }
926 926
927 927 /*
928 928 * Notify link is down now
929 929 */
930 930 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
931 931
932 932 /*
933 933 * create the mf thread to handle the link status,
934 934 * recovery fatal error, etc.
935 935 */
936 936 sc->sc_mf_thread_switch = 1;
937 937 if (NULL == sc->sc_mf_thread) {
938 938 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0,
939 939 iwh_thread, sc, 0, &p0, TS_RUN, minclsyspri);
940 940 }
941 941
942 942 atomic_or_32(&sc->sc_flags, IWH_F_ATTACHED);
943 943
944 944 return (DDI_SUCCESS);
945 945
946 946 attach_fail15:
947 947 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
948 948
949 949 attach_fail14:
950 950 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
951 951
952 952 attach_fail13:
953 953 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
954 954 sc->sc_soft_hdl = NULL;
955 955
956 956 attach_fail12:
957 957 ieee80211_detach(ic);
958 958
959 959 attach_fail11:
960 960 iwh_free_fw_dma(sc);
961 961
962 962 attach_fail10:
963 963 iwh_ring_free(sc);
964 964
965 965 attach_fail9:
966 966 iwh_free_kw(sc);
967 967
968 968 attach_fail8:
969 969 iwh_free_shared(sc);
970 970
971 971 attach_fail7:
972 972 iwh_destroy_locks(sc);
973 973
974 974 attach_fail6:
975 975 (void) ddi_intr_free(sc->sc_intr_htable[0]);
976 976
977 977 attach_fail5:
978 978 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
979 979
980 980 attach_fail4:
981 981 ddi_regs_map_free(&sc->sc_handle);
982 982
983 983 attach_fail3:
984 984 ddi_regs_map_free(&sc->sc_cfg_handle);
985 985
986 986 attach_fail2:
987 987 ddi_soft_state_free(iwh_soft_state_p, instance);
988 988
989 989 attach_fail1:
990 990 return (DDI_FAILURE);
991 991 }
992 992
993 993 int
994 994 iwh_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
995 995 {
996 996 iwh_sc_t *sc;
997 997 ieee80211com_t *ic;
998 998 int err;
999 999
1000 1000 sc = ddi_get_soft_state(iwh_soft_state_p, ddi_get_instance(dip));
1001 1001 ASSERT(sc != NULL);
1002 1002 ic = &sc->sc_ic;
1003 1003
1004 1004 switch (cmd) {
1005 1005 case DDI_DETACH:
1006 1006 break;
1007 1007
1008 1008 case DDI_SUSPEND:
1009 1009 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
1010 1010 atomic_and_32(&sc->sc_flags, ~IWH_F_RATE_AUTO_CTL);
1011 1011
1012 1012 atomic_or_32(&sc->sc_flags, IWH_F_SUSPEND);
1013 1013
1014 1014 if (sc->sc_flags & IWH_F_RUNNING) {
1015 1015 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1016 1016 iwh_stop(sc);
1017 1017 }
1018 1018
1019 1019 IWH_DBG((IWH_DEBUG_RESUME, "iwh_detach(): "
1020 1020 "suspend\n"));
1021 1021 return (DDI_SUCCESS);
1022 1022
1023 1023 default:
1024 1024 return (DDI_FAILURE);
1025 1025 }
1026 1026
1027 1027 if (!(sc->sc_flags & IWH_F_ATTACHED)) {
1028 1028 return (DDI_FAILURE);
1029 1029 }
1030 1030
1031 1031 /*
1032 1032 * Destroy the mf_thread
1033 1033 */
1034 1034 sc->sc_mf_thread_switch = 0;
1035 1035
1036 1036 mutex_enter(&sc->sc_mt_lock);
1037 1037 while (sc->sc_mf_thread != NULL) {
1038 1038 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) {
1039 1039 break;
1040 1040 }
1041 1041 }
1042 1042 mutex_exit(&sc->sc_mt_lock);
1043 1043
1044 1044 err = mac_disable(sc->sc_ic.ic_mach);
1045 1045 if (err != DDI_SUCCESS) {
1046 1046 return (err);
1047 1047 }
1048 1048
1049 1049 /*
1050 1050 * stop chipset
1051 1051 */
1052 1052 iwh_stop(sc);
1053 1053
1054 1054 DELAY(500000);
1055 1055
1056 1056 /*
1057 1057 * release buffer for calibration
1058 1058 */
1059 1059 iwh_release_calib_buffer(sc);
1060 1060
1061 1061 /*
1062 1062 * Unregiste from GLD
1063 1063 */
1064 1064 (void) mac_unregister(sc->sc_ic.ic_mach);
1065 1065
1066 1066 mutex_enter(&sc->sc_glock);
1067 1067 iwh_free_fw_dma(sc);
1068 1068 iwh_ring_free(sc);
1069 1069 iwh_free_kw(sc);
1070 1070 iwh_free_shared(sc);
1071 1071 mutex_exit(&sc->sc_glock);
1072 1072
1073 1073 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
1074 1074 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
1075 1075 (void) ddi_intr_free(sc->sc_intr_htable[0]);
1076 1076 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
1077 1077
1078 1078 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
1079 1079 sc->sc_soft_hdl = NULL;
1080 1080
1081 1081 /*
1082 1082 * detach from 80211 module
1083 1083 */
1084 1084 ieee80211_detach(&sc->sc_ic);
1085 1085
1086 1086 iwh_destroy_locks(sc);
1087 1087
1088 1088 ddi_regs_map_free(&sc->sc_handle);
1089 1089 ddi_regs_map_free(&sc->sc_cfg_handle);
1090 1090 ddi_remove_minor_node(dip, NULL);
1091 1091 ddi_soft_state_free(iwh_soft_state_p, ddi_get_instance(dip));
1092 1092
1093 1093 return (DDI_SUCCESS);
1094 1094 }
1095 1095
1096 1096 /*
1097 1097 * destroy all locks
1098 1098 */
1099 1099 static void
1100 1100 iwh_destroy_locks(iwh_sc_t *sc)
1101 1101 {
1102 1102 cv_destroy(&sc->sc_mt_cv);
1103 1103 cv_destroy(&sc->sc_cmd_cv);
1104 1104 cv_destroy(&sc->sc_put_seg_cv);
1105 1105 cv_destroy(&sc->sc_ucode_cv);
1106 1106 mutex_destroy(&sc->sc_mt_lock);
1107 1107 mutex_destroy(&sc->sc_tx_lock);
1108 1108 mutex_destroy(&sc->sc_glock);
1109 1109 }
1110 1110
1111 1111 /*
1112 1112 * Allocate an area of memory and a DMA handle for accessing it
1113 1113 */
1114 1114 static int
1115 1115 iwh_alloc_dma_mem(iwh_sc_t *sc, size_t memsize,
1116 1116 ddi_dma_attr_t *dma_attr_p, ddi_device_acc_attr_t *acc_attr_p,
1117 1117 uint_t dma_flags, iwh_dma_t *dma_p)
1118 1118 {
1119 1119 caddr_t vaddr;
1120 1120 int err = DDI_FAILURE;
1121 1121
1122 1122 /*
1123 1123 * Allocate handle
1124 1124 */
1125 1125 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p,
1126 1126 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
1127 1127 if (err != DDI_SUCCESS) {
1128 1128 dma_p->dma_hdl = NULL;
1129 1129 return (DDI_FAILURE);
1130 1130 }
1131 1131
1132 1132 /*
1133 1133 * Allocate memory
1134 1134 */
1135 1135 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, acc_attr_p,
1136 1136 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING),
1137 1137 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl);
1138 1138 if (err != DDI_SUCCESS) {
1139 1139 ddi_dma_free_handle(&dma_p->dma_hdl);
1140 1140 dma_p->dma_hdl = NULL;
1141 1141 dma_p->acc_hdl = NULL;
1142 1142 return (DDI_FAILURE);
1143 1143 }
1144 1144
1145 1145 /*
1146 1146 * Bind the two together
1147 1147 */
1148 1148 dma_p->mem_va = vaddr;
1149 1149 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
1150 1150 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL,
1151 1151 &dma_p->cookie, &dma_p->ncookies);
1152 1152 if (err != DDI_DMA_MAPPED) {
1153 1153 ddi_dma_mem_free(&dma_p->acc_hdl);
1154 1154 ddi_dma_free_handle(&dma_p->dma_hdl);
1155 1155 dma_p->acc_hdl = NULL;
1156 1156 dma_p->dma_hdl = NULL;
1157 1157 return (DDI_FAILURE);
1158 1158 }
1159 1159
1160 1160 dma_p->nslots = ~0U;
1161 1161 dma_p->size = ~0U;
1162 1162 dma_p->token = ~0U;
1163 1163 dma_p->offset = 0;
1164 1164 return (DDI_SUCCESS);
1165 1165 }
1166 1166
1167 1167 /*
1168 1168 * Free one allocated area of DMAable memory
1169 1169 */
1170 1170 static void
1171 1171 iwh_free_dma_mem(iwh_dma_t *dma_p)
1172 1172 {
1173 1173 if (dma_p->dma_hdl != NULL) {
1174 1174 if (dma_p->ncookies) {
1175 1175 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
1176 1176 dma_p->ncookies = 0;
1177 1177 }
1178 1178 ddi_dma_free_handle(&dma_p->dma_hdl);
1179 1179 dma_p->dma_hdl = NULL;
1180 1180 }
1181 1181
1182 1182 if (dma_p->acc_hdl != NULL) {
1183 1183 ddi_dma_mem_free(&dma_p->acc_hdl);
1184 1184 dma_p->acc_hdl = NULL;
1185 1185 }
1186 1186 }
1187 1187
1188 1188 /*
1189 1189 * copy ucode into dma buffers
1190 1190 */
1191 1191 static int
1192 1192 iwh_alloc_fw_dma(iwh_sc_t *sc)
1193 1193 {
1194 1194 int err = DDI_FAILURE;
1195 1195 iwh_dma_t *dma_p;
1196 1196 char *t;
1197 1197
1198 1198 /*
1199 1199 * firmware image layout:
1200 1200 * |HDR|<-TEXT->|<-DATA->|<-INIT_TEXT->|<-INIT_DATA->|<-BOOT->|
1201 1201 */
1202 1202
1203 1203 /*
1204 1204 * copy text of runtime ucode
1205 1205 */
1206 1206 t = (char *)(sc->sc_hdr + 1);
1207 1207 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz),
1208 1208 &fw_dma_attr, &iwh_dma_accattr,
1209 1209 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1210 1210 &sc->sc_dma_fw_text);
1211 1211 if (err != DDI_SUCCESS) {
1212 1212 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1213 1213 "failed to allocate text dma memory.\n");
1214 1214 goto fail;
1215 1215 }
1216 1216
1217 1217 dma_p = &sc->sc_dma_fw_text;
1218 1218
1219 1219 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1220 1220 "text[ncookies:%d addr:%lx size:%lx]\n",
1221 1221 dma_p->ncookies, dma_p->cookie.dmac_address,
1222 1222 dma_p->cookie.dmac_size));
1223 1223
1224 1224 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->textsz));
1225 1225
1226 1226 /*
1227 1227 * copy data and bak-data of runtime ucode
1228 1228 */
1229 1229 t += LE_32(sc->sc_hdr->textsz);
1230 1230 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1231 1231 &fw_dma_attr, &iwh_dma_accattr,
1232 1232 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1233 1233 &sc->sc_dma_fw_data);
1234 1234 if (err != DDI_SUCCESS) {
1235 1235 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1236 1236 "failed to allocate data dma memory\n");
1237 1237 goto fail;
1238 1238 }
1239 1239
1240 1240 dma_p = &sc->sc_dma_fw_data;
1241 1241
1242 1242 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1243 1243 "data[ncookies:%d addr:%lx size:%lx]\n",
1244 1244 dma_p->ncookies, dma_p->cookie.dmac_address,
1245 1245 dma_p->cookie.dmac_size));
1246 1246
1247 1247 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->datasz));
1248 1248
1249 1249 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1250 1250 &fw_dma_attr, &iwh_dma_accattr,
1251 1251 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1252 1252 &sc->sc_dma_fw_data_bak);
1253 1253 if (err != DDI_SUCCESS) {
1254 1254 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1255 1255 "failed to allocate data bakup dma memory\n");
1256 1256 goto fail;
1257 1257 }
1258 1258
1259 1259 dma_p = &sc->sc_dma_fw_data_bak;
1260 1260
1261 1261 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1262 1262 "data_bak[ncookies:%d addr:%lx "
1263 1263 "size:%lx]\n",
1264 1264 dma_p->ncookies, dma_p->cookie.dmac_address,
1265 1265 dma_p->cookie.dmac_size));
1266 1266
1267 1267 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->datasz));
1268 1268
1269 1269 /*
1270 1270 * copy text of init ucode
1271 1271 */
1272 1272 t += LE_32(sc->sc_hdr->datasz);
1273 1273 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz),
1274 1274 &fw_dma_attr, &iwh_dma_accattr,
1275 1275 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1276 1276 &sc->sc_dma_fw_init_text);
1277 1277 if (err != DDI_SUCCESS) {
1278 1278 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1279 1279 "failed to allocate init text dma memory\n");
1280 1280 goto fail;
1281 1281 }
1282 1282
1283 1283 dma_p = &sc->sc_dma_fw_init_text;
1284 1284
1285 1285 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1286 1286 "init_text[ncookies:%d addr:%lx "
1287 1287 "size:%lx]\n",
1288 1288 dma_p->ncookies, dma_p->cookie.dmac_address,
1289 1289 dma_p->cookie.dmac_size));
1290 1290
1291 1291 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->init_textsz));
1292 1292
1293 1293 /*
1294 1294 * copy data of init ucode
1295 1295 */
1296 1296 t += LE_32(sc->sc_hdr->init_textsz);
1297 1297 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz),
1298 1298 &fw_dma_attr, &iwh_dma_accattr,
1299 1299 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1300 1300 &sc->sc_dma_fw_init_data);
1301 1301 if (err != DDI_SUCCESS) {
1302 1302 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1303 1303 "failed to allocate init data dma memory\n");
1304 1304 goto fail;
1305 1305 }
1306 1306
1307 1307 dma_p = &sc->sc_dma_fw_init_data;
1308 1308
1309 1309 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1310 1310 "init_data[ncookies:%d addr:%lx "
1311 1311 "size:%lx]\n",
1312 1312 dma_p->ncookies, dma_p->cookie.dmac_address,
1313 1313 dma_p->cookie.dmac_size));
1314 1314
1315 1315 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->init_datasz));
1316 1316
1317 1317 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz);
1318 1318
1319 1319 fail:
1320 1320 return (err);
1321 1321 }
1322 1322
1323 1323 static void
1324 1324 iwh_free_fw_dma(iwh_sc_t *sc)
1325 1325 {
1326 1326 iwh_free_dma_mem(&sc->sc_dma_fw_text);
1327 1327 iwh_free_dma_mem(&sc->sc_dma_fw_data);
1328 1328 iwh_free_dma_mem(&sc->sc_dma_fw_data_bak);
1329 1329 iwh_free_dma_mem(&sc->sc_dma_fw_init_text);
1330 1330 iwh_free_dma_mem(&sc->sc_dma_fw_init_data);
1331 1331 }
1332 1332
1333 1333 /*
1334 1334 * Allocate a shared buffer between host and NIC.
1335 1335 */
1336 1336 static int
1337 1337 iwh_alloc_shared(iwh_sc_t *sc)
1338 1338 {
1339 1339 #ifdef DEBUG
1340 1340 iwh_dma_t *dma_p;
1341 1341 #endif
1342 1342 int err = DDI_FAILURE;
1343 1343
1344 1344 /*
1345 1345 * must be aligned on a 4K-page boundary
1346 1346 */
1347 1347 err = iwh_alloc_dma_mem(sc, sizeof (iwh_shared_t),
1348 1348 &sh_dma_attr, &iwh_dma_descattr,
1349 1349 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1350 1350 &sc->sc_dma_sh);
1351 1351 if (err != DDI_SUCCESS) {
1352 1352 goto fail;
1353 1353 }
1354 1354
1355 1355 sc->sc_shared = (iwh_shared_t *)sc->sc_dma_sh.mem_va;
1356 1356
1357 1357 #ifdef DEBUG
1358 1358 dma_p = &sc->sc_dma_sh;
1359 1359 #endif
1360 1360 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_shared(): "
1361 1361 "sh[ncookies:%d addr:%lx size:%lx]\n",
1362 1362 dma_p->ncookies, dma_p->cookie.dmac_address,
1363 1363 dma_p->cookie.dmac_size));
1364 1364
1365 1365 return (err);
1366 1366
1367 1367 fail:
1368 1368 iwh_free_shared(sc);
1369 1369 return (err);
1370 1370 }
1371 1371
1372 1372 static void
1373 1373 iwh_free_shared(iwh_sc_t *sc)
1374 1374 {
1375 1375 iwh_free_dma_mem(&sc->sc_dma_sh);
1376 1376 }
1377 1377
1378 1378 /*
1379 1379 * Allocate a keep warm page.
1380 1380 */
1381 1381 static int
1382 1382 iwh_alloc_kw(iwh_sc_t *sc)
1383 1383 {
1384 1384 #ifdef DEBUG
1385 1385 iwh_dma_t *dma_p;
1386 1386 #endif
1387 1387 int err = DDI_FAILURE;
1388 1388
1389 1389 /*
1390 1390 * must be aligned on a 4K-page boundary
1391 1391 */
1392 1392 err = iwh_alloc_dma_mem(sc, IWH_KW_SIZE,
1393 1393 &kw_dma_attr, &iwh_dma_descattr,
1394 1394 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1395 1395 &sc->sc_dma_kw);
1396 1396 if (err != DDI_SUCCESS) {
1397 1397 goto fail;
1398 1398 }
1399 1399
1400 1400 #ifdef DEBUG
1401 1401 dma_p = &sc->sc_dma_kw;
1402 1402 #endif
1403 1403 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_kw(): "
1404 1404 "kw[ncookies:%d addr:%lx size:%lx]\n",
1405 1405 dma_p->ncookies, dma_p->cookie.dmac_address,
1406 1406 dma_p->cookie.dmac_size));
1407 1407
1408 1408 return (err);
1409 1409
1410 1410 fail:
1411 1411 iwh_free_kw(sc);
1412 1412 return (err);
1413 1413 }
1414 1414
1415 1415 static void
1416 1416 iwh_free_kw(iwh_sc_t *sc)
1417 1417 {
1418 1418 iwh_free_dma_mem(&sc->sc_dma_kw);
1419 1419 }
1420 1420
1421 1421 /*
1422 1422 * initialize RX ring buffers
1423 1423 */
1424 1424 static int
1425 1425 iwh_alloc_rx_ring(iwh_sc_t *sc)
1426 1426 {
1427 1427 iwh_rx_ring_t *ring;
1428 1428 iwh_rx_data_t *data;
1429 1429 #ifdef DEBUG
1430 1430 iwh_dma_t *dma_p;
1431 1431 #endif
1432 1432 int i, err = DDI_FAILURE;
1433 1433
1434 1434 ring = &sc->sc_rxq;
1435 1435 ring->cur = 0;
1436 1436
1437 1437 /*
1438 1438 * allocate RX description ring buffer
1439 1439 */
1440 1440 err = iwh_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t),
1441 1441 &ring_desc_dma_attr, &iwh_dma_descattr,
1442 1442 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1443 1443 &ring->dma_desc);
1444 1444 if (err != DDI_SUCCESS) {
1445 1445 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1446 1446 "dma alloc rx ring desc "
1447 1447 "failed\n"));
1448 1448 goto fail;
1449 1449 }
1450 1450
1451 1451 ring->desc = (uint32_t *)ring->dma_desc.mem_va;
1452 1452 #ifdef DEBUG
1453 1453 dma_p = &ring->dma_desc;
1454 1454 #endif
1455 1455 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1456 1456 "rx bd[ncookies:%d addr:%lx size:%lx]\n",
1457 1457 dma_p->ncookies, dma_p->cookie.dmac_address,
1458 1458 dma_p->cookie.dmac_size));
1459 1459
1460 1460 /*
1461 1461 * Allocate Rx frame buffers.
1462 1462 */
1463 1463 for (i = 0; i < RX_QUEUE_SIZE; i++) {
1464 1464 data = &ring->data[i];
1465 1465 err = iwh_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1466 1466 &rx_buffer_dma_attr, &iwh_dma_accattr,
1467 1467 DDI_DMA_READ | DDI_DMA_STREAMING,
1468 1468 &data->dma_data);
1469 1469 if (err != DDI_SUCCESS) {
1470 1470 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1471 1471 "dma alloc rx ring "
1472 1472 "buf[%d] failed\n", i));
1473 1473 goto fail;
1474 1474 }
1475 1475 /*
1476 1476 * the physical address bit [8-36] are used,
1477 1477 * instead of bit [0-31] in 3945.
1478 1478 */
1479 1479 ring->desc[i] = (uint32_t)
1480 1480 (data->dma_data.cookie.dmac_address >> 8);
1481 1481 }
1482 1482
1483 1483 #ifdef DEBUG
1484 1484 dma_p = &ring->data[0].dma_data;
1485 1485 #endif
1486 1486 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1487 1487 "rx buffer[0][ncookies:%d addr:%lx "
1488 1488 "size:%lx]\n",
1489 1489 dma_p->ncookies, dma_p->cookie.dmac_address,
1490 1490 dma_p->cookie.dmac_size));
1491 1491
1492 1492 IWH_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
1493 1493
1494 1494 return (err);
1495 1495
1496 1496 fail:
1497 1497 iwh_free_rx_ring(sc);
1498 1498 return (err);
1499 1499 }
1500 1500
1501 1501 /*
1502 1502 * disable RX ring
1503 1503 */
1504 1504 static void
1505 1505 iwh_reset_rx_ring(iwh_sc_t *sc)
1506 1506 {
1507 1507 int n;
1508 1508
1509 1509 iwh_mac_access_enter(sc);
1510 1510 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
1511 1511 for (n = 0; n < 2000; n++) {
1512 1512 if (IWH_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) {
1513 1513 break;
1514 1514 }
1515 1515 DELAY(1000);
1516 1516 }
1517 1517 #ifdef DEBUG
1518 1518 if (2000 == n) {
1519 1519 IWH_DBG((IWH_DEBUG_DMA, "iwh_reset_rx_ring(): "
1520 1520 "timeout resetting Rx ring\n"));
1521 1521 }
1522 1522 #endif
1523 1523 iwh_mac_access_exit(sc);
1524 1524
1525 1525 sc->sc_rxq.cur = 0;
1526 1526 }
1527 1527
1528 1528 static void
1529 1529 iwh_free_rx_ring(iwh_sc_t *sc)
1530 1530 {
1531 1531 int i;
1532 1532
1533 1533 for (i = 0; i < RX_QUEUE_SIZE; i++) {
1534 1534 if (sc->sc_rxq.data[i].dma_data.dma_hdl) {
1535 1535 IWH_DMA_SYNC(sc->sc_rxq.data[i].dma_data,
1536 1536 DDI_DMA_SYNC_FORCPU);
1537 1537 }
1538 1538
1539 1539 iwh_free_dma_mem(&sc->sc_rxq.data[i].dma_data);
1540 1540 }
1541 1541
1542 1542 if (sc->sc_rxq.dma_desc.dma_hdl) {
1543 1543 IWH_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV);
1544 1544 }
1545 1545
1546 1546 iwh_free_dma_mem(&sc->sc_rxq.dma_desc);
1547 1547 }
1548 1548
1549 1549 /*
1550 1550 * initialize TX ring buffers
1551 1551 */
1552 1552 static int
1553 1553 iwh_alloc_tx_ring(iwh_sc_t *sc, iwh_tx_ring_t *ring,
1554 1554 int slots, int qid)
1555 1555 {
1556 1556 iwh_tx_data_t *data;
1557 1557 iwh_tx_desc_t *desc_h;
1558 1558 uint32_t paddr_desc_h;
1559 1559 iwh_cmd_t *cmd_h;
1560 1560 uint32_t paddr_cmd_h;
1561 1561 #ifdef DEBUG
1562 1562 iwh_dma_t *dma_p;
1563 1563 #endif
1564 1564 int i, err = DDI_FAILURE;
1565 1565
1566 1566 ring->qid = qid;
1567 1567 ring->count = TFD_QUEUE_SIZE_MAX;
1568 1568 ring->window = slots;
1569 1569 ring->queued = 0;
1570 1570 ring->cur = 0;
1571 1571 ring->desc_cur = 0;
1572 1572
1573 1573 /*
1574 1574 * allocate buffer for TX descriptor ring
1575 1575 */
1576 1576 err = iwh_alloc_dma_mem(sc,
1577 1577 TFD_QUEUE_SIZE_MAX * sizeof (iwh_tx_desc_t),
1578 1578 &ring_desc_dma_attr, &iwh_dma_descattr,
1579 1579 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1580 1580 &ring->dma_desc);
1581 1581 if (err != DDI_SUCCESS) {
1582 1582 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1583 1583 "dma alloc tx ring desc[%d] "
1584 1584 "failed\n", qid));
1585 1585 goto fail;
1586 1586 }
1587 1587
1588 1588 #ifdef DEBUG
1589 1589 dma_p = &ring->dma_desc;
1590 1590 #endif
1591 1591 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1592 1592 "tx bd[ncookies:%d addr:%lx size:%lx]\n",
1593 1593 dma_p->ncookies, dma_p->cookie.dmac_address,
1594 1594 dma_p->cookie.dmac_size));
1595 1595
1596 1596 desc_h = (iwh_tx_desc_t *)ring->dma_desc.mem_va;
1597 1597 paddr_desc_h = ring->dma_desc.cookie.dmac_address;
1598 1598
1599 1599 /*
1600 1600 * allocate buffer for ucode command
1601 1601 */
1602 1602 err = iwh_alloc_dma_mem(sc,
1603 1603 TFD_QUEUE_SIZE_MAX * sizeof (iwh_cmd_t),
1604 1604 &cmd_dma_attr, &iwh_dma_accattr,
1605 1605 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1606 1606 &ring->dma_cmd);
1607 1607 if (err != DDI_SUCCESS) {
1608 1608 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1609 1609 "dma alloc tx ring cmd[%d]"
1610 1610 " failed\n", qid));
1611 1611 goto fail;
1612 1612 }
1613 1613
1614 1614 #ifdef DEBUG
1615 1615 dma_p = &ring->dma_cmd;
1616 1616 #endif
1617 1617 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1618 1618 "tx cmd[ncookies:%d addr:%lx size:%lx]\n",
1619 1619 dma_p->ncookies, dma_p->cookie.dmac_address,
1620 1620 dma_p->cookie.dmac_size));
1621 1621
1622 1622 cmd_h = (iwh_cmd_t *)ring->dma_cmd.mem_va;
1623 1623 paddr_cmd_h = ring->dma_cmd.cookie.dmac_address;
1624 1624
1625 1625 /*
1626 1626 * Allocate Tx frame buffers.
1627 1627 */
1628 1628 ring->data = kmem_zalloc(sizeof (iwh_tx_data_t) * TFD_QUEUE_SIZE_MAX,
1629 1629 KM_NOSLEEP);
1630 1630 if (NULL == ring->data) {
1631 1631 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1632 1632 "could not allocate "
1633 1633 "tx data slots\n"));
1634 1634 goto fail;
1635 1635 }
1636 1636
1637 1637 for (i = 0; i < TFD_QUEUE_SIZE_MAX; i++) {
1638 1638 data = &ring->data[i];
1639 1639 err = iwh_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1640 1640 &tx_buffer_dma_attr, &iwh_dma_accattr,
1641 1641 DDI_DMA_WRITE | DDI_DMA_STREAMING,
1642 1642 &data->dma_data);
1643 1643 if (err != DDI_SUCCESS) {
1644 1644 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1645 1645 "dma alloc tx "
1646 1646 "ring buf[%d] failed\n", i));
1647 1647 goto fail;
1648 1648 }
1649 1649
1650 1650 data->desc = desc_h + i;
1651 1651 data->paddr_desc = paddr_desc_h +
1652 1652 _PTRDIFF(data->desc, desc_h);
1653 1653 data->cmd = cmd_h + i;
1654 1654 data->paddr_cmd = paddr_cmd_h +
1655 1655 _PTRDIFF(data->cmd, cmd_h);
1656 1656 }
1657 1657 #ifdef DEBUG
1658 1658 dma_p = &ring->data[0].dma_data;
1659 1659 #endif
1660 1660 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1661 1661 "tx buffer[0][ncookies:%d addr:%lx "
1662 1662 "size:%lx]\n",
1663 1663 dma_p->ncookies, dma_p->cookie.dmac_address,
1664 1664 dma_p->cookie.dmac_size));
1665 1665
1666 1666 return (err);
1667 1667
1668 1668 fail:
1669 1669 iwh_free_tx_ring(ring);
1670 1670
1671 1671 return (err);
1672 1672 }
1673 1673
1674 1674 /*
1675 1675 * disable TX ring
1676 1676 */
1677 1677 static void
1678 1678 iwh_reset_tx_ring(iwh_sc_t *sc, iwh_tx_ring_t *ring)
1679 1679 {
1680 1680 iwh_tx_data_t *data;
1681 1681 int i, n;
1682 1682
1683 1683 iwh_mac_access_enter(sc);
1684 1684
1685 1685 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
1686 1686 for (n = 0; n < 200; n++) {
1687 1687 if (IWH_READ(sc, IWH_FH_TSSR_TX_STATUS_REG) &
1688 1688 IWH_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ring->qid)) {
1689 1689 break;
1690 1690 }
1691 1691 DELAY(10);
1692 1692 }
1693 1693
1694 1694 #ifdef DEBUG
1695 1695 if (200 == n) {
1696 1696 IWH_DBG((IWH_DEBUG_DMA, "iwh_reset_tx_ring(): "
1697 1697 "timeout reset tx ring %d\n",
1698 1698 ring->qid));
1699 1699 }
1700 1700 #endif
1701 1701
1702 1702 iwh_mac_access_exit(sc);
1703 1703
1704 1704 /*
1705 1705 * by pass, if it's quiesce
1706 1706 */
1707 1707 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
1708 1708 for (i = 0; i < ring->count; i++) {
1709 1709 data = &ring->data[i];
1710 1710 IWH_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV);
1711 1711 }
1712 1712 }
1713 1713
1714 1714 ring->queued = 0;
1715 1715 ring->cur = 0;
1716 1716 ring->desc_cur = 0;
1717 1717 }
1718 1718
1719 1719 static void
1720 1720 iwh_free_tx_ring(iwh_tx_ring_t *ring)
1721 1721 {
1722 1722 int i;
1723 1723
1724 1724 if (ring->dma_desc.dma_hdl != NULL) {
1725 1725 IWH_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
1726 1726 }
1727 1727 iwh_free_dma_mem(&ring->dma_desc);
1728 1728
1729 1729 if (ring->dma_cmd.dma_hdl != NULL) {
1730 1730 IWH_DMA_SYNC(ring->dma_cmd, DDI_DMA_SYNC_FORDEV);
1731 1731 }
1732 1732 iwh_free_dma_mem(&ring->dma_cmd);
1733 1733
1734 1734 if (ring->data != NULL) {
1735 1735 for (i = 0; i < ring->count; i++) {
1736 1736 if (ring->data[i].dma_data.dma_hdl) {
1737 1737 IWH_DMA_SYNC(ring->data[i].dma_data,
1738 1738 DDI_DMA_SYNC_FORDEV);
1739 1739 }
1740 1740 iwh_free_dma_mem(&ring->data[i].dma_data);
1741 1741 }
1742 1742 kmem_free(ring->data, ring->count * sizeof (iwh_tx_data_t));
1743 1743 }
1744 1744 }
1745 1745
1746 1746 /*
1747 1747 * initialize TX and RX ring
1748 1748 */
1749 1749 static int
1750 1750 iwh_ring_init(iwh_sc_t *sc)
1751 1751 {
1752 1752 int i, err = DDI_FAILURE;
1753 1753
1754 1754 for (i = 0; i < IWH_NUM_QUEUES; i++) {
1755 1755 if (IWH_CMD_QUEUE_NUM == i) {
1756 1756 continue;
1757 1757 }
1758 1758
1759 1759 err = iwh_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS,
1760 1760 i);
1761 1761 if (err != DDI_SUCCESS) {
1762 1762 goto fail;
1763 1763 }
1764 1764 }
1765 1765
1766 1766 /*
1767 1767 * initialize command queue
1768 1768 */
1769 1769 err = iwh_alloc_tx_ring(sc, &sc->sc_txq[IWH_CMD_QUEUE_NUM],
1770 1770 TFD_CMD_SLOTS, IWH_CMD_QUEUE_NUM);
1771 1771 if (err != DDI_SUCCESS) {
1772 1772 goto fail;
1773 1773 }
1774 1774
1775 1775 err = iwh_alloc_rx_ring(sc);
1776 1776 if (err != DDI_SUCCESS) {
1777 1777 goto fail;
1778 1778 }
1779 1779
1780 1780 fail:
1781 1781 return (err);
1782 1782 }
1783 1783
1784 1784 static void
1785 1785 iwh_ring_free(iwh_sc_t *sc)
1786 1786 {
1787 1787 int i = IWH_NUM_QUEUES;
1788 1788
1789 1789 iwh_free_rx_ring(sc);
1790 1790 while (--i >= 0) {
1791 1791 iwh_free_tx_ring(&sc->sc_txq[i]);
↓ open down ↓ |
1791 lines elided |
↑ open up ↑ |
1792 1792 }
1793 1793 }
1794 1794
1795 1795 /* ARGSUSED */
1796 1796 static ieee80211_node_t *
1797 1797 iwh_node_alloc(ieee80211com_t *ic)
1798 1798 {
1799 1799 iwh_amrr_t *amrr;
1800 1800
1801 1801 amrr = kmem_zalloc(sizeof (iwh_amrr_t), KM_SLEEP);
1802 - if (NULL == amrr) {
1803 - cmn_err(CE_WARN, "iwh_node_alloc(): "
1804 - "failed to allocate memory for amrr structure\n");
1805 - return (NULL);
1806 - }
1807 1802
1808 1803 iwh_amrr_init(amrr);
1809 1804
1810 1805 return (&amrr->in);
1811 1806 }
1812 1807
1813 1808 static void
1814 1809 iwh_node_free(ieee80211_node_t *in)
1815 1810 {
1816 1811 ieee80211com_t *ic;
1817 1812
1818 1813 if ((NULL == in) ||
1819 1814 (NULL == in->in_ic)) {
1820 1815 cmn_err(CE_WARN, "iwh_node_free() "
1821 1816 "Got a NULL point from Net80211 module\n");
1822 1817 return;
1823 1818 }
1824 1819 ic = in->in_ic;
1825 1820
1826 1821 if (ic->ic_node_cleanup != NULL) {
1827 1822 ic->ic_node_cleanup(in);
1828 1823 }
1829 1824
1830 1825 if (in->in_wpa_ie != NULL) {
1831 1826 ieee80211_free(in->in_wpa_ie);
1832 1827 }
1833 1828
1834 1829 if (in->in_wme_ie != NULL) {
1835 1830 ieee80211_free(in->in_wme_ie);
1836 1831 }
1837 1832
1838 1833 if (in->in_htcap_ie != NULL) {
1839 1834 ieee80211_free(in->in_htcap_ie);
1840 1835 }
1841 1836
1842 1837 kmem_free(in, sizeof (iwh_amrr_t));
1843 1838 }
1844 1839
1845 1840 /*
1846 1841 * change station's state. this function will be invoked by 80211 module
1847 1842 * when need to change staton's state.
1848 1843 */
1849 1844 static int
1850 1845 iwh_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg)
1851 1846 {
1852 1847 iwh_sc_t *sc;
1853 1848 ieee80211_node_t *in;
1854 1849 enum ieee80211_state ostate;
1855 1850 iwh_add_sta_t node;
1856 1851 iwh_amrr_t *amrr;
1857 1852 uint8_t r;
1858 1853 int i, err = IWH_FAIL;
1859 1854
1860 1855 if (NULL == ic) {
1861 1856 return (err);
1862 1857 }
1863 1858 sc = (iwh_sc_t *)ic;
1864 1859 in = ic->ic_bss;
1865 1860 ostate = ic->ic_state;
1866 1861
1867 1862 mutex_enter(&sc->sc_glock);
1868 1863
1869 1864 switch (nstate) {
1870 1865 case IEEE80211_S_SCAN:
1871 1866 switch (ostate) {
1872 1867 case IEEE80211_S_INIT:
1873 1868 atomic_or_32(&sc->sc_flags, IWH_F_SCANNING);
1874 1869 iwh_set_led(sc, 2, 10, 2);
1875 1870
1876 1871 /*
1877 1872 * clear association to receive beacons from
1878 1873 * all BSS'es
1879 1874 */
1880 1875 sc->sc_config.assoc_id = 0;
1881 1876 sc->sc_config.filter_flags &=
1882 1877 ~LE_32(RXON_FILTER_ASSOC_MSK);
1883 1878
1884 1879 IWH_DBG((IWH_DEBUG_80211, "iwh_newstate(): "
1885 1880 "config chan %d "
1886 1881 "flags %x filter_flags %x\n",
1887 1882 LE_16(sc->sc_config.chan),
1888 1883 LE_32(sc->sc_config.flags),
1889 1884 LE_32(sc->sc_config.filter_flags)));
1890 1885
1891 1886 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
1892 1887 sizeof (iwh_rxon_cmd_t), 1);
1893 1888 if (err != IWH_SUCCESS) {
1894 1889 cmn_err(CE_WARN, "iwh_newstate(): "
1895 1890 "could not clear association\n");
1896 1891 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1897 1892 mutex_exit(&sc->sc_glock);
1898 1893 return (err);
1899 1894 }
1900 1895
1901 1896 /*
1902 1897 * add broadcast node to send probe request
1903 1898 */
1904 1899 (void) memset(&node, 0, sizeof (node));
1905 1900 (void) memset(&node.sta.addr, 0xff, IEEE80211_ADDR_LEN);
1906 1901 node.sta.sta_id = IWH_BROADCAST_ID;
1907 1902 err = iwh_cmd(sc, REPLY_ADD_STA, &node,
1908 1903 sizeof (node), 1);
1909 1904 if (err != IWH_SUCCESS) {
1910 1905 cmn_err(CE_WARN, "iwh_newstate(): "
1911 1906 "could not add broadcast node\n");
1912 1907 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1913 1908 mutex_exit(&sc->sc_glock);
1914 1909 return (err);
1915 1910 }
1916 1911 break;
1917 1912 case IEEE80211_S_SCAN:
1918 1913 mutex_exit(&sc->sc_glock);
1919 1914 /* step to next channel before actual FW scan */
1920 1915 err = sc->sc_newstate(ic, nstate, arg);
1921 1916 mutex_enter(&sc->sc_glock);
1922 1917 if ((err != 0) || ((err = iwh_scan(sc)) != 0)) {
1923 1918 cmn_err(CE_WARN, "iwh_newstate(): "
1924 1919 "could not initiate scan\n");
1925 1920 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1926 1921 ieee80211_cancel_scan(ic);
1927 1922 }
1928 1923 mutex_exit(&sc->sc_glock);
1929 1924 return (err);
1930 1925 default:
1931 1926 break;
1932 1927 }
1933 1928 sc->sc_clk = 0;
1934 1929 break;
1935 1930
1936 1931 case IEEE80211_S_AUTH:
1937 1932 if (ostate == IEEE80211_S_SCAN) {
1938 1933 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1939 1934 }
1940 1935
1941 1936 /*
1942 1937 * reset state to handle reassociations correctly
1943 1938 */
1944 1939 sc->sc_config.assoc_id = 0;
1945 1940 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
1946 1941
1947 1942 /*
1948 1943 * before sending authentication and association request frame,
1949 1944 * we need do something in the hardware, such as setting the
1950 1945 * channel same to the target AP...
1951 1946 */
1952 1947 if ((err = iwh_hw_set_before_auth(sc)) != 0) {
1953 1948 IWH_DBG((IWH_DEBUG_80211, "iwh_newstate(): "
1954 1949 "could not send authentication request\n"));
1955 1950 mutex_exit(&sc->sc_glock);
1956 1951 return (err);
1957 1952 }
1958 1953 break;
1959 1954
1960 1955 case IEEE80211_S_RUN:
1961 1956 if (ostate == IEEE80211_S_SCAN) {
1962 1957 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1963 1958 }
1964 1959
1965 1960 if (IEEE80211_M_MONITOR == ic->ic_opmode) {
1966 1961 /*
1967 1962 * let LED blink when monitoring
1968 1963 */
1969 1964 iwh_set_led(sc, 2, 10, 10);
1970 1965 break;
1971 1966 }
1972 1967
1973 1968 IWH_DBG((IWH_DEBUG_80211, "iwh_newstate(): "
1974 1969 "associated.\n"));
1975 1970
1976 1971 err = iwh_run_state_config(sc);
1977 1972 if (err != IWH_SUCCESS) {
1978 1973 cmn_err(CE_WARN, "iwh_newstate(): "
1979 1974 "failed to set up association\n");
1980 1975 mutex_exit(&sc->sc_glock);
1981 1976 return (err);
1982 1977 }
1983 1978
1984 1979 /*
1985 1980 * start automatic rate control
1986 1981 */
1987 1982 if ((in->in_flags & IEEE80211_NODE_HT) &&
1988 1983 (sc->sc_ht_conf.ht_support) &&
1989 1984 (in->in_htrates.rs_nrates > 0) &&
1990 1985 (in->in_htrates.rs_nrates <= IEEE80211_HTRATE_MAXSIZE)) {
1991 1986 amrr = (iwh_amrr_t *)in;
1992 1987
1993 1988 for (i = in->in_htrates.rs_nrates - 1; i > 0; i--) {
1994 1989
1995 1990 r = in->in_htrates.rs_rates[i] &
1996 1991 IEEE80211_RATE_VAL;
1997 1992 if ((r != 0) && (r <= 0xd) &&
1998 1993 (sc->sc_ht_conf.tx_support_mcs[r/8] &
1999 1994 (1 << (r%8)))) {
2000 1995 amrr->ht_mcs_idx = r;
2001 1996 atomic_or_32(&sc->sc_flags,
2002 1997 IWH_F_RATE_AUTO_CTL);
2003 1998 break;
2004 1999 }
2005 2000 }
2006 2001 } else {
2007 2002 if (IEEE80211_FIXED_RATE_NONE == ic->ic_fixed_rate) {
2008 2003 atomic_or_32(&sc->sc_flags,
2009 2004 IWH_F_RATE_AUTO_CTL);
2010 2005
2011 2006 /*
2012 2007 * set rate to some reasonable initial value
2013 2008 */
2014 2009 i = in->in_rates.ir_nrates - 1;
2015 2010 while (i > 0 && IEEE80211_RATE(i) > 72) {
2016 2011 i--;
2017 2012 }
2018 2013 in->in_txrate = i;
2019 2014
2020 2015 } else {
2021 2016 atomic_and_32(&sc->sc_flags,
2022 2017 ~IWH_F_RATE_AUTO_CTL);
2023 2018 }
2024 2019 }
2025 2020
2026 2021 /*
2027 2022 * set LED on after associated
2028 2023 */
2029 2024 iwh_set_led(sc, 2, 0, 1);
2030 2025 break;
2031 2026
2032 2027 case IEEE80211_S_INIT:
2033 2028 if (ostate == IEEE80211_S_SCAN) {
2034 2029 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
2035 2030 }
2036 2031 /*
2037 2032 * set LED off after init
2038 2033 */
2039 2034 iwh_set_led(sc, 2, 1, 0);
2040 2035 break;
2041 2036
2042 2037 case IEEE80211_S_ASSOC:
2043 2038 if (ostate == IEEE80211_S_SCAN) {
2044 2039 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
2045 2040 }
2046 2041 break;
2047 2042 }
2048 2043
2049 2044 mutex_exit(&sc->sc_glock);
2050 2045
2051 2046 return (sc->sc_newstate(ic, nstate, arg));
2052 2047 }
2053 2048
2054 2049 /*
2055 2050 * exclusive access to mac begin.
2056 2051 */
2057 2052 static void
2058 2053 iwh_mac_access_enter(iwh_sc_t *sc)
2059 2054 {
2060 2055 uint32_t tmp;
2061 2056 int n;
2062 2057
2063 2058 tmp = IWH_READ(sc, CSR_GP_CNTRL);
2064 2059 IWH_WRITE(sc, CSR_GP_CNTRL,
2065 2060 tmp | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2066 2061
2067 2062 /*
2068 2063 * wait until we succeed
2069 2064 */
2070 2065 for (n = 0; n < 1000; n++) {
2071 2066 if ((IWH_READ(sc, CSR_GP_CNTRL) &
2072 2067 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2073 2068 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP)) ==
2074 2069 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN) {
2075 2070 break;
2076 2071 }
2077 2072 DELAY(10);
2078 2073 }
2079 2074
2080 2075 #ifdef DEBUG
2081 2076 if (1000 == n) {
2082 2077 IWH_DBG((IWH_DEBUG_PIO, "iwh_mac_access_enter(): "
2083 2078 "could not lock memory\n"));
2084 2079 }
2085 2080 #endif
2086 2081 }
2087 2082
2088 2083 /*
2089 2084 * exclusive access to mac end.
2090 2085 */
2091 2086 static void
2092 2087 iwh_mac_access_exit(iwh_sc_t *sc)
2093 2088 {
2094 2089 uint32_t tmp = IWH_READ(sc, CSR_GP_CNTRL);
2095 2090 IWH_WRITE(sc, CSR_GP_CNTRL,
2096 2091 tmp & ~CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2097 2092 }
2098 2093
2099 2094 /*
2100 2095 * this function defined here for future use.
2101 2096 * static uint32_t
2102 2097 * iwh_mem_read(iwh_sc_t *sc, uint32_t addr)
2103 2098 * {
2104 2099 * IWH_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
2105 2100 * return (IWH_READ(sc, HBUS_TARG_MEM_RDAT));
2106 2101 * }
2107 2102 */
2108 2103
2109 2104 /*
2110 2105 * write mac memory
2111 2106 */
2112 2107 static void
2113 2108 iwh_mem_write(iwh_sc_t *sc, uint32_t addr, uint32_t data)
2114 2109 {
2115 2110 IWH_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
2116 2111 IWH_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
2117 2112 }
2118 2113
2119 2114 /*
2120 2115 * read mac register
2121 2116 */
2122 2117 static uint32_t
2123 2118 iwh_reg_read(iwh_sc_t *sc, uint32_t addr)
2124 2119 {
2125 2120 IWH_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
2126 2121 return (IWH_READ(sc, HBUS_TARG_PRPH_RDAT));
2127 2122 }
2128 2123
2129 2124 /*
2130 2125 * write mac register
2131 2126 */
2132 2127 static void
2133 2128 iwh_reg_write(iwh_sc_t *sc, uint32_t addr, uint32_t data)
2134 2129 {
2135 2130 IWH_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
2136 2131 IWH_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
2137 2132 }
2138 2133
2139 2134
2140 2135 /*
2141 2136 * steps of loading ucode:
2142 2137 * load init ucode=>init alive=>calibrate=>
2143 2138 * receive calibration result=>reinitialize NIC=>
2144 2139 * load runtime ucode=>runtime alive=>
2145 2140 * send calibration result=>running.
2146 2141 */
2147 2142 static int
2148 2143 iwh_load_init_firmware(iwh_sc_t *sc)
2149 2144 {
2150 2145 int err = IWH_FAIL;
2151 2146 clock_t clk;
2152 2147
2153 2148 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2154 2149
2155 2150 /*
2156 2151 * load init_text section of uCode to hardware
2157 2152 */
2158 2153 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address,
2159 2154 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size);
2160 2155 if (err != IWH_SUCCESS) {
2161 2156 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2162 2157 "failed to write init uCode.\n");
2163 2158 return (err);
2164 2159 }
2165 2160
2166 2161 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2167 2162
2168 2163 /*
2169 2164 * wait loading init_text until completed or timeout
2170 2165 */
2171 2166 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2172 2167 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2173 2168 break;
2174 2169 }
2175 2170 }
2176 2171
2177 2172 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2178 2173 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2179 2174 "timeout waiting for init uCode load.\n");
2180 2175 return (IWH_FAIL);
2181 2176 }
2182 2177
2183 2178 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2184 2179
2185 2180 /*
2186 2181 * load init_data section of uCode to hardware
2187 2182 */
2188 2183 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address,
2189 2184 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size);
2190 2185 if (err != IWH_SUCCESS) {
2191 2186 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2192 2187 "failed to write init_data uCode.\n");
2193 2188 return (err);
2194 2189 }
2195 2190
2196 2191 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2197 2192
2198 2193 /*
2199 2194 * wait loading init_data until completed or timeout
2200 2195 */
2201 2196 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2202 2197 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2203 2198 break;
2204 2199 }
2205 2200 }
2206 2201
2207 2202 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2208 2203 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2209 2204 "timeout waiting for init_data uCode load.\n");
2210 2205 return (IWH_FAIL);
2211 2206 }
2212 2207
2213 2208 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2214 2209
2215 2210 return (err);
2216 2211 }
2217 2212
2218 2213 static int
2219 2214 iwh_load_run_firmware(iwh_sc_t *sc)
2220 2215 {
2221 2216 int err = IWH_FAIL;
2222 2217 clock_t clk;
2223 2218
2224 2219 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2225 2220
2226 2221 /*
2227 2222 * load init_text section of uCode to hardware
2228 2223 */
2229 2224 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address,
2230 2225 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size);
2231 2226 if (err != IWH_SUCCESS) {
2232 2227 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2233 2228 "failed to write run uCode.\n");
2234 2229 return (err);
2235 2230 }
2236 2231
2237 2232 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2238 2233
2239 2234 /*
2240 2235 * wait loading run_text until completed or timeout
2241 2236 */
2242 2237 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2243 2238 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2244 2239 break;
2245 2240 }
2246 2241 }
2247 2242
2248 2243 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2249 2244 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2250 2245 "timeout waiting for run uCode load.\n");
2251 2246 return (IWH_FAIL);
2252 2247 }
2253 2248
2254 2249 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2255 2250
2256 2251 /*
2257 2252 * load run_data section of uCode to hardware
2258 2253 */
2259 2254 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address,
2260 2255 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size);
2261 2256 if (err != IWH_SUCCESS) {
2262 2257 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2263 2258 "failed to write run_data uCode.\n");
2264 2259 return (err);
2265 2260 }
2266 2261
2267 2262 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2268 2263
2269 2264 /*
2270 2265 * wait loading run_data until completed or timeout
2271 2266 */
2272 2267 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2273 2268 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2274 2269 break;
2275 2270 }
2276 2271 }
2277 2272
2278 2273 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2279 2274 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2280 2275 "timeout waiting for run_data uCode load.\n");
2281 2276 return (IWH_FAIL);
2282 2277 }
2283 2278
2284 2279 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2285 2280
2286 2281 return (err);
2287 2282 }
2288 2283
2289 2284 /*
2290 2285 * this function will be invoked to receive phy information
2291 2286 * when a frame is received.
2292 2287 */
2293 2288 static void
2294 2289 iwh_rx_phy_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2295 2290 {
2296 2291
2297 2292 sc->sc_rx_phy_res.flag = 1;
2298 2293
2299 2294 bcopy((uint8_t *)(desc + 1), sc->sc_rx_phy_res.buf,
2300 2295 sizeof (iwh_rx_phy_res_t));
2301 2296 }
2302 2297
2303 2298 /*
2304 2299 * this function will be invoked to receive body of frame when
2305 2300 * a frame is received.
2306 2301 */
2307 2302 static void
2308 2303 iwh_rx_mpdu_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2309 2304 {
2310 2305 ieee80211com_t *ic = &sc->sc_ic;
2311 2306 #ifdef DEBUG
2312 2307 iwh_rx_ring_t *ring = &sc->sc_rxq;
2313 2308 #endif
2314 2309 struct ieee80211_frame *wh;
2315 2310 struct iwh_rx_non_cfg_phy *phyinfo;
2316 2311 struct iwh_rx_mpdu_body_size *mpdu_size;
2317 2312 mblk_t *mp;
2318 2313 int16_t t;
2319 2314 uint16_t len, rssi, agc;
2320 2315 uint32_t temp, crc, *tail;
2321 2316 uint32_t arssi, brssi, crssi, mrssi;
2322 2317 iwh_rx_phy_res_t *stat;
2323 2318 ieee80211_node_t *in;
2324 2319
2325 2320 /*
2326 2321 * assuming not 11n here. cope with 11n in phase-II
2327 2322 */
2328 2323 mpdu_size = (struct iwh_rx_mpdu_body_size *)(desc + 1);
2329 2324 stat = (iwh_rx_phy_res_t *)sc->sc_rx_phy_res.buf;
2330 2325 if (stat->cfg_phy_cnt > 20) {
2331 2326 return;
2332 2327 }
2333 2328
2334 2329 phyinfo = (struct iwh_rx_non_cfg_phy *)stat->non_cfg_phy;
2335 2330 temp = LE_32(phyinfo->non_cfg_phy[IWH_RX_RES_AGC_IDX]);
2336 2331 agc = (temp & IWH_OFDM_AGC_MSK) >> IWH_OFDM_AGC_BIT_POS;
2337 2332
2338 2333 temp = LE_32(phyinfo->non_cfg_phy[IWH_RX_RES_RSSI_AB_IDX]);
2339 2334 arssi = (temp & IWH_OFDM_RSSI_A_MSK) >> IWH_OFDM_RSSI_A_BIT_POS;
2340 2335 brssi = (temp & IWH_OFDM_RSSI_B_MSK) >> IWH_OFDM_RSSI_B_BIT_POS;
2341 2336
2342 2337 temp = LE_32(phyinfo->non_cfg_phy[IWH_RX_RES_RSSI_C_IDX]);
2343 2338 crssi = (temp & IWH_OFDM_RSSI_C_MSK) >> IWH_OFDM_RSSI_C_BIT_POS;
2344 2339
2345 2340 mrssi = MAX(arssi, brssi);
2346 2341 mrssi = MAX(mrssi, crssi);
2347 2342
2348 2343 t = mrssi - agc - IWH_RSSI_OFFSET;
2349 2344 /*
2350 2345 * convert dBm to percentage
2351 2346 */
2352 2347 rssi = (100 * 75 * 75 - (-20 - t) * (15 * 75 + 62 * (-20 - t)))
2353 2348 / (75 * 75);
2354 2349 if (rssi > 100) {
2355 2350 rssi = 100;
2356 2351 }
2357 2352 if (rssi < 1) {
2358 2353 rssi = 1;
2359 2354 }
2360 2355
2361 2356 /*
2362 2357 * size of frame, not include FCS
2363 2358 */
2364 2359 len = LE_16(mpdu_size->byte_count);
2365 2360 tail = (uint32_t *)((uint8_t *)(desc + 1) +
2366 2361 sizeof (struct iwh_rx_mpdu_body_size) + len);
2367 2362 bcopy(tail, &crc, 4);
2368 2363
2369 2364 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2370 2365 "rx intr: idx=%d phy_len=%x len=%d "
2371 2366 "rate=%x chan=%d tstamp=%x non_cfg_phy_count=%x "
2372 2367 "cfg_phy_count=%x tail=%x", ring->cur, sizeof (*stat),
2373 2368 len, stat->rate.r.s.rate, stat->channel,
2374 2369 LE_32(stat->timestampl), stat->non_cfg_phy_cnt,
2375 2370 stat->cfg_phy_cnt, LE_32(crc)));
2376 2371
2377 2372 if ((len < 16) || (len > sc->sc_dmabuf_sz)) {
2378 2373 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2379 2374 "rx frame oversize\n"));
2380 2375 return;
2381 2376 }
2382 2377
2383 2378 /*
2384 2379 * discard Rx frames with bad CRC
2385 2380 */
2386 2381 if ((LE_32(crc) &
2387 2382 (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) !=
2388 2383 (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) {
2389 2384 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2390 2385 "rx crc error tail: %x\n",
2391 2386 LE_32(crc)));
2392 2387 sc->sc_rx_err++;
2393 2388 return;
2394 2389 }
2395 2390
2396 2391 wh = (struct ieee80211_frame *)
2397 2392 ((uint8_t *)(desc + 1)+ sizeof (struct iwh_rx_mpdu_body_size));
2398 2393
2399 2394 if (IEEE80211_FC0_SUBTYPE_ASSOC_RESP == *(uint8_t *)wh) {
2400 2395 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2);
2401 2396 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2402 2397 "rx : association id = %x\n",
2403 2398 sc->sc_assoc_id));
2404 2399 }
2405 2400
2406 2401 #ifdef DEBUG
2407 2402 if (iwh_dbg_flags & IWH_DEBUG_RX) {
2408 2403 ieee80211_dump_pkt((uint8_t *)wh, len, 0, 0);
2409 2404 }
2410 2405 #endif
2411 2406
2412 2407 in = ieee80211_find_rxnode(ic, wh);
2413 2408 mp = allocb(len, BPRI_MED);
2414 2409 if (mp) {
2415 2410 bcopy(wh, mp->b_wptr, len);
2416 2411 mp->b_wptr += len;
2417 2412
2418 2413 /*
2419 2414 * send the frame to the 802.11 layer
2420 2415 */
2421 2416 (void) ieee80211_input(ic, mp, in, rssi, 0);
2422 2417 } else {
2423 2418 sc->sc_rx_nobuf++;
2424 2419 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2425 2420 "alloc rx buf failed\n"));
2426 2421 }
2427 2422
2428 2423 /*
2429 2424 * release node reference
2430 2425 */
2431 2426 ieee80211_free_node(in);
2432 2427 }
2433 2428
2434 2429 /*
2435 2430 * process correlative affairs after a frame is sent.
2436 2431 */
2437 2432 static void
2438 2433 iwh_tx_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2439 2434 {
2440 2435 ieee80211com_t *ic = &sc->sc_ic;
2441 2436 iwh_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];
2442 2437 iwh_tx_stat_t *stat = (iwh_tx_stat_t *)(desc + 1);
2443 2438 iwh_amrr_t *amrr;
2444 2439
2445 2440 if (NULL == ic->ic_bss) {
2446 2441 return;
2447 2442 }
2448 2443
2449 2444 amrr = (iwh_amrr_t *)ic->ic_bss;
2450 2445
2451 2446 amrr->txcnt++;
2452 2447 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_tx_intr(): "
2453 2448 "tx: %d cnt\n", amrr->txcnt));
2454 2449
2455 2450 if (stat->ntries > 0) {
2456 2451 amrr->retrycnt++;
2457 2452 sc->sc_tx_retries++;
2458 2453 IWH_DBG((IWH_DEBUG_TX, "iwh_tx_intr(): "
2459 2454 "tx: %d retries\n",
2460 2455 sc->sc_tx_retries));
2461 2456 }
2462 2457
2463 2458 mutex_enter(&sc->sc_mt_lock);
2464 2459 sc->sc_tx_timer = 0;
2465 2460 mutex_exit(&sc->sc_mt_lock);
2466 2461
2467 2462 mutex_enter(&sc->sc_tx_lock);
2468 2463
2469 2464 ring->queued--;
2470 2465 if (ring->queued < 0) {
2471 2466 ring->queued = 0;
2472 2467 }
2473 2468
2474 2469 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) {
2475 2470 sc->sc_need_reschedule = 0;
2476 2471 mutex_exit(&sc->sc_tx_lock);
2477 2472 mac_tx_update(ic->ic_mach);
2478 2473 mutex_enter(&sc->sc_tx_lock);
2479 2474 }
2480 2475
2481 2476 mutex_exit(&sc->sc_tx_lock);
2482 2477 }
2483 2478
2484 2479 /*
2485 2480 * inform a given command has been executed
2486 2481 */
2487 2482 static void
2488 2483 iwh_cmd_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2489 2484 {
2490 2485 if ((desc->hdr.qid & 7) != 4) {
2491 2486 return;
2492 2487 }
2493 2488
2494 2489 if (sc->sc_cmd_accum > 0) {
2495 2490 sc->sc_cmd_accum--;
2496 2491 return;
2497 2492 }
2498 2493
2499 2494 mutex_enter(&sc->sc_glock);
2500 2495
2501 2496 sc->sc_cmd_flag = SC_CMD_FLG_DONE;
2502 2497
2503 2498 cv_signal(&sc->sc_cmd_cv);
2504 2499
2505 2500 mutex_exit(&sc->sc_glock);
2506 2501
2507 2502 IWH_DBG((IWH_DEBUG_CMD, "iwh_cmd_intr(): "
2508 2503 "qid=%x idx=%d flags=%x type=0x%x\n",
2509 2504 desc->hdr.qid, desc->hdr.idx, desc->hdr.flags,
2510 2505 desc->hdr.type));
2511 2506 }
2512 2507
2513 2508 /*
2514 2509 * this function will be invoked when alive notification occur.
2515 2510 */
2516 2511 static void
2517 2512 iwh_ucode_alive(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2518 2513 {
2519 2514 uint32_t rv;
2520 2515 struct iwh_calib_cfg_cmd cmd;
2521 2516 struct iwh_alive_resp *ar =
2522 2517 (struct iwh_alive_resp *)(desc + 1);
2523 2518 struct iwh_calib_results *res_p = &sc->sc_calib_results;
2524 2519
2525 2520 /*
2526 2521 * the microcontroller is ready
2527 2522 */
2528 2523 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2529 2524 "microcode alive notification minor: %x major: %x type: "
2530 2525 "%x subtype: %x\n",
2531 2526 ar->ucode_minor, ar->ucode_minor, ar->ver_type, ar->ver_subtype));
2532 2527
2533 2528 #ifdef DEBUG
2534 2529 if (LE_32(ar->is_valid) != UCODE_VALID_OK) {
2535 2530 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2536 2531 "microcontroller initialization failed\n"));
2537 2532 }
2538 2533 #endif
2539 2534
2540 2535 /*
2541 2536 * determine if init alive or runtime alive.
2542 2537 */
2543 2538 if (INITIALIZE_SUBTYPE == ar->ver_subtype) {
2544 2539 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2545 2540 "initialization alive received.\n"));
2546 2541
2547 2542 bcopy(ar, &sc->sc_card_alive_init,
2548 2543 sizeof (struct iwh_init_alive_resp));
2549 2544
2550 2545 /*
2551 2546 * necessary configuration to NIC
2552 2547 */
2553 2548 mutex_enter(&sc->sc_glock);
2554 2549
2555 2550 rv = iwh_alive_common(sc);
2556 2551 if (rv != IWH_SUCCESS) {
2557 2552 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2558 2553 "common alive process failed in init alive.\n");
2559 2554 mutex_exit(&sc->sc_glock);
2560 2555 return;
2561 2556 }
2562 2557
2563 2558 (void) memset(&cmd, 0, sizeof (cmd));
2564 2559
2565 2560 cmd.ucd_calib_cfg.once.is_enable = IWH_CALIB_INIT_CFG_ALL;
2566 2561 cmd.ucd_calib_cfg.once.start = IWH_CALIB_INIT_CFG_ALL;
2567 2562 cmd.ucd_calib_cfg.once.send_res = IWH_CALIB_INIT_CFG_ALL;
2568 2563 cmd.ucd_calib_cfg.flags = IWH_CALIB_INIT_CFG_ALL;
2569 2564
2570 2565 /*
2571 2566 * require ucode execute calibration
2572 2567 */
2573 2568 rv = iwh_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1);
2574 2569 if (rv != IWH_SUCCESS) {
2575 2570 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2576 2571 "failed to send calibration configure command.\n");
2577 2572 mutex_exit(&sc->sc_glock);
2578 2573 return;
2579 2574 }
2580 2575
2581 2576 mutex_exit(&sc->sc_glock);
2582 2577
2583 2578 } else { /* runtime alive */
2584 2579
2585 2580 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2586 2581 "runtime alive received.\n"));
2587 2582
2588 2583 bcopy(ar, &sc->sc_card_alive_run,
2589 2584 sizeof (struct iwh_alive_resp));
2590 2585
2591 2586 mutex_enter(&sc->sc_glock);
2592 2587
2593 2588 /*
2594 2589 * necessary configuration to NIC
2595 2590 */
2596 2591 rv = iwh_alive_common(sc);
2597 2592 if (rv != IWH_SUCCESS) {
2598 2593 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2599 2594 "common alive process failed in run alive.\n");
2600 2595 mutex_exit(&sc->sc_glock);
2601 2596 return;
2602 2597 }
2603 2598
2604 2599 /*
2605 2600 * send the result of local oscilator calibration to uCode.
2606 2601 */
2607 2602 if (res_p->lo_res != NULL) {
2608 2603 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2609 2604 res_p->lo_res, res_p->lo_res_len, 1);
2610 2605 if (rv != IWH_SUCCESS) {
2611 2606 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2612 2607 "failed to send local"
2613 2608 "oscilator calibration command.\n");
2614 2609 mutex_exit(&sc->sc_glock);
2615 2610 return;
2616 2611 }
2617 2612
2618 2613 DELAY(1000);
2619 2614 }
2620 2615
2621 2616 /*
2622 2617 * send the result of TX IQ calibration to uCode.
2623 2618 */
2624 2619 if (res_p->tx_iq_res != NULL) {
2625 2620 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2626 2621 res_p->tx_iq_res, res_p->tx_iq_res_len, 1);
2627 2622 if (rv != IWH_SUCCESS) {
2628 2623 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2629 2624 "failed to send TX IQ"
2630 2625 "calibration command.\n");
2631 2626 mutex_exit(&sc->sc_glock);
2632 2627 return;
2633 2628 }
2634 2629
2635 2630 DELAY(1000);
2636 2631 }
2637 2632
2638 2633 /*
2639 2634 * sned the result of TX IQ perd calibration to uCode.
2640 2635 */
2641 2636 if (res_p->tx_iq_perd_res != NULL) {
2642 2637 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2643 2638 res_p->tx_iq_perd_res,
2644 2639 res_p->tx_iq_perd_res_len, 1);
2645 2640 if (rv != IWH_SUCCESS) {
2646 2641 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2647 2642 "failed to send TX IQ perd"
2648 2643 "calibration command.\n");
2649 2644 mutex_exit(&sc->sc_glock);
2650 2645 return;
2651 2646 }
2652 2647
2653 2648 DELAY(1000);
2654 2649 }
2655 2650
2656 2651 /*
2657 2652 * send the result of DC calibration to uCode.
2658 2653 */
2659 2654 if (res_p->dc_res != NULL) {
2660 2655 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2661 2656 res_p->dc_res,
2662 2657 res_p->dc_res_len, 1);
2663 2658 if (rv != IWH_SUCCESS) {
2664 2659 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2665 2660 "failed to send DC"
2666 2661 "calibration command.\n");
2667 2662 mutex_exit(&sc->sc_glock);
2668 2663 return;
2669 2664 }
2670 2665
2671 2666 DELAY(1000);
2672 2667 }
2673 2668
2674 2669 /*
2675 2670 * send the result of BASE BAND calibration to uCode.
2676 2671 */
2677 2672 if (res_p->base_band_res != NULL) {
2678 2673 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2679 2674 res_p->base_band_res,
2680 2675 res_p->base_band_res_len, 1);
2681 2676 if (rv != IWH_SUCCESS) {
2682 2677 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2683 2678 "failed to send BASE BAND"
2684 2679 "calibration command.\n");
2685 2680 mutex_exit(&sc->sc_glock);
2686 2681 return;
2687 2682 }
2688 2683
2689 2684 DELAY(1000);
2690 2685 }
2691 2686
2692 2687 atomic_or_32(&sc->sc_flags, IWH_F_FW_INIT);
2693 2688 cv_signal(&sc->sc_ucode_cv);
2694 2689
2695 2690 mutex_exit(&sc->sc_glock);
2696 2691 }
2697 2692
2698 2693 }
2699 2694
2700 2695 /*
2701 2696 * deal with receiving frames, command response
2702 2697 * and all notifications from ucode.
2703 2698 */
2704 2699 /* ARGSUSED */
2705 2700 static uint_t
2706 2701 iwh_rx_softintr(caddr_t arg, caddr_t unused)
2707 2702 {
2708 2703 iwh_sc_t *sc;
2709 2704 ieee80211com_t *ic;
2710 2705 iwh_rx_desc_t *desc;
2711 2706 iwh_rx_data_t *data;
2712 2707 uint32_t index;
2713 2708
2714 2709 if (NULL == arg) {
2715 2710 return (DDI_INTR_UNCLAIMED);
2716 2711 }
2717 2712 sc = (iwh_sc_t *)arg;
2718 2713 ic = &sc->sc_ic;
2719 2714
2720 2715 /*
2721 2716 * firmware has moved the index of the rx queue, driver get it,
2722 2717 * and deal with it.
2723 2718 */
2724 2719 index = (sc->sc_shared->val0) & 0xfff;
2725 2720
2726 2721 while (sc->sc_rxq.cur != index) {
2727 2722 data = &sc->sc_rxq.data[sc->sc_rxq.cur];
2728 2723 desc = (iwh_rx_desc_t *)data->dma_data.mem_va;
2729 2724
2730 2725 IWH_DBG((IWH_DEBUG_INTR, "iwh_rx_softintr(): "
2731 2726 "rx notification index = %d"
2732 2727 " cur = %d qid=%x idx=%d flags=%x type=%x len=%d\n",
2733 2728 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,
2734 2729 desc->hdr.flags, desc->hdr.type, LE_32(desc->len)));
2735 2730
2736 2731 /*
2737 2732 * a command other than a tx need to be replied
2738 2733 */
2739 2734 if (!(desc->hdr.qid & 0x80) &&
2740 2735 (desc->hdr.type != REPLY_SCAN_CMD) &&
2741 2736 (desc->hdr.type != REPLY_TX)) {
2742 2737 iwh_cmd_intr(sc, desc);
2743 2738 }
2744 2739
2745 2740 switch (desc->hdr.type) {
2746 2741 case REPLY_RX_PHY_CMD:
2747 2742 iwh_rx_phy_intr(sc, desc);
2748 2743 break;
2749 2744
2750 2745 case REPLY_RX_MPDU_CMD:
2751 2746 iwh_rx_mpdu_intr(sc, desc);
2752 2747 break;
2753 2748
2754 2749 case REPLY_TX:
2755 2750 iwh_tx_intr(sc, desc);
2756 2751 break;
2757 2752
2758 2753 case REPLY_ALIVE:
2759 2754 iwh_ucode_alive(sc, desc);
2760 2755 break;
2761 2756
2762 2757 case CARD_STATE_NOTIFICATION:
2763 2758 {
2764 2759 uint32_t *status = (uint32_t *)(desc + 1);
2765 2760
2766 2761 IWH_DBG((IWH_DEBUG_RADIO, "iwh_rx_softintr(): "
2767 2762 "state changed to %x\n",
2768 2763 LE_32(*status)));
2769 2764
2770 2765 if (LE_32(*status) & 1) {
2771 2766 /*
2772 2767 * the radio button has to be pushed(OFF). It
2773 2768 * is considered as a hw error, the
2774 2769 * iwh_thread() tries to recover it after the
2775 2770 * button is pushed again(ON)
2776 2771 */
2777 2772 cmn_err(CE_NOTE, "iwh_rx_softintr(): "
2778 2773 "radio transmitter is off\n");
2779 2774 sc->sc_ostate = sc->sc_ic.ic_state;
2780 2775 ieee80211_new_state(&sc->sc_ic,
2781 2776 IEEE80211_S_INIT, -1);
2782 2777 atomic_or_32(&sc->sc_flags,
2783 2778 (IWH_F_HW_ERR_RECOVER | IWH_F_RADIO_OFF));
2784 2779 }
2785 2780
2786 2781 break;
2787 2782 }
2788 2783
2789 2784 case SCAN_START_NOTIFICATION:
2790 2785 {
2791 2786 iwh_start_scan_t *scan =
2792 2787 (iwh_start_scan_t *)(desc + 1);
2793 2788
2794 2789 IWH_DBG((IWH_DEBUG_SCAN, "iwh_rx_softintr(): "
2795 2790 "scanning channel %d status %x\n",
2796 2791 scan->chan, LE_32(scan->status)));
2797 2792
2798 2793 ic->ic_curchan = &ic->ic_sup_channels[scan->chan];
2799 2794 break;
2800 2795 }
2801 2796
2802 2797 case SCAN_COMPLETE_NOTIFICATION:
2803 2798 {
2804 2799 #ifdef DEBUG
2805 2800 iwh_stop_scan_t *scan =
2806 2801 (iwh_stop_scan_t *)(desc + 1);
2807 2802
2808 2803 IWH_DBG((IWH_DEBUG_SCAN, "iwh_rx_softintr(): "
2809 2804 "completed channel %d (burst of %d) status %02x\n",
2810 2805 scan->chan, scan->nchan, scan->status));
2811 2806 #endif
2812 2807
2813 2808 sc->sc_scan_pending++;
2814 2809 break;
2815 2810 }
2816 2811
2817 2812 case STATISTICS_NOTIFICATION:
2818 2813 {
2819 2814 /*
2820 2815 * handle statistics notification
2821 2816 */
2822 2817 break;
2823 2818 }
2824 2819
2825 2820 case CALIBRATION_RES_NOTIFICATION:
2826 2821 iwh_save_calib_result(sc, desc);
2827 2822 break;
2828 2823
2829 2824 case CALIBRATION_COMPLETE_NOTIFICATION:
2830 2825 mutex_enter(&sc->sc_glock);
2831 2826 atomic_or_32(&sc->sc_flags, IWH_F_FW_INIT);
2832 2827 cv_signal(&sc->sc_ucode_cv);
2833 2828 mutex_exit(&sc->sc_glock);
2834 2829 break;
2835 2830
2836 2831 case MISSED_BEACONS_NOTIFICATION:
2837 2832 /* handle beacon miss by software mechanism */
2838 2833 break;
2839 2834 }
2840 2835
2841 2836 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE;
2842 2837 }
2843 2838
2844 2839 /*
2845 2840 * driver dealt with what received in rx queue and tell the information
2846 2841 * to the firmware.
2847 2842 */
2848 2843 index = (0 == index) ? RX_QUEUE_SIZE - 1 : index - 1;
2849 2844 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
2850 2845
2851 2846 /*
2852 2847 * re-enable interrupts
2853 2848 */
2854 2849 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2855 2850
2856 2851 return (DDI_INTR_CLAIMED);
2857 2852 }
2858 2853
2859 2854 /*
2860 2855 * the handle of interrupt
2861 2856 */
2862 2857 /* ARGSUSED */
2863 2858 static uint_t
2864 2859 iwh_intr(caddr_t arg, caddr_t unused)
2865 2860 {
2866 2861 iwh_sc_t *sc;
2867 2862 uint32_t r, rfh;
2868 2863
2869 2864 if (NULL == arg) {
2870 2865 return (DDI_INTR_UNCLAIMED);
2871 2866 }
2872 2867 sc = (iwh_sc_t *)arg;
2873 2868
2874 2869 r = IWH_READ(sc, CSR_INT);
2875 2870 if (0 == r || 0xffffffff == r) {
2876 2871 return (DDI_INTR_UNCLAIMED);
2877 2872 }
2878 2873
2879 2874 IWH_DBG((IWH_DEBUG_INTR, "iwh_intr(): "
2880 2875 "interrupt reg %x\n", r));
2881 2876
2882 2877 rfh = IWH_READ(sc, CSR_FH_INT_STATUS);
2883 2878
2884 2879 IWH_DBG((IWH_DEBUG_INTR, "iwh_intr(): "
2885 2880 "FH interrupt reg %x\n", rfh));
2886 2881
2887 2882 /*
2888 2883 * disable interrupts
2889 2884 */
2890 2885 IWH_WRITE(sc, CSR_INT_MASK, 0);
2891 2886
2892 2887 /*
2893 2888 * ack interrupts
2894 2889 */
2895 2890 IWH_WRITE(sc, CSR_INT, r);
2896 2891 IWH_WRITE(sc, CSR_FH_INT_STATUS, rfh);
2897 2892
2898 2893 if (r & (BIT_INT_SWERROR | BIT_INT_ERR)) {
2899 2894 IWH_DBG((IWH_DEBUG_FW, "iwh_intr(): "
2900 2895 "fatal firmware error\n"));
2901 2896 iwh_stop(sc);
2902 2897 sc->sc_ostate = sc->sc_ic.ic_state;
2903 2898
2904 2899 /*
2905 2900 * notify upper layer
2906 2901 */
2907 2902 if (!IWH_CHK_FAST_RECOVER(sc)) {
2908 2903 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2909 2904 }
2910 2905
2911 2906 atomic_or_32(&sc->sc_flags, IWH_F_HW_ERR_RECOVER);
2912 2907 return (DDI_INTR_CLAIMED);
2913 2908 }
2914 2909
2915 2910 if (r & BIT_INT_RF_KILL) {
2916 2911 uint32_t tmp = IWH_READ(sc, CSR_GP_CNTRL);
2917 2912 if (tmp & (1 << 27)) {
2918 2913 cmn_err(CE_NOTE, "RF switch: radio on\n");
2919 2914 }
2920 2915 }
2921 2916
2922 2917 if ((r & (BIT_INT_FH_RX | BIT_INT_SW_RX)) ||
2923 2918 (rfh & FH_INT_RX_MASK)) {
2924 2919 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL);
2925 2920 return (DDI_INTR_CLAIMED);
2926 2921 }
2927 2922
2928 2923 if (r & BIT_INT_FH_TX) {
2929 2924 mutex_enter(&sc->sc_glock);
2930 2925 atomic_or_32(&sc->sc_flags, IWH_F_PUT_SEG);
2931 2926 cv_signal(&sc->sc_put_seg_cv);
2932 2927 mutex_exit(&sc->sc_glock);
2933 2928 }
2934 2929
2935 2930 #ifdef DEBUG
2936 2931 if (r & BIT_INT_ALIVE) {
2937 2932 IWH_DBG((IWH_DEBUG_FW, "iwh_intr(): "
2938 2933 "firmware initialized.\n"));
2939 2934 }
2940 2935 #endif
2941 2936
2942 2937 /*
2943 2938 * re-enable interrupts
2944 2939 */
2945 2940 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2946 2941
2947 2942 return (DDI_INTR_CLAIMED);
2948 2943 }
2949 2944
2950 2945 static uint8_t
2951 2946 iwh_rate_to_plcp(int rate)
2952 2947 {
2953 2948 uint8_t ret;
2954 2949
2955 2950 switch (rate) {
2956 2951 /*
2957 2952 * CCK rates
2958 2953 */
2959 2954 case 2:
2960 2955 ret = 0xa;
2961 2956 break;
2962 2957
2963 2958 case 4:
2964 2959 ret = 0x14;
2965 2960 break;
2966 2961
2967 2962 case 11:
2968 2963 ret = 0x37;
2969 2964 break;
2970 2965
2971 2966 case 22:
2972 2967 ret = 0x6e;
2973 2968 break;
2974 2969
2975 2970 /*
2976 2971 * OFDM rates
2977 2972 */
2978 2973 case 12:
2979 2974 ret = 0xd;
2980 2975 break;
2981 2976
2982 2977 case 18:
2983 2978 ret = 0xf;
2984 2979 break;
2985 2980
2986 2981 case 24:
2987 2982 ret = 0x5;
2988 2983 break;
2989 2984
2990 2985 case 36:
2991 2986 ret = 0x7;
2992 2987 break;
2993 2988
2994 2989 case 48:
2995 2990 ret = 0x9;
2996 2991 break;
2997 2992
2998 2993 case 72:
2999 2994 ret = 0xb;
3000 2995 break;
3001 2996
3002 2997 case 96:
3003 2998 ret = 0x1;
3004 2999 break;
3005 3000
3006 3001 case 108:
3007 3002 ret = 0x3;
3008 3003 break;
3009 3004
3010 3005 default:
3011 3006 ret = 0;
3012 3007 break;
3013 3008 }
3014 3009
3015 3010 return (ret);
3016 3011 }
3017 3012
3018 3013 /*
3019 3014 * invoked by GLD send frames
3020 3015 */
3021 3016 static mblk_t *
3022 3017 iwh_m_tx(void *arg, mblk_t *mp)
3023 3018 {
3024 3019 iwh_sc_t *sc;
3025 3020 ieee80211com_t *ic;
3026 3021 mblk_t *next;
3027 3022
3028 3023 if (NULL == arg) {
3029 3024 return (NULL);
3030 3025 }
3031 3026 sc = (iwh_sc_t *)arg;
3032 3027 ic = &sc->sc_ic;
3033 3028
3034 3029 if (sc->sc_flags & IWH_F_SUSPEND) {
3035 3030 freemsgchain(mp);
3036 3031 return (NULL);
3037 3032 }
3038 3033
3039 3034 if (ic->ic_state != IEEE80211_S_RUN) {
3040 3035 freemsgchain(mp);
3041 3036 return (NULL);
3042 3037 }
3043 3038
3044 3039 if ((sc->sc_flags & IWH_F_HW_ERR_RECOVER) &&
3045 3040 IWH_CHK_FAST_RECOVER(sc)) {
3046 3041 IWH_DBG((IWH_DEBUG_FW, "iwh_m_tx(): "
3047 3042 "hold queue\n"));
3048 3043 return (mp);
3049 3044 }
3050 3045
3051 3046 while (mp != NULL) {
3052 3047 next = mp->b_next;
3053 3048 mp->b_next = NULL;
3054 3049 if (iwh_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != 0) {
3055 3050 mp->b_next = next;
3056 3051 break;
3057 3052 }
3058 3053 mp = next;
3059 3054 }
3060 3055
3061 3056 return (mp);
3062 3057 }
3063 3058
3064 3059 /*
3065 3060 * send frames
3066 3061 */
3067 3062 static int
3068 3063 iwh_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
3069 3064 {
3070 3065 iwh_sc_t *sc;
3071 3066 iwh_tx_ring_t *ring;
3072 3067 iwh_tx_desc_t *desc;
3073 3068 iwh_tx_data_t *data;
3074 3069 iwh_tx_data_t *desc_data;
3075 3070 iwh_cmd_t *cmd;
3076 3071 iwh_tx_cmd_t *tx;
3077 3072 ieee80211_node_t *in;
3078 3073 struct ieee80211_frame *wh, *mp_wh;
3079 3074 struct ieee80211_key *k = NULL;
3080 3075 mblk_t *m, *m0;
3081 3076 int hdrlen, len, len0, mblen, off, err = IWH_SUCCESS;
3082 3077 uint16_t masks = 0;
3083 3078 uint32_t rate, s_id = 0;
3084 3079 int txq_id = NON_QOS_TXQ;
3085 3080 struct ieee80211_qosframe *qwh = NULL;
3086 3081 int tid = WME_TID_INVALID;
3087 3082
3088 3083 if (NULL == ic) {
3089 3084 return (IWH_FAIL);
3090 3085 }
3091 3086 sc = (iwh_sc_t *)ic;
3092 3087
3093 3088 if (sc->sc_flags & IWH_F_SUSPEND) {
3094 3089 if ((type & IEEE80211_FC0_TYPE_MASK) !=
3095 3090 IEEE80211_FC0_TYPE_DATA) {
3096 3091 freemsg(mp);
3097 3092 }
3098 3093 err = IWH_FAIL;
3099 3094 goto exit;
3100 3095 }
3101 3096
3102 3097 if ((NULL == mp) || (MBLKL(mp) <= 0)) {
3103 3098 return (IWH_FAIL);
3104 3099 }
3105 3100
3106 3101 mp_wh = (struct ieee80211_frame *)mp->b_rptr;
3107 3102
3108 3103 /*
3109 3104 * Determine send which AP or station in IBSS
3110 3105 */
3111 3106 in = ieee80211_find_txnode(ic, mp_wh->i_addr1);
3112 3107 if (NULL == in) {
3113 3108 cmn_err(CE_WARN, "iwh_send(): "
3114 3109 "failed to find tx node\n");
3115 3110 freemsg(mp);
3116 3111 sc->sc_tx_err++;
3117 3112 err = IWH_SUCCESS;
3118 3113 goto exit;
3119 3114 }
3120 3115
3121 3116 /*
3122 3117 * Determine TX queue according to traffic ID in frame
3123 3118 * if working in QoS mode.
3124 3119 */
3125 3120 if (in->in_flags & IEEE80211_NODE_QOS) {
3126 3121
3127 3122 if ((type & IEEE80211_FC0_TYPE_MASK) ==
3128 3123 IEEE80211_FC0_TYPE_DATA) {
3129 3124
3130 3125 if (mp_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3131 3126 qwh = (struct ieee80211_qosframe *)mp_wh;
3132 3127
3133 3128 tid = qwh->i_qos[0] & IEEE80211_QOS_TID;
3134 3129 txq_id = iwh_wme_tid_to_txq(tid);
3135 3130
3136 3131 if (txq_id < TXQ_FOR_AC_MIN ||
3137 3132 (txq_id > TXQ_FOR_AC_MAX)) {
3138 3133 freemsg(mp);
3139 3134 sc->sc_tx_err++;
3140 3135 err = IWH_SUCCESS;
3141 3136 goto exit;
3142 3137 }
3143 3138
3144 3139 } else {
3145 3140 txq_id = NON_QOS_TXQ;
3146 3141 }
3147 3142
3148 3143 } else if ((type & IEEE80211_FC0_TYPE_MASK) ==
3149 3144 IEEE80211_FC0_TYPE_MGT) {
3150 3145 txq_id = QOS_TXQ_FOR_MGT;
3151 3146 } else {
3152 3147 txq_id = NON_QOS_TXQ;
3153 3148 }
3154 3149
3155 3150 } else {
3156 3151 txq_id = NON_QOS_TXQ;
3157 3152 }
3158 3153
3159 3154 mutex_enter(&sc->sc_tx_lock);
3160 3155 ring = &sc->sc_txq[txq_id];
3161 3156 data = &ring->data[ring->cur];
3162 3157 cmd = data->cmd;
3163 3158 bzero(cmd, sizeof (*cmd));
3164 3159
3165 3160 ring->cur = (ring->cur + 1) % ring->count;
3166 3161
3167 3162 /*
3168 3163 * Need reschedule TX if TX buffer is full.
3169 3164 */
3170 3165 if (ring->queued > ring->count - IWH_MAX_WIN_SIZE) {
3171 3166 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3172 3167 "no txbuf\n"));
3173 3168
3174 3169 sc->sc_need_reschedule = 1;
3175 3170 mutex_exit(&sc->sc_tx_lock);
3176 3171
3177 3172 if ((type & IEEE80211_FC0_TYPE_MASK) !=
3178 3173 IEEE80211_FC0_TYPE_DATA) {
3179 3174 freemsg(mp);
3180 3175 }
3181 3176 sc->sc_tx_nobuf++;
3182 3177 err = IWH_FAIL;
3183 3178 goto exit;
3184 3179 }
3185 3180
3186 3181 ring->queued++;
3187 3182
3188 3183 mutex_exit(&sc->sc_tx_lock);
3189 3184
3190 3185 hdrlen = ieee80211_hdrspace(ic, mp->b_rptr);
3191 3186
3192 3187 m = allocb(msgdsize(mp) + 32, BPRI_MED);
3193 3188 if (NULL == m) { /* can not alloc buf, drop this package */
3194 3189 cmn_err(CE_WARN, "iwh_send(): "
3195 3190 "failed to allocate msgbuf\n");
3196 3191 freemsg(mp);
3197 3192
3198 3193 mutex_enter(&sc->sc_tx_lock);
3199 3194 ring->queued--;
3200 3195 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3201 3196 sc->sc_need_reschedule = 0;
3202 3197 mutex_exit(&sc->sc_tx_lock);
3203 3198 mac_tx_update(ic->ic_mach);
3204 3199 mutex_enter(&sc->sc_tx_lock);
3205 3200 }
3206 3201 mutex_exit(&sc->sc_tx_lock);
3207 3202
3208 3203 err = IWH_SUCCESS;
3209 3204 goto exit;
3210 3205 }
3211 3206
3212 3207 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
3213 3208 mblen = MBLKL(m0);
3214 3209 bcopy(m0->b_rptr, m->b_rptr + off, mblen);
3215 3210 off += mblen;
3216 3211 }
3217 3212
3218 3213 m->b_wptr += off;
3219 3214
3220 3215 wh = (struct ieee80211_frame *)m->b_rptr;
3221 3216
3222 3217 /*
3223 3218 * Net80211 module encapsulate outbound data frames.
3224 3219 * Add some feilds of 80211 frame.
3225 3220 */
3226 3221 if ((type & IEEE80211_FC0_TYPE_MASK) ==
3227 3222 IEEE80211_FC0_TYPE_DATA) {
3228 3223 (void) ieee80211_encap(ic, m, in);
3229 3224 }
3230 3225
3231 3226 freemsg(mp);
3232 3227
3233 3228 cmd->hdr.type = REPLY_TX;
3234 3229 cmd->hdr.flags = 0;
3235 3230 cmd->hdr.qid = ring->qid;
3236 3231
3237 3232 tx = (iwh_tx_cmd_t *)cmd->data;
3238 3233 tx->tx_flags = 0;
3239 3234
3240 3235 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3241 3236 tx->tx_flags &= ~(LE_32(TX_CMD_FLG_ACK_MSK));
3242 3237 } else {
3243 3238 tx->tx_flags |= LE_32(TX_CMD_FLG_ACK_MSK);
3244 3239 }
3245 3240
3246 3241 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
3247 3242 k = ieee80211_crypto_encap(ic, m);
3248 3243 if (NULL == k) {
3249 3244 freemsg(m);
3250 3245 sc->sc_tx_err++;
3251 3246
3252 3247 mutex_enter(&sc->sc_tx_lock);
3253 3248 ring->queued--;
3254 3249 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3255 3250 sc->sc_need_reschedule = 0;
3256 3251 mutex_exit(&sc->sc_tx_lock);
3257 3252 mac_tx_update(ic->ic_mach);
3258 3253 mutex_enter(&sc->sc_tx_lock);
3259 3254 }
3260 3255 mutex_exit(&sc->sc_tx_lock);
3261 3256
3262 3257 err = IWH_SUCCESS;
3263 3258 goto exit;
3264 3259 }
3265 3260
3266 3261 /*
3267 3262 * packet header may have moved, reset our local pointer
3268 3263 */
3269 3264 wh = (struct ieee80211_frame *)m->b_rptr;
3270 3265 }
3271 3266
3272 3267 len = msgdsize(m);
3273 3268
3274 3269 #ifdef DEBUG
3275 3270 if (iwh_dbg_flags & IWH_DEBUG_TX) {
3276 3271 ieee80211_dump_pkt((uint8_t *)wh, hdrlen, 0, 0);
3277 3272 }
3278 3273 #endif
3279 3274
3280 3275 tx->rts_retry_limit = IWH_TX_RTS_RETRY_LIMIT;
3281 3276 tx->data_retry_limit = IWH_TX_DATA_RETRY_LIMIT;
3282 3277
3283 3278 /*
3284 3279 * specific TX parameters for management frames
3285 3280 */
3286 3281 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3287 3282 IEEE80211_FC0_TYPE_MGT) {
3288 3283 /*
3289 3284 * mgmt frames are sent at 1M
3290 3285 */
3291 3286 if ((in->in_rates.ir_rates[0] &
3292 3287 IEEE80211_RATE_VAL) != 0) {
3293 3288 rate = in->in_rates.ir_rates[0] & IEEE80211_RATE_VAL;
3294 3289 } else {
3295 3290 rate = 2;
3296 3291 }
3297 3292
3298 3293 tx->tx_flags |= LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
3299 3294
3300 3295 /*
3301 3296 * tell h/w to set timestamp in probe responses
3302 3297 */
3303 3298 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3304 3299 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
3305 3300 tx->tx_flags |= LE_32(TX_CMD_FLG_TSF_MSK);
3306 3301
3307 3302 tx->data_retry_limit = 3;
3308 3303 if (tx->data_retry_limit < tx->rts_retry_limit) {
3309 3304 tx->rts_retry_limit = tx->data_retry_limit;
3310 3305 }
3311 3306 }
3312 3307
3313 3308 if (((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3314 3309 IEEE80211_FC0_SUBTYPE_ASSOC_REQ) ||
3315 3310 ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3316 3311 IEEE80211_FC0_SUBTYPE_REASSOC_REQ)) {
3317 3312 tx->timeout.pm_frame_timeout = LE_16(3);
3318 3313 } else {
3319 3314 tx->timeout.pm_frame_timeout = LE_16(2);
3320 3315 }
3321 3316
3322 3317 } else {
3323 3318 /*
3324 3319 * do it here for the software way rate scaling.
3325 3320 * later for rate scaling in hardware.
3326 3321 *
3327 3322 * now the txrate is determined in tx cmd flags, set to the
3328 3323 * max value 54M for 11g and 11M for 11b and 96M for 11n
3329 3324 * originally.
3330 3325 */
3331 3326 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3332 3327 rate = ic->ic_fixed_rate;
3333 3328 } else {
3334 3329 if ((in->in_flags & IEEE80211_NODE_HT) &&
3335 3330 (sc->sc_ht_conf.ht_support)) {
3336 3331 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
3337 3332 rate = amrr->ht_mcs_idx;
3338 3333 } else {
3339 3334 if ((in->in_rates.ir_rates[in->in_txrate] &
3340 3335 IEEE80211_RATE_VAL) != 0) {
3341 3336 rate = in->in_rates.
3342 3337 ir_rates[in->in_txrate] &
3343 3338 IEEE80211_RATE_VAL;
3344 3339 }
3345 3340 }
3346 3341 }
3347 3342
3348 3343 if (tid != WME_TID_INVALID) {
3349 3344 tx->tid_tspec = (uint8_t)tid;
3350 3345 tx->tx_flags &= LE_32(~TX_CMD_FLG_SEQ_CTL_MSK);
3351 3346 } else {
3352 3347 tx->tx_flags |= LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
3353 3348 }
3354 3349
3355 3350 tx->timeout.pm_frame_timeout = 0;
3356 3351 }
3357 3352
3358 3353 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3359 3354 "tx rate[%d of %d] = %x",
3360 3355 in->in_txrate, in->in_rates.ir_nrates, rate));
3361 3356
3362 3357 len0 = roundup(4 + sizeof (iwh_tx_cmd_t) + hdrlen, 4);
3363 3358 if (len0 != (4 + sizeof (iwh_tx_cmd_t) + hdrlen)) {
3364 3359 tx->tx_flags |= LE_32(TX_CMD_FLG_MH_PAD_MSK);
3365 3360 }
3366 3361
3367 3362 /*
3368 3363 * retrieve destination node's id
3369 3364 */
3370 3365 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3371 3366 tx->sta_id = IWH_BROADCAST_ID;
3372 3367 } else {
3373 3368 tx->sta_id = IWH_AP_ID;
3374 3369 }
3375 3370
3376 3371 if ((in->in_flags & IEEE80211_NODE_HT) &&
3377 3372 (sc->sc_ht_conf.ht_support) &&
3378 3373 ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3379 3374 IEEE80211_FC0_TYPE_DATA)) {
3380 3375 if (rate >= HT_2CHAIN_RATE_MIN_IDX) {
3381 3376 rate |= LE_32(RATE_MCS_ANT_AB_MSK);
3382 3377 } else {
3383 3378 rate |= LE_32(RATE_MCS_ANT_B_MSK);
3384 3379 }
3385 3380
3386 3381 rate |= LE_32((1 << RATE_MCS_HT_POS));
3387 3382
3388 3383 tx->rate.r.rate_n_flags = rate;
3389 3384
3390 3385 } else {
3391 3386 if (2 == rate || 4 == rate || 11 == rate || 22 == rate) {
3392 3387 masks |= RATE_MCS_CCK_MSK;
3393 3388 }
3394 3389
3395 3390 masks |= RATE_MCS_ANT_B_MSK;
3396 3391 tx->rate.r.rate_n_flags = LE_32(iwh_rate_to_plcp(rate) | masks);
3397 3392 }
3398 3393
3399 3394 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3400 3395 "tx flag = %x",
3401 3396 tx->tx_flags));
3402 3397
3403 3398 tx->stop_time.life_time = LE_32(0xffffffff);
3404 3399
3405 3400 tx->len = LE_16(len);
3406 3401
3407 3402 tx->dram_lsb_ptr =
3408 3403 LE_32(data->paddr_cmd + 4 + offsetof(iwh_tx_cmd_t, scratch));
3409 3404 tx->dram_msb_ptr = 0;
3410 3405 tx->driver_txop = 0;
3411 3406 tx->next_frame_len = 0;
3412 3407
3413 3408 bcopy(m->b_rptr, tx + 1, hdrlen);
3414 3409 m->b_rptr += hdrlen;
3415 3410 bcopy(m->b_rptr, data->dma_data.mem_va, (len - hdrlen));
3416 3411
3417 3412 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3418 3413 "sending data: qid=%d idx=%d len=%d",
3419 3414 ring->qid, ring->cur, len));
3420 3415
3421 3416 /*
3422 3417 * first segment includes the tx cmd plus the 802.11 header,
3423 3418 * the second includes the remaining of the 802.11 frame.
3424 3419 */
3425 3420
3426 3421 mutex_enter(&sc->sc_tx_lock);
3427 3422 cmd->hdr.idx = ring->desc_cur;
3428 3423 desc_data = &ring->data[ring->desc_cur];
3429 3424 desc = desc_data->desc;
3430 3425 bzero(desc, sizeof (*desc));
3431 3426 desc->val0 = 2 << 24;
3432 3427 desc->pa[0].tb1_addr = data->paddr_cmd;
3433 3428 desc->pa[0].val1 = ((len0 << 4) & 0xfff0) |
3434 3429 ((data->dma_data.cookie.dmac_address & 0xffff) << 16);
3435 3430 desc->pa[0].val2 =
3436 3431 ((data->dma_data.cookie.dmac_address & 0xffff0000) >> 16) |
3437 3432 ((len - hdrlen) << 20);
3438 3433 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3439 3434 "phy addr1 = 0x%x phy addr2 = 0x%x "
3440 3435 "len1 = 0x%x, len2 = 0x%x val1 = 0x%x val2 = 0x%x",
3441 3436 data->paddr_cmd, data->dma_data.cookie.dmac_address,
3442 3437 len0, len - hdrlen, desc->pa[0].val1, desc->pa[0].val2));
3443 3438
3444 3439 /*
3445 3440 * kick ring
3446 3441 */
3447 3442 s_id = tx->sta_id;
3448 3443
3449 3444 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3450 3445 tfd_offset[ring->desc_cur].val =
3451 3446 (8 + len) | (s_id << 12);
3452 3447 if (ring->desc_cur < IWH_MAX_WIN_SIZE) {
3453 3448 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3454 3449 tfd_offset[IWH_QUEUE_SIZE + ring->desc_cur].val =
3455 3450 (8 + len) | (s_id << 12);
3456 3451 }
3457 3452
3458 3453 IWH_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV);
3459 3454 IWH_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
3460 3455
3461 3456 ring->desc_cur = (ring->desc_cur + 1) % ring->count;
3462 3457 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur);
3463 3458
3464 3459 mutex_exit(&sc->sc_tx_lock);
3465 3460 freemsg(m);
3466 3461
3467 3462 /*
3468 3463 * release node reference
3469 3464 */
3470 3465 ieee80211_free_node(in);
3471 3466
3472 3467 ic->ic_stats.is_tx_bytes += len;
3473 3468 ic->ic_stats.is_tx_frags++;
3474 3469
3475 3470 mutex_enter(&sc->sc_mt_lock);
3476 3471 if (0 == sc->sc_tx_timer) {
3477 3472 sc->sc_tx_timer = 4;
3478 3473 }
3479 3474 mutex_exit(&sc->sc_mt_lock);
3480 3475
3481 3476 exit:
3482 3477 return (err);
3483 3478 }
3484 3479
3485 3480 /*
3486 3481 * invoked by GLD to deal with IOCTL affaires
3487 3482 */
3488 3483 static void
3489 3484 iwh_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
3490 3485 {
3491 3486 iwh_sc_t *sc;
3492 3487 ieee80211com_t *ic;
3493 3488 int err = EINVAL;
3494 3489
3495 3490 if (NULL == arg) {
3496 3491 return;
3497 3492 }
3498 3493 sc = (iwh_sc_t *)arg;
3499 3494 ic = &sc->sc_ic;
3500 3495
3501 3496 err = ieee80211_ioctl(ic, wq, mp);
3502 3497 if (ENETRESET == err) {
3503 3498 /*
3504 3499 * This is special for the hidden AP connection.
3505 3500 * In any case, we should make sure only one 'scan'
3506 3501 * in the driver for a 'connect' CLI command. So
3507 3502 * when connecting to a hidden AP, the scan is just
3508 3503 * sent out to the air when we know the desired
3509 3504 * essid of the AP we want to connect.
3510 3505 */
3511 3506 if (ic->ic_des_esslen) {
3512 3507 if (sc->sc_flags & IWH_F_RUNNING) {
3513 3508 iwh_m_stop(sc);
3514 3509 (void) iwh_m_start(sc);
3515 3510 (void) ieee80211_new_state(ic,
3516 3511 IEEE80211_S_SCAN, -1);
3517 3512 }
3518 3513 }
3519 3514 }
3520 3515 }
3521 3516
3522 3517 /*
3523 3518 * Call back functions for get/set proporty
3524 3519 */
3525 3520 static int
3526 3521 iwh_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3527 3522 uint_t wldp_length, void *wldp_buf)
3528 3523 {
3529 3524 iwh_sc_t *sc;
3530 3525 int err = EINVAL;
3531 3526
3532 3527 if (NULL == arg) {
3533 3528 return (EINVAL);
3534 3529 }
3535 3530 sc = (iwh_sc_t *)arg;
3536 3531
3537 3532 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3538 3533 wldp_length, wldp_buf);
3539 3534
3540 3535 return (err);
3541 3536 }
3542 3537
3543 3538 static void
3544 3539 iwh_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3545 3540 mac_prop_info_handle_t mph)
3546 3541 {
3547 3542 iwh_sc_t *sc = (iwh_sc_t *)arg;
3548 3543
3549 3544 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
3550 3545 }
3551 3546
3552 3547 static int
3553 3548 iwh_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3554 3549 uint_t wldp_length, const void *wldp_buf)
3555 3550 {
3556 3551 iwh_sc_t *sc;
3557 3552 ieee80211com_t *ic;
3558 3553 int err = EINVAL;
3559 3554
3560 3555 if (NULL == arg) {
3561 3556 return (EINVAL);
3562 3557 }
3563 3558 sc = (iwh_sc_t *)arg;
3564 3559 ic = &sc->sc_ic;
3565 3560
3566 3561 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
3567 3562 wldp_buf);
3568 3563
3569 3564 if (err == ENETRESET) {
3570 3565 if (ic->ic_des_esslen) {
3571 3566 if (sc->sc_flags & IWH_F_RUNNING) {
3572 3567 iwh_m_stop(sc);
3573 3568 (void) iwh_m_start(sc);
3574 3569 (void) ieee80211_new_state(ic,
3575 3570 IEEE80211_S_SCAN, -1);
3576 3571 }
3577 3572 }
3578 3573 err = 0;
3579 3574 }
3580 3575 return (err);
3581 3576 }
3582 3577
3583 3578 /*
3584 3579 * invoked by GLD supply statistics NIC and driver
3585 3580 */
3586 3581 static int
3587 3582 iwh_m_stat(void *arg, uint_t stat, uint64_t *val)
3588 3583 {
3589 3584 iwh_sc_t *sc;
3590 3585 ieee80211com_t *ic;
3591 3586 ieee80211_node_t *in;
3592 3587
3593 3588 if (NULL == arg) {
3594 3589 return (EINVAL);
3595 3590 }
3596 3591 sc = (iwh_sc_t *)arg;
3597 3592 ic = &sc->sc_ic;
3598 3593
3599 3594 mutex_enter(&sc->sc_glock);
3600 3595
3601 3596 switch (stat) {
3602 3597 case MAC_STAT_IFSPEED:
3603 3598 in = ic->ic_bss;
3604 3599 *val = ((IEEE80211_FIXED_RATE_NONE == ic->ic_fixed_rate) ?
3605 3600 IEEE80211_RATE(in->in_txrate) :
3606 3601 ic->ic_fixed_rate) / 2 * 1000000;
3607 3602 break;
3608 3603
3609 3604 case MAC_STAT_NOXMTBUF:
3610 3605 *val = sc->sc_tx_nobuf;
3611 3606 break;
3612 3607
3613 3608 case MAC_STAT_NORCVBUF:
3614 3609 *val = sc->sc_rx_nobuf;
3615 3610 break;
3616 3611
3617 3612 case MAC_STAT_IERRORS:
3618 3613 *val = sc->sc_rx_err;
3619 3614 break;
3620 3615
3621 3616 case MAC_STAT_RBYTES:
3622 3617 *val = ic->ic_stats.is_rx_bytes;
3623 3618 break;
3624 3619
3625 3620 case MAC_STAT_IPACKETS:
3626 3621 *val = ic->ic_stats.is_rx_frags;
3627 3622 break;
3628 3623
3629 3624 case MAC_STAT_OBYTES:
3630 3625 *val = ic->ic_stats.is_tx_bytes;
3631 3626 break;
3632 3627
3633 3628 case MAC_STAT_OPACKETS:
3634 3629 *val = ic->ic_stats.is_tx_frags;
3635 3630 break;
3636 3631
3637 3632 case MAC_STAT_OERRORS:
3638 3633 case WIFI_STAT_TX_FAILED:
3639 3634 *val = sc->sc_tx_err;
3640 3635 break;
3641 3636
3642 3637 case WIFI_STAT_TX_RETRANS:
3643 3638 *val = sc->sc_tx_retries;
3644 3639 break;
3645 3640
3646 3641 case WIFI_STAT_FCS_ERRORS:
3647 3642 case WIFI_STAT_WEP_ERRORS:
3648 3643 case WIFI_STAT_TX_FRAGS:
3649 3644 case WIFI_STAT_MCAST_TX:
3650 3645 case WIFI_STAT_RTS_SUCCESS:
3651 3646 case WIFI_STAT_RTS_FAILURE:
3652 3647 case WIFI_STAT_ACK_FAILURE:
3653 3648 case WIFI_STAT_RX_FRAGS:
3654 3649 case WIFI_STAT_MCAST_RX:
3655 3650 case WIFI_STAT_RX_DUPS:
3656 3651 mutex_exit(&sc->sc_glock);
3657 3652 return (ieee80211_stat(ic, stat, val));
3658 3653
3659 3654 default:
3660 3655 mutex_exit(&sc->sc_glock);
3661 3656 return (ENOTSUP);
3662 3657 }
3663 3658
3664 3659 mutex_exit(&sc->sc_glock);
3665 3660
3666 3661 return (IWH_SUCCESS);
3667 3662 }
3668 3663
3669 3664 /*
3670 3665 * invoked by GLD to start or open NIC
3671 3666 */
3672 3667 static int
3673 3668 iwh_m_start(void *arg)
3674 3669 {
3675 3670 iwh_sc_t *sc;
3676 3671 ieee80211com_t *ic;
3677 3672 int err = IWH_FAIL;
3678 3673
3679 3674 if (NULL == arg) {
3680 3675 return (EINVAL);
3681 3676 }
3682 3677 sc = (iwh_sc_t *)arg;
3683 3678 ic = &sc->sc_ic;
3684 3679
3685 3680 err = iwh_init(sc);
3686 3681 if (err != IWH_SUCCESS) {
3687 3682 /*
3688 3683 * The hw init err(eg. RF is OFF). Return Success to make
3689 3684 * the 'plumb' succeed. The iwh_thread() tries to re-init
3690 3685 * background.
3691 3686 */
3692 3687 atomic_or_32(&sc->sc_flags, IWH_F_HW_ERR_RECOVER);
3693 3688 return (IWH_SUCCESS);
3694 3689 }
3695 3690
3696 3691 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3697 3692
3698 3693 atomic_or_32(&sc->sc_flags, IWH_F_RUNNING);
3699 3694
3700 3695 return (IWH_SUCCESS);
3701 3696 }
3702 3697
3703 3698 /*
3704 3699 * invoked by GLD to stop or down NIC
3705 3700 */
3706 3701 static void
3707 3702 iwh_m_stop(void *arg)
3708 3703 {
3709 3704 iwh_sc_t *sc;
3710 3705 ieee80211com_t *ic;
3711 3706
3712 3707 if (NULL == arg) {
3713 3708 return;
3714 3709 }
3715 3710 sc = (iwh_sc_t *)arg;
3716 3711 ic = &sc->sc_ic;
3717 3712
3718 3713 iwh_stop(sc);
3719 3714
3720 3715 /*
3721 3716 * release buffer for calibration
3722 3717 */
3723 3718 iwh_release_calib_buffer(sc);
3724 3719
3725 3720 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3726 3721
3727 3722 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
3728 3723 atomic_and_32(&sc->sc_flags, ~IWH_F_RATE_AUTO_CTL);
3729 3724
3730 3725 atomic_and_32(&sc->sc_flags, ~IWH_F_RUNNING);
3731 3726 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
3732 3727 }
3733 3728
3734 3729 /*
3735 3730 * invoked by GLD to configure NIC
3736 3731 */
3737 3732 static int
3738 3733 iwh_m_unicst(void *arg, const uint8_t *macaddr)
3739 3734 {
3740 3735 iwh_sc_t *sc;
3741 3736 ieee80211com_t *ic;
3742 3737 int err = IWH_SUCCESS;
3743 3738
3744 3739 if (NULL == arg) {
3745 3740 return (EINVAL);
3746 3741 }
3747 3742 sc = (iwh_sc_t *)arg;
3748 3743 ic = &sc->sc_ic;
3749 3744
3750 3745 if (!IEEE80211_ADDR_EQ(ic->ic_macaddr, macaddr)) {
3751 3746 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr);
3752 3747 mutex_enter(&sc->sc_glock);
3753 3748 err = iwh_config(sc);
3754 3749 mutex_exit(&sc->sc_glock);
3755 3750 if (err != IWH_SUCCESS) {
3756 3751 cmn_err(CE_WARN, "iwh_m_unicst(): "
3757 3752 "failed to configure device\n");
3758 3753 goto fail;
3759 3754 }
3760 3755 }
3761 3756
3762 3757 fail:
3763 3758 return (err);
3764 3759 }
3765 3760
3766 3761 /* ARGSUSED */
3767 3762 static int
3768 3763 iwh_m_multicst(void *arg, boolean_t add, const uint8_t *m)
3769 3764 {
3770 3765 return (IWH_SUCCESS);
3771 3766 }
3772 3767
3773 3768 /* ARGSUSED */
3774 3769 static int
3775 3770 iwh_m_promisc(void *arg, boolean_t on)
3776 3771 {
3777 3772 return (IWH_SUCCESS);
3778 3773 }
3779 3774
3780 3775 /*
3781 3776 * kernel thread to deal with exceptional situation
3782 3777 */
3783 3778 static void
3784 3779 iwh_thread(iwh_sc_t *sc)
3785 3780 {
3786 3781 ieee80211com_t *ic = &sc->sc_ic;
3787 3782 clock_t clk;
3788 3783 int err, n = 0, timeout = 0;
3789 3784 uint32_t tmp;
3790 3785 #ifdef DEBUG
3791 3786 int times = 0;
3792 3787 #endif
3793 3788
3794 3789 while (sc->sc_mf_thread_switch) {
3795 3790 tmp = IWH_READ(sc, CSR_GP_CNTRL);
3796 3791 if (tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) {
3797 3792 atomic_and_32(&sc->sc_flags, ~IWH_F_RADIO_OFF);
3798 3793 } else {
3799 3794 atomic_or_32(&sc->sc_flags, IWH_F_RADIO_OFF);
3800 3795 }
3801 3796
3802 3797 /*
3803 3798 * If in SUSPEND or the RF is OFF, do nothing.
3804 3799 */
3805 3800 if (sc->sc_flags & IWH_F_RADIO_OFF) {
3806 3801 delay(drv_usectohz(100000));
3807 3802 continue;
3808 3803 }
3809 3804
3810 3805 /*
3811 3806 * recovery fatal error
3812 3807 */
3813 3808 if (ic->ic_mach &&
3814 3809 (sc->sc_flags & IWH_F_HW_ERR_RECOVER)) {
3815 3810
3816 3811 IWH_DBG((IWH_DEBUG_FW, "iwh_thread(): "
3817 3812 "try to recover fatal hw error: %d\n", times++));
3818 3813
3819 3814 iwh_stop(sc);
3820 3815
3821 3816 if (IWH_CHK_FAST_RECOVER(sc)) {
3822 3817 /*
3823 3818 * save runtime configuration
3824 3819 */
3825 3820 bcopy(&sc->sc_config, &sc->sc_config_save,
3826 3821 sizeof (sc->sc_config));
3827 3822 } else {
3828 3823 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3829 3824 delay(drv_usectohz(2000000 + n*500000));
3830 3825 }
3831 3826
3832 3827 err = iwh_init(sc);
3833 3828 if (err != IWH_SUCCESS) {
3834 3829 n++;
3835 3830 if (n < 20) {
3836 3831 continue;
3837 3832 }
3838 3833 }
3839 3834
3840 3835 n = 0;
3841 3836 if (!err) {
3842 3837 atomic_or_32(&sc->sc_flags, IWH_F_RUNNING);
3843 3838 }
3844 3839
3845 3840
3846 3841 if (!IWH_CHK_FAST_RECOVER(sc) ||
3847 3842 iwh_fast_recover(sc) != IWH_SUCCESS) {
3848 3843 atomic_and_32(&sc->sc_flags,
3849 3844 ~IWH_F_HW_ERR_RECOVER);
3850 3845
3851 3846 delay(drv_usectohz(2000000));
3852 3847 if (sc->sc_ostate != IEEE80211_S_INIT) {
3853 3848 ieee80211_new_state(ic,
3854 3849 IEEE80211_S_SCAN, 0);
3855 3850 }
3856 3851 }
3857 3852 }
3858 3853
3859 3854 if (ic->ic_mach &&
3860 3855 (sc->sc_flags & IWH_F_SCANNING) && sc->sc_scan_pending) {
3861 3856 IWH_DBG((IWH_DEBUG_SCAN, "iwh_thread(): "
3862 3857 "wait for probe response\n"));
3863 3858
3864 3859 sc->sc_scan_pending--;
3865 3860 delay(drv_usectohz(200000));
3866 3861 ieee80211_next_scan(ic);
3867 3862 }
3868 3863
3869 3864 /*
3870 3865 * rate ctl
3871 3866 */
3872 3867 if (ic->ic_mach &&
3873 3868 (sc->sc_flags & IWH_F_RATE_AUTO_CTL)) {
3874 3869 clk = ddi_get_lbolt();
3875 3870 if (clk > sc->sc_clk + drv_usectohz(1000000)) {
3876 3871 iwh_amrr_timeout(sc);
3877 3872 }
3878 3873 }
3879 3874
3880 3875 if ((ic->ic_state == IEEE80211_S_RUN) &&
3881 3876 (ic->ic_beaconmiss++ > 100)) { /* 10 seconds */
3882 3877 cmn_err(CE_WARN, "iwh: beacon missed for 10 seconds\n");
3883 3878 (void) ieee80211_new_state(ic,
3884 3879 IEEE80211_S_INIT, -1);
3885 3880 }
3886 3881
3887 3882 delay(drv_usectohz(100000));
3888 3883
3889 3884 mutex_enter(&sc->sc_mt_lock);
3890 3885 if (sc->sc_tx_timer) {
3891 3886 timeout++;
3892 3887 if (10 == timeout) {
3893 3888 sc->sc_tx_timer--;
3894 3889 if (0 == sc->sc_tx_timer) {
3895 3890 atomic_or_32(&sc->sc_flags,
3896 3891 IWH_F_HW_ERR_RECOVER);
3897 3892 sc->sc_ostate = IEEE80211_S_RUN;
3898 3893 IWH_DBG((IWH_DEBUG_FW, "iwh_thread(): "
3899 3894 "try to recover from "
3900 3895 "send fail\n"));
3901 3896 }
3902 3897 timeout = 0;
3903 3898 }
3904 3899 }
3905 3900 mutex_exit(&sc->sc_mt_lock);
3906 3901 }
3907 3902
3908 3903 mutex_enter(&sc->sc_mt_lock);
3909 3904 sc->sc_mf_thread = NULL;
3910 3905 cv_signal(&sc->sc_mt_cv);
3911 3906 mutex_exit(&sc->sc_mt_lock);
3912 3907 }
3913 3908
3914 3909 /*
3915 3910 * Send a command to the ucode.
3916 3911 */
3917 3912 static int
3918 3913 iwh_cmd(iwh_sc_t *sc, int code, const void *buf, int size, int async)
3919 3914 {
3920 3915 iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
3921 3916 iwh_tx_desc_t *desc;
3922 3917 iwh_cmd_t *cmd;
3923 3918
3924 3919 ASSERT(size <= sizeof (cmd->data));
3925 3920 ASSERT(mutex_owned(&sc->sc_glock));
3926 3921
3927 3922 IWH_DBG((IWH_DEBUG_CMD, "iwh_cmd() "
3928 3923 "code[%d]", code));
3929 3924 desc = ring->data[ring->cur].desc;
3930 3925 cmd = ring->data[ring->cur].cmd;
3931 3926
3932 3927 cmd->hdr.type = (uint8_t)code;
3933 3928 cmd->hdr.flags = 0;
3934 3929 cmd->hdr.qid = ring->qid;
3935 3930 cmd->hdr.idx = ring->cur;
3936 3931 bcopy(buf, cmd->data, size);
3937 3932 (void) memset(desc, 0, sizeof (*desc));
3938 3933
3939 3934 desc->val0 = 1 << 24;
3940 3935 desc->pa[0].tb1_addr =
3941 3936 (uint32_t)(ring->data[ring->cur].paddr_cmd & 0xffffffff);
3942 3937 desc->pa[0].val1 = ((4 + size) << 4) & 0xfff0;
3943 3938
3944 3939 if (async) {
3945 3940 sc->sc_cmd_accum++;
3946 3941 }
3947 3942
3948 3943 /*
3949 3944 * kick cmd ring XXX
3950 3945 */
3951 3946 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3952 3947 tfd_offset[ring->cur].val = 8;
3953 3948 if (ring->cur < IWH_MAX_WIN_SIZE) {
3954 3949 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3955 3950 tfd_offset[IWH_QUEUE_SIZE + ring->cur].val = 8;
3956 3951 }
3957 3952 ring->cur = (ring->cur + 1) % ring->count;
3958 3953 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3959 3954
3960 3955 if (async) {
3961 3956 return (IWH_SUCCESS);
3962 3957 } else {
3963 3958 clock_t clk;
3964 3959
3965 3960 clk = ddi_get_lbolt() + drv_usectohz(2000000);
3966 3961 while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) {
3967 3962 if (cv_timedwait(&sc->sc_cmd_cv,
3968 3963 &sc->sc_glock, clk) < 0) {
3969 3964 break;
3970 3965 }
3971 3966 }
3972 3967
3973 3968 if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) {
3974 3969 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3975 3970 return (IWH_SUCCESS);
3976 3971 } else {
3977 3972 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3978 3973 return (IWH_FAIL);
3979 3974 }
3980 3975 }
3981 3976 }
3982 3977
3983 3978 /*
3984 3979 * require ucode seting led of NIC
3985 3980 */
3986 3981 static void
3987 3982 iwh_set_led(iwh_sc_t *sc, uint8_t id, uint8_t off, uint8_t on)
3988 3983 {
3989 3984 iwh_led_cmd_t led;
3990 3985
3991 3986 led.interval = LE_32(100000); /* unit: 100ms */
3992 3987 led.id = id;
3993 3988 led.off = off;
3994 3989 led.on = on;
3995 3990
3996 3991 (void) iwh_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1);
3997 3992 }
3998 3993
3999 3994 /*
4000 3995 * necessary setting to NIC before authentication
4001 3996 */
4002 3997 static int
4003 3998 iwh_hw_set_before_auth(iwh_sc_t *sc)
4004 3999 {
4005 4000 ieee80211com_t *ic = &sc->sc_ic;
4006 4001 ieee80211_node_t *in = ic->ic_bss;
4007 4002 int err = IWH_FAIL;
4008 4003
4009 4004 /*
4010 4005 * update adapter's configuration according
4011 4006 * the info of target AP
4012 4007 */
4013 4008 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
4014 4009 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan));
4015 4010
4016 4011 if (ic->ic_curmode != IEEE80211_MODE_11NG) {
4017 4012
4018 4013 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0;
4019 4014 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0;
4020 4015 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0;
4021 4016
4022 4017 if (IEEE80211_MODE_11B == ic->ic_curmode) {
4023 4018 sc->sc_config.cck_basic_rates = 0x03;
4024 4019 sc->sc_config.ofdm_basic_rates = 0;
4025 4020 } else if ((in->in_chan != IEEE80211_CHAN_ANYC) &&
4026 4021 (IEEE80211_IS_CHAN_5GHZ(in->in_chan))) {
4027 4022 sc->sc_config.cck_basic_rates = 0;
4028 4023 sc->sc_config.ofdm_basic_rates = 0x15;
4029 4024 } else { /* assume 802.11b/g */
4030 4025 sc->sc_config.cck_basic_rates = 0x0f;
4031 4026 sc->sc_config.ofdm_basic_rates = 0xff;
4032 4027 }
4033 4028 }
4034 4029
4035 4030 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
4036 4031 RXON_FLG_SHORT_SLOT_MSK);
4037 4032
4038 4033 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
4039 4034 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK);
4040 4035 } else {
4041 4036 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK);
4042 4037 }
4043 4038
4044 4039 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) {
4045 4040 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4046 4041 } else {
4047 4042 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK);
4048 4043 }
4049 4044
4050 4045 IWH_DBG((IWH_DEBUG_80211, "iwh_hw_set_before_auth(): "
4051 4046 "config chan %d flags %x "
4052 4047 "filter_flags %x cck %x ofdm %x"
4053 4048 " bssid:%02x:%02x:%02x:%02x:%02x:%2x\n",
4054 4049 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags),
4055 4050 LE_32(sc->sc_config.filter_flags),
4056 4051 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates,
4057 4052 sc->sc_config.bssid[0], sc->sc_config.bssid[1],
4058 4053 sc->sc_config.bssid[2], sc->sc_config.bssid[3],
4059 4054 sc->sc_config.bssid[4], sc->sc_config.bssid[5]));
4060 4055
4061 4056 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
4062 4057 sizeof (iwh_rxon_cmd_t), 1);
4063 4058 if (err != IWH_SUCCESS) {
4064 4059 cmn_err(CE_WARN, "iwh_hw_set_before_auth(): "
4065 4060 "failed to config chan%d\n", sc->sc_config.chan);
4066 4061 return (err);
4067 4062 }
4068 4063
4069 4064 if ((sc->sc_dev_id != 0x423c) &&
4070 4065 (sc->sc_dev_id != 0x423d)) {
4071 4066 err = iwh_tx_power_table(sc, 1);
4072 4067 if (err != IWH_SUCCESS) {
4073 4068 return (err);
4074 4069 }
4075 4070 }
4076 4071
4077 4072 /*
4078 4073 * add default AP node
4079 4074 */
4080 4075 err = iwh_add_ap_sta(sc);
4081 4076 if (err != IWH_SUCCESS) {
4082 4077 return (err);
4083 4078 }
4084 4079
4085 4080 if ((sc->sc_dev_id != 0x423c) &&
4086 4081 (sc->sc_dev_id != 0x423d)) {
4087 4082 /*
4088 4083 * set up retry rate table for AP node
4089 4084 */
4090 4085 err = iwh_ap_lq(sc);
4091 4086 if (err != IWH_SUCCESS) {
4092 4087 return (err);
4093 4088 }
4094 4089 }
4095 4090
4096 4091 return (err);
4097 4092 }
4098 4093
4099 4094 /*
4100 4095 * Send a scan request(assembly scan cmd) to the firmware.
4101 4096 */
4102 4097 static int
4103 4098 iwh_scan(iwh_sc_t *sc)
4104 4099 {
4105 4100 ieee80211com_t *ic = &sc->sc_ic;
4106 4101 iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
4107 4102 iwh_tx_desc_t *desc;
4108 4103 iwh_tx_data_t *data;
4109 4104 iwh_cmd_t *cmd;
4110 4105 iwh_scan_hdr_t *hdr;
4111 4106 iwh_scan_chan_t chan;
4112 4107 struct ieee80211_frame *wh;
4113 4108 ieee80211_node_t *in = ic->ic_bss;
4114 4109 uint8_t essid[IEEE80211_NWID_LEN+1];
4115 4110 struct ieee80211_rateset *rs;
4116 4111 enum ieee80211_phymode mode;
4117 4112 uint8_t *frm;
4118 4113 int i, pktlen, nrates;
4119 4114
4120 4115 data = &ring->data[ring->cur];
4121 4116 desc = data->desc;
4122 4117 cmd = (iwh_cmd_t *)data->dma_data.mem_va;
4123 4118
4124 4119 cmd->hdr.type = REPLY_SCAN_CMD;
4125 4120 cmd->hdr.flags = 0;
4126 4121 cmd->hdr.qid = ring->qid;
4127 4122 cmd->hdr.idx = ring->cur | 0x40;
4128 4123
4129 4124 hdr = (iwh_scan_hdr_t *)cmd->data;
4130 4125 (void) memset(hdr, 0, sizeof (iwh_scan_hdr_t));
4131 4126 hdr->nchan = 1;
4132 4127 hdr->quiet_time = LE_16(50);
4133 4128 hdr->quiet_plcp_th = LE_16(1);
4134 4129
4135 4130 hdr->flags = LE_32(RXON_FLG_BAND_24G_MSK);
4136 4131 hdr->rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
4137 4132 (0x7 << RXON_RX_CHAIN_VALID_POS) |
4138 4133 (0x2 << RXON_RX_CHAIN_FORCE_SEL_POS) |
4139 4134 (0x2 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
4140 4135
4141 4136 hdr->tx_cmd.tx_flags = LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
4142 4137 hdr->tx_cmd.sta_id = IWH_BROADCAST_ID;
4143 4138 hdr->tx_cmd.stop_time.life_time = LE_32(0xffffffff);
4144 4139 hdr->tx_cmd.rate.r.rate_n_flags = LE_32(iwh_rate_to_plcp(2));
4145 4140 hdr->tx_cmd.rate.r.rate_n_flags |=
4146 4141 LE_32(RATE_MCS_ANT_B_MSK |RATE_MCS_CCK_MSK);
4147 4142 hdr->direct_scan[0].len = ic->ic_des_esslen;
4148 4143 hdr->direct_scan[0].id = IEEE80211_ELEMID_SSID;
4149 4144
4150 4145 hdr->filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4151 4146 RXON_FILTER_BCON_AWARE_MSK);
4152 4147
4153 4148 if (ic->ic_des_esslen) {
4154 4149 bcopy(ic->ic_des_essid, essid, ic->ic_des_esslen);
4155 4150 essid[ic->ic_des_esslen] = '\0';
4156 4151 IWH_DBG((IWH_DEBUG_SCAN, "iwh_scan(): "
4157 4152 "directed scan %s\n", essid));
4158 4153
4159 4154 bcopy(ic->ic_des_essid, hdr->direct_scan[0].ssid,
4160 4155 ic->ic_des_esslen);
4161 4156 } else {
4162 4157 bzero(hdr->direct_scan[0].ssid,
4163 4158 sizeof (hdr->direct_scan[0].ssid));
4164 4159 }
4165 4160
4166 4161 /*
4167 4162 * a probe request frame is required after the REPLY_SCAN_CMD
4168 4163 */
4169 4164 wh = (struct ieee80211_frame *)(hdr + 1);
4170 4165 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
4171 4166 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
4172 4167 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
4173 4168 (void) memset(wh->i_addr1, 0xff, 6);
4174 4169 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_macaddr);
4175 4170 (void) memset(wh->i_addr3, 0xff, 6);
4176 4171 *(uint16_t *)&wh->i_dur[0] = 0;
4177 4172 *(uint16_t *)&wh->i_seq[0] = 0;
4178 4173
4179 4174 frm = (uint8_t *)(wh + 1);
4180 4175
4181 4176 /*
4182 4177 * essid IE
4183 4178 */
4184 4179 if (in->in_esslen) {
4185 4180 bcopy(in->in_essid, essid, in->in_esslen);
4186 4181 essid[in->in_esslen] = '\0';
4187 4182 IWH_DBG((IWH_DEBUG_SCAN, "iwh_scan(): "
4188 4183 "probe with ESSID %s\n",
4189 4184 essid));
4190 4185 }
4191 4186 *frm++ = IEEE80211_ELEMID_SSID;
4192 4187 *frm++ = in->in_esslen;
4193 4188 bcopy(in->in_essid, frm, in->in_esslen);
4194 4189 frm += in->in_esslen;
4195 4190
4196 4191 mode = ieee80211_chan2mode(ic, ic->ic_curchan);
4197 4192 rs = &ic->ic_sup_rates[mode];
4198 4193
4199 4194 /*
4200 4195 * supported rates IE
4201 4196 */
4202 4197 *frm++ = IEEE80211_ELEMID_RATES;
4203 4198 nrates = rs->ir_nrates;
4204 4199 if (nrates > IEEE80211_RATE_SIZE) {
4205 4200 nrates = IEEE80211_RATE_SIZE;
4206 4201 }
4207 4202
4208 4203 *frm++ = (uint8_t)nrates;
4209 4204 bcopy(rs->ir_rates, frm, nrates);
4210 4205 frm += nrates;
4211 4206
4212 4207 /*
4213 4208 * supported xrates IE
4214 4209 */
4215 4210 if (rs->ir_nrates > IEEE80211_RATE_SIZE) {
4216 4211 nrates = rs->ir_nrates - IEEE80211_RATE_SIZE;
4217 4212 *frm++ = IEEE80211_ELEMID_XRATES;
4218 4213 *frm++ = (uint8_t)nrates;
4219 4214 bcopy(rs->ir_rates + IEEE80211_RATE_SIZE, frm, nrates);
4220 4215 frm += nrates;
4221 4216 }
4222 4217
4223 4218 /*
4224 4219 * optionnal IE (usually for wpa)
4225 4220 */
4226 4221 if (ic->ic_opt_ie != NULL) {
4227 4222 bcopy(ic->ic_opt_ie, frm, ic->ic_opt_ie_len);
4228 4223 frm += ic->ic_opt_ie_len;
4229 4224 }
4230 4225
4231 4226 /* setup length of probe request */
4232 4227 hdr->tx_cmd.len = LE_16(_PTRDIFF(frm, wh));
4233 4228 hdr->len = LE_16(hdr->nchan * sizeof (iwh_scan_chan_t) +
4234 4229 LE_16(hdr->tx_cmd.len) + sizeof (iwh_scan_hdr_t));
4235 4230
4236 4231 /*
4237 4232 * the attribute of the scan channels are required after the probe
4238 4233 * request frame.
4239 4234 */
4240 4235 for (i = 1; i <= hdr->nchan; i++) {
4241 4236 if (ic->ic_des_esslen) {
4242 4237 chan.type = LE_32(3);
4243 4238 } else {
4244 4239 chan.type = LE_32(1);
4245 4240 }
4246 4241
4247 4242 chan.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
4248 4243 chan.tpc.tx_gain = 0x28;
4249 4244 chan.tpc.dsp_atten = 110;
4250 4245 chan.active_dwell = LE_16(50);
4251 4246 chan.passive_dwell = LE_16(120);
4252 4247
4253 4248 bcopy(&chan, frm, sizeof (iwh_scan_chan_t));
4254 4249 frm += sizeof (iwh_scan_chan_t);
4255 4250 }
4256 4251
4257 4252 pktlen = _PTRDIFF(frm, cmd);
4258 4253
4259 4254 (void) memset(desc, 0, sizeof (*desc));
4260 4255 desc->val0 = 1 << 24;
4261 4256 desc->pa[0].tb1_addr =
4262 4257 (uint32_t)(data->dma_data.cookie.dmac_address & 0xffffffff);
4263 4258 desc->pa[0].val1 = (pktlen << 4) & 0xfff0;
4264 4259
4265 4260 /*
4266 4261 * maybe for cmd, filling the byte cnt table is not necessary.
4267 4262 * anyway, we fill it here.
4268 4263 */
4269 4264 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]
4270 4265 .tfd_offset[ring->cur].val = 8;
4271 4266 if (ring->cur < IWH_MAX_WIN_SIZE) {
4272 4267 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
4273 4268 tfd_offset[IWH_QUEUE_SIZE + ring->cur].val = 8;
4274 4269 }
4275 4270
4276 4271 /*
4277 4272 * kick cmd ring
4278 4273 */
4279 4274 ring->cur = (ring->cur + 1) % ring->count;
4280 4275 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4281 4276
4282 4277 return (IWH_SUCCESS);
4283 4278 }
4284 4279
4285 4280 /*
4286 4281 * configure NIC by using ucode commands after loading ucode.
4287 4282 */
4288 4283 static int
4289 4284 iwh_config(iwh_sc_t *sc)
4290 4285 {
4291 4286 ieee80211com_t *ic = &sc->sc_ic;
4292 4287 iwh_powertable_cmd_t powertable;
4293 4288 iwh_bt_cmd_t bt;
4294 4289 iwh_add_sta_t node;
4295 4290 iwh_rem_sta_t rm_sta;
4296 4291 const uint8_t bcast[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
4297 4292 iwh_link_quality_cmd_t link_quality;
4298 4293 int i, err = IWH_FAIL;
4299 4294 uint16_t masks = 0;
4300 4295
4301 4296 /*
4302 4297 * set power mode. Disable power management at present, do it later
4303 4298 */
4304 4299 (void) memset(&powertable, 0, sizeof (powertable));
4305 4300 powertable.flags = LE_16(0x8);
4306 4301 err = iwh_cmd(sc, POWER_TABLE_CMD, &powertable,
4307 4302 sizeof (powertable), 0);
4308 4303 if (err != IWH_SUCCESS) {
4309 4304 cmn_err(CE_WARN, "iwh_config(): "
4310 4305 "failed to set power mode\n");
4311 4306 return (err);
4312 4307 }
4313 4308
4314 4309 /*
4315 4310 * configure bt coexistence
4316 4311 */
4317 4312 (void) memset(&bt, 0, sizeof (bt));
4318 4313 bt.flags = 3;
4319 4314 bt.lead_time = 0xaa;
4320 4315 bt.max_kill = 1;
4321 4316 err = iwh_cmd(sc, REPLY_BT_CONFIG, &bt,
4322 4317 sizeof (bt), 0);
4323 4318 if (err != IWH_SUCCESS) {
4324 4319 cmn_err(CE_WARN, "iwh_config(): "
4325 4320 "failed to configurate bt coexistence\n");
4326 4321 return (err);
4327 4322 }
4328 4323
4329 4324 /*
4330 4325 * configure rxon
4331 4326 */
4332 4327 (void) memset(&sc->sc_config, 0, sizeof (iwh_rxon_cmd_t));
4333 4328 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
4334 4329 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
4335 4330 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
4336 4331 sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK);
4337 4332 sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4338 4333 RXON_FLG_CHANNEL_MODE_PURE_40_MSK));
4339 4334
4340 4335 switch (ic->ic_opmode) {
4341 4336 case IEEE80211_M_STA:
4342 4337 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
4343 4338 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4344 4339 RXON_FILTER_DIS_DECRYPT_MSK |
4345 4340 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
4346 4341 break;
4347 4342
4348 4343 case IEEE80211_M_IBSS:
4349 4344 case IEEE80211_M_AHDEMO:
4350 4345 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
4351 4346
4352 4347 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4353 4348 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4354 4349 RXON_FILTER_DIS_DECRYPT_MSK |
4355 4350 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
4356 4351 break;
4357 4352
4358 4353 case IEEE80211_M_HOSTAP:
4359 4354 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
4360 4355 break;
4361 4356
4362 4357 case IEEE80211_M_MONITOR:
4363 4358 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
4364 4359 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4365 4360 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
4366 4361 break;
4367 4362 }
4368 4363
4369 4364 /*
4370 4365 * Support all CCK rates.
4371 4366 */
4372 4367 sc->sc_config.cck_basic_rates = 0x0f;
4373 4368
4374 4369 /*
4375 4370 * Support all OFDM rates.
4376 4371 */
4377 4372 sc->sc_config.ofdm_basic_rates = 0xff;
4378 4373
4379 4374 /*
4380 4375 * Determine HT supported rates.
4381 4376 */
4382 4377 switch (sc->sc_ht_conf.rx_stream_count) {
4383 4378 case 3:
4384 4379 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0xff;
4385 4380 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
4386 4381 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4387 4382 break;
4388 4383 case 2:
4389 4384 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
4390 4385 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4391 4386 break;
4392 4387 case 1:
4393 4388 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4394 4389 break;
4395 4390 default:
4396 4391 cmn_err(CE_WARN, "iwh_config(): "
4397 4392 "RX stream count %d is not in suitable range\n",
4398 4393 sc->sc_ht_conf.rx_stream_count);
4399 4394 return (IWH_FAIL);
4400 4395 }
4401 4396
4402 4397 /*
4403 4398 * set RX chains/antennas.
4404 4399 */
4405 4400 iwh_config_rxon_chain(sc);
4406 4401
4407 4402 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
4408 4403 sizeof (iwh_rxon_cmd_t), 0);
4409 4404 if (err != IWH_SUCCESS) {
4410 4405 cmn_err(CE_WARN, "iwh_config(): "
4411 4406 "failed to set configure command\n");
4412 4407 return (err);
4413 4408 }
4414 4409
4415 4410 /*
4416 4411 * remove all nodes in NIC
4417 4412 */
4418 4413 (void) memset(&rm_sta, 0, sizeof (rm_sta));
4419 4414 rm_sta.num_sta = 1;
4420 4415 bcopy(bcast, rm_sta.addr, 6);
4421 4416
4422 4417 err = iwh_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwh_rem_sta_t), 0);
4423 4418 if (err != IWH_SUCCESS) {
4424 4419 cmn_err(CE_WARN, "iwh_config(): "
4425 4420 "failed to remove broadcast node in hardware.\n");
4426 4421 return (err);
4427 4422 }
4428 4423
4429 4424 if ((sc->sc_dev_id != 0x423c) &&
4430 4425 (sc->sc_dev_id != 0x423d)) {
4431 4426 /*
4432 4427 * configure TX power table
4433 4428 */
4434 4429 err = iwh_tx_power_table(sc, 0);
4435 4430 if (err != IWH_SUCCESS) {
4436 4431 return (err);
4437 4432 }
4438 4433 }
4439 4434
4440 4435 /*
4441 4436 * add broadcast node so that we can send broadcast frame
4442 4437 */
4443 4438 (void) memset(&node, 0, sizeof (node));
4444 4439 (void) memset(node.sta.addr, 0xff, 6);
4445 4440 node.mode = 0;
4446 4441 node.sta.sta_id = IWH_BROADCAST_ID;
4447 4442 node.station_flags = 0;
4448 4443
4449 4444 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0);
4450 4445 if (err != IWH_SUCCESS) {
4451 4446 cmn_err(CE_WARN, "iwh_config(): "
4452 4447 "failed to add broadcast node\n");
4453 4448 return (err);
4454 4449 }
4455 4450
4456 4451 if ((sc->sc_dev_id != 0x423c) &&
4457 4452 (sc->sc_dev_id != 0x423d)) {
4458 4453 /*
4459 4454 * TX_LINK_QUALITY cmd
4460 4455 */
4461 4456 (void) memset(&link_quality, 0, sizeof (link_quality));
4462 4457 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4463 4458 masks |= RATE_MCS_CCK_MSK;
4464 4459 masks |= RATE_MCS_ANT_B_MSK;
4465 4460 masks &= ~RATE_MCS_ANT_A_MSK;
4466 4461 link_quality.rate_n_flags[i] =
4467 4462 LE_32(iwh_rate_to_plcp(2) | masks);
4468 4463 }
4469 4464
4470 4465 link_quality.general_params.single_stream_ant_msk = 2;
4471 4466 link_quality.general_params.dual_stream_ant_msk = 3;
4472 4467 link_quality.agg_params.agg_dis_start_th = 3;
4473 4468 link_quality.agg_params.agg_time_limit = LE_16(4000);
4474 4469 link_quality.sta_id = IWH_BROADCAST_ID;
4475 4470 err = iwh_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
4476 4471 sizeof (link_quality), 0);
4477 4472 if (err != IWH_SUCCESS) {
4478 4473 cmn_err(CE_WARN, "iwh_config(): "
4479 4474 "failed to config link quality table\n");
4480 4475 return (err);
4481 4476 }
4482 4477 }
4483 4478
4484 4479 return (err);
4485 4480 }
4486 4481
4487 4482 /*
4488 4483 * quiesce(9E) entry point.
4489 4484 * This function is called when the system is single-threaded at high
4490 4485 * PIL with preemption disabled. Therefore, this function must not be
4491 4486 * blocked.
4492 4487 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
4493 4488 * DDI_FAILURE indicates an error condition and should almost never happen.
4494 4489 */
4495 4490 static int
4496 4491 iwh_quiesce(dev_info_t *dip)
4497 4492 {
4498 4493 iwh_sc_t *sc;
4499 4494
4500 4495 sc = ddi_get_soft_state(iwh_soft_state_p, ddi_get_instance(dip));
4501 4496 if (sc == NULL) {
4502 4497 return (DDI_FAILURE);
4503 4498 }
4504 4499
4505 4500 #ifdef DEBUG
4506 4501 /*
4507 4502 * by pass any messages, if it's quiesce
4508 4503 */
4509 4504 iwh_dbg_flags = 0;
4510 4505 #endif
4511 4506
4512 4507 /*
4513 4508 * No more blocking is allowed while we are in the
4514 4509 * quiesce(9E) entry point.
4515 4510 */
4516 4511 atomic_or_32(&sc->sc_flags, IWH_F_QUIESCED);
4517 4512
4518 4513 /*
4519 4514 * Disable and mask all interrupts.
4520 4515 */
4521 4516 iwh_stop(sc);
4522 4517
4523 4518 return (DDI_SUCCESS);
4524 4519 }
4525 4520
4526 4521 static void
4527 4522 iwh_stop_master(iwh_sc_t *sc)
4528 4523 {
4529 4524 uint32_t tmp;
4530 4525 int n;
4531 4526
4532 4527 tmp = IWH_READ(sc, CSR_RESET);
4533 4528 IWH_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
4534 4529
4535 4530 tmp = IWH_READ(sc, CSR_GP_CNTRL);
4536 4531 if ((tmp & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE) ==
4537 4532 CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE) {
4538 4533 return;
4539 4534 }
4540 4535
4541 4536 for (n = 0; n < 2000; n++) {
4542 4537 if (IWH_READ(sc, CSR_RESET) &
4543 4538 CSR_RESET_REG_FLAG_MASTER_DISABLED) {
4544 4539 break;
4545 4540 }
4546 4541 DELAY(1000);
4547 4542 }
4548 4543
4549 4544 #ifdef DEBUG
4550 4545 if (2000 == n) {
4551 4546 IWH_DBG((IWH_DEBUG_HW, "iwh_stop_master(): "
4552 4547 "timeout waiting for master stop\n"));
4553 4548 }
4554 4549 #endif
4555 4550 }
4556 4551
4557 4552 static int
4558 4553 iwh_power_up(iwh_sc_t *sc)
4559 4554 {
4560 4555 uint32_t tmp;
4561 4556
4562 4557 iwh_mac_access_enter(sc);
4563 4558 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4564 4559 tmp &= ~APMG_PS_CTRL_REG_MSK_POWER_SRC;
4565 4560 tmp |= APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN;
4566 4561 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4567 4562 iwh_mac_access_exit(sc);
4568 4563
4569 4564 DELAY(5000);
4570 4565 return (IWH_SUCCESS);
4571 4566 }
4572 4567
4573 4568 /*
4574 4569 * hardware initialization
4575 4570 */
4576 4571 static int
4577 4572 iwh_preinit(iwh_sc_t *sc)
4578 4573 {
4579 4574 int n;
4580 4575 uint8_t vlink;
4581 4576 uint16_t radio_cfg;
4582 4577 uint32_t tmp;
4583 4578
4584 4579 /*
4585 4580 * clear any pending interrupts
4586 4581 */
4587 4582 IWH_WRITE(sc, CSR_INT, 0xffffffff);
4588 4583
4589 4584 tmp = IWH_READ(sc, CSR_GIO_CHICKEN_BITS);
4590 4585 IWH_WRITE(sc, CSR_GIO_CHICKEN_BITS,
4591 4586 tmp | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
4592 4587
4593 4588 tmp = IWH_READ(sc, CSR_ANA_PLL_CFG);
4594 4589 IWH_WRITE(sc, CSR_ANA_PLL_CFG, tmp | IWH_CSR_ANA_PLL_CFG);
4595 4590
4596 4591 tmp = IWH_READ(sc, CSR_GP_CNTRL);
4597 4592 IWH_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4598 4593
4599 4594 /*
4600 4595 * wait for clock ready
4601 4596 */
4602 4597 for (n = 0; n < 1000; n++) {
4603 4598 if (IWH_READ(sc, CSR_GP_CNTRL) &
4604 4599 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) {
4605 4600 break;
4606 4601 }
4607 4602 DELAY(10);
4608 4603 }
4609 4604
4610 4605 if (1000 == n) {
4611 4606 return (ETIMEDOUT);
4612 4607 }
4613 4608
4614 4609 iwh_mac_access_enter(sc);
4615 4610
4616 4611 iwh_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4617 4612
4618 4613 DELAY(20);
4619 4614 tmp = iwh_reg_read(sc, ALM_APMG_PCIDEV_STT);
4620 4615 iwh_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |
4621 4616 APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE);
4622 4617 iwh_mac_access_exit(sc);
4623 4618
4624 4619 radio_cfg = IWH_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION);
4625 4620 if (SP_RADIO_TYPE_MSK(radio_cfg) < SP_RADIO_TYPE_MAX) {
4626 4621 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4627 4622 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4628 4623 tmp | SP_RADIO_TYPE_MSK(radio_cfg) |
4629 4624 SP_RADIO_STEP_MSK(radio_cfg) |
4630 4625 SP_RADIO_DASH_MSK(radio_cfg));
4631 4626 } else {
4632 4627 cmn_err(CE_WARN, "iwh_preinit(): "
4633 4628 "radio configuration information in eeprom is wrong\n");
4634 4629 return (IWH_FAIL);
4635 4630 }
4636 4631
4637 4632
4638 4633 IWH_WRITE(sc, CSR_INT_COALESCING, 512 / 32);
4639 4634
4640 4635 (void) iwh_power_up(sc);
4641 4636
4642 4637 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) {
4643 4638 tmp = ddi_get32(sc->sc_cfg_handle,
4644 4639 (uint32_t *)(sc->sc_cfg_base + 0xe8));
4645 4640 ddi_put32(sc->sc_cfg_handle,
4646 4641 (uint32_t *)(sc->sc_cfg_base + 0xe8),
4647 4642 tmp & ~(1 << 11));
4648 4643 }
4649 4644
4650 4645 vlink = ddi_get8(sc->sc_cfg_handle,
4651 4646 (uint8_t *)(sc->sc_cfg_base + 0xf0));
4652 4647 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0),
4653 4648 vlink & ~2);
4654 4649
4655 4650 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4656 4651 tmp |= CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
4657 4652 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI;
4658 4653 IWH_WRITE(sc, CSR_SW_VER, tmp);
4659 4654
4660 4655 /*
4661 4656 * make sure power supply on each part of the hardware
4662 4657 */
4663 4658 iwh_mac_access_enter(sc);
4664 4659 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4665 4660 tmp |= APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ;
4666 4661 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4667 4662 DELAY(5);
4668 4663
4669 4664 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4670 4665 tmp &= ~APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ;
4671 4666 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4672 4667 iwh_mac_access_exit(sc);
4673 4668
4674 4669 return (IWH_SUCCESS);
4675 4670 }
4676 4671
4677 4672 /*
4678 4673 * set up semphore flag to own EEPROM
4679 4674 */
4680 4675 static int
4681 4676 iwh_eep_sem_down(iwh_sc_t *sc)
4682 4677 {
4683 4678 int count1, count2;
4684 4679 uint32_t tmp;
4685 4680
4686 4681 for (count1 = 0; count1 < 1000; count1++) {
4687 4682 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4688 4683 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4689 4684 tmp | CSR_HW_IF_CONFIG_REG_EEP_SEM);
4690 4685
4691 4686 for (count2 = 0; count2 < 2; count2++) {
4692 4687 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
4693 4688 CSR_HW_IF_CONFIG_REG_EEP_SEM) {
4694 4689 return (IWH_SUCCESS);
4695 4690 }
4696 4691 DELAY(10000);
4697 4692 }
4698 4693 }
4699 4694
4700 4695 return (IWH_FAIL);
4701 4696 }
4702 4697
4703 4698 /*
4704 4699 * reset semphore flag to release EEPROM
4705 4700 */
4706 4701 static void
4707 4702 iwh_eep_sem_up(iwh_sc_t *sc)
4708 4703 {
4709 4704 uint32_t tmp;
4710 4705
4711 4706 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4712 4707 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4713 4708 tmp & (~CSR_HW_IF_CONFIG_REG_EEP_SEM));
4714 4709 }
4715 4710
4716 4711 /*
4717 4712 * This function read all infomation from eeprom
4718 4713 */
4719 4714 static int
4720 4715 iwh_eep_load(iwh_sc_t *sc)
4721 4716 {
4722 4717 int i, rr;
4723 4718 uint32_t rv, tmp, eep_gp;
4724 4719 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map);
4725 4720 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map;
4726 4721
4727 4722 /*
4728 4723 * read eeprom gp register in CSR
4729 4724 */
4730 4725 eep_gp = IWH_READ(sc, CSR_EEPROM_GP);
4731 4726 if ((eep_gp & CSR_EEPROM_GP_VALID_MSK) ==
4732 4727 CSR_EEPROM_GP_BAD_SIGNATURE) {
4733 4728 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_eep_load(): "
4734 4729 "not find eeprom\n"));
4735 4730 return (IWH_FAIL);
4736 4731 }
4737 4732
4738 4733 rr = iwh_eep_sem_down(sc);
4739 4734 if (rr != 0) {
4740 4735 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_eep_load(): "
4741 4736 "driver failed to own EEPROM\n"));
4742 4737 return (IWH_FAIL);
4743 4738 }
4744 4739
4745 4740 for (addr = 0; addr < eep_sz; addr += 2) {
4746 4741 IWH_WRITE(sc, CSR_EEPROM_REG, addr<<1);
4747 4742 tmp = IWH_READ(sc, CSR_EEPROM_REG);
4748 4743 IWH_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
4749 4744
4750 4745 for (i = 0; i < 10; i++) {
4751 4746 rv = IWH_READ(sc, CSR_EEPROM_REG);
4752 4747 if (rv & 1) {
4753 4748 break;
4754 4749 }
4755 4750 DELAY(10);
4756 4751 }
4757 4752
4758 4753 if (!(rv & 1)) {
4759 4754 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_eep_load(): "
4760 4755 "time out when read eeprome\n"));
4761 4756 iwh_eep_sem_up(sc);
4762 4757 return (IWH_FAIL);
4763 4758 }
4764 4759
4765 4760 eep_p[addr/2] = LE_16(rv >> 16);
4766 4761 }
4767 4762
4768 4763 iwh_eep_sem_up(sc);
4769 4764 return (IWH_SUCCESS);
4770 4765 }
4771 4766
4772 4767 /*
4773 4768 * initialize mac address in ieee80211com_t struct
4774 4769 */
4775 4770 static void
4776 4771 iwh_get_mac_from_eep(iwh_sc_t *sc)
4777 4772 {
4778 4773 ieee80211com_t *ic = &sc->sc_ic;
4779 4774
4780 4775 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]);
4781 4776
4782 4777 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_get_mac_from_eep(): "
4783 4778 "mac:%2x:%2x:%2x:%2x:%2x:%2x\n",
4784 4779 ic->ic_macaddr[0], ic->ic_macaddr[1], ic->ic_macaddr[2],
4785 4780 ic->ic_macaddr[3], ic->ic_macaddr[4], ic->ic_macaddr[5]));
4786 4781 }
4787 4782
4788 4783 /*
4789 4784 * main initialization function
4790 4785 */
4791 4786 static int
4792 4787 iwh_init(iwh_sc_t *sc)
4793 4788 {
4794 4789 int err = IWH_FAIL;
4795 4790 clock_t clk;
4796 4791
4797 4792 /*
4798 4793 * release buffer for calibration
4799 4794 */
4800 4795 iwh_release_calib_buffer(sc);
4801 4796
4802 4797 mutex_enter(&sc->sc_glock);
4803 4798 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4804 4799
4805 4800 err = iwh_init_common(sc);
4806 4801 if (err != IWH_SUCCESS) {
4807 4802 mutex_exit(&sc->sc_glock);
4808 4803 return (IWH_FAIL);
4809 4804 }
4810 4805
4811 4806 /*
4812 4807 * backup ucode data part for future use.
4813 4808 */
4814 4809 bcopy(sc->sc_dma_fw_data.mem_va,
4815 4810 sc->sc_dma_fw_data_bak.mem_va,
4816 4811 sc->sc_dma_fw_data.alength);
4817 4812
4818 4813 /* load firmware init segment into NIC */
4819 4814 err = iwh_load_init_firmware(sc);
4820 4815 if (err != IWH_SUCCESS) {
4821 4816 cmn_err(CE_WARN, "iwh_init(): "
4822 4817 "failed to setup init firmware\n");
4823 4818 mutex_exit(&sc->sc_glock);
4824 4819 return (IWH_FAIL);
4825 4820 }
4826 4821
4827 4822 /*
4828 4823 * now press "execute" start running
4829 4824 */
4830 4825 IWH_WRITE(sc, CSR_RESET, 0);
4831 4826
4832 4827 clk = ddi_get_lbolt() + drv_usectohz(1000000);
4833 4828 while (!(sc->sc_flags & IWH_F_FW_INIT)) {
4834 4829 if (cv_timedwait(&sc->sc_ucode_cv,
4835 4830 &sc->sc_glock, clk) < 0) {
4836 4831 break;
4837 4832 }
4838 4833 }
4839 4834
4840 4835 if (!(sc->sc_flags & IWH_F_FW_INIT)) {
4841 4836 cmn_err(CE_WARN, "iwh_init(): "
4842 4837 "failed to process init alive.\n");
4843 4838 mutex_exit(&sc->sc_glock);
4844 4839 return (IWH_FAIL);
4845 4840 }
4846 4841
4847 4842 mutex_exit(&sc->sc_glock);
4848 4843
4849 4844 /*
4850 4845 * stop chipset for initializing chipset again
4851 4846 */
4852 4847 iwh_stop(sc);
4853 4848
4854 4849 mutex_enter(&sc->sc_glock);
4855 4850 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4856 4851
4857 4852 err = iwh_init_common(sc);
4858 4853 if (err != IWH_SUCCESS) {
4859 4854 mutex_exit(&sc->sc_glock);
4860 4855 return (IWH_FAIL);
4861 4856 }
4862 4857
4863 4858 /*
4864 4859 * load firmware run segment into NIC
4865 4860 */
4866 4861 err = iwh_load_run_firmware(sc);
4867 4862 if (err != IWH_SUCCESS) {
4868 4863 cmn_err(CE_WARN, "iwh_init(): "
4869 4864 "failed to setup run firmware\n");
4870 4865 mutex_exit(&sc->sc_glock);
4871 4866 return (IWH_FAIL);
4872 4867 }
4873 4868
4874 4869 /*
4875 4870 * now press "execute" start running
4876 4871 */
4877 4872 IWH_WRITE(sc, CSR_RESET, 0);
4878 4873
4879 4874 clk = ddi_get_lbolt() + drv_usectohz(1000000);
4880 4875 while (!(sc->sc_flags & IWH_F_FW_INIT)) {
4881 4876 if (cv_timedwait(&sc->sc_ucode_cv,
4882 4877 &sc->sc_glock, clk) < 0) {
4883 4878 break;
4884 4879 }
4885 4880 }
4886 4881
4887 4882 if (!(sc->sc_flags & IWH_F_FW_INIT)) {
4888 4883 cmn_err(CE_WARN, "iwh_init(): "
4889 4884 "failed to process runtime alive.\n");
4890 4885 mutex_exit(&sc->sc_glock);
4891 4886 return (IWH_FAIL);
4892 4887 }
4893 4888
4894 4889 mutex_exit(&sc->sc_glock);
4895 4890
4896 4891 DELAY(1000);
4897 4892
4898 4893 mutex_enter(&sc->sc_glock);
4899 4894 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4900 4895
4901 4896 /*
4902 4897 * at this point, the firmware is loaded OK, then config the hardware
4903 4898 * with the ucode API, including rxon, txpower, etc.
4904 4899 */
4905 4900 err = iwh_config(sc);
4906 4901 if (err) {
4907 4902 cmn_err(CE_WARN, "iwh_init(): "
4908 4903 "failed to configure device\n");
4909 4904 mutex_exit(&sc->sc_glock);
4910 4905 return (IWH_FAIL);
4911 4906 }
4912 4907
4913 4908 /*
4914 4909 * at this point, hardware may receive beacons :)
4915 4910 */
4916 4911 mutex_exit(&sc->sc_glock);
4917 4912 return (IWH_SUCCESS);
4918 4913 }
4919 4914
4920 4915 /*
4921 4916 * stop or disable NIC
4922 4917 */
4923 4918 static void
4924 4919 iwh_stop(iwh_sc_t *sc)
4925 4920 {
4926 4921 uint32_t tmp;
4927 4922 int i;
4928 4923
4929 4924 /*
4930 4925 * by pass if it's quiesced
4931 4926 */
4932 4927 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
4933 4928 mutex_enter(&sc->sc_glock);
4934 4929 }
4935 4930
4936 4931 IWH_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4937 4932 /*
4938 4933 * disable interrupts
4939 4934 */
4940 4935 IWH_WRITE(sc, CSR_INT_MASK, 0);
4941 4936 IWH_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
4942 4937 IWH_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
4943 4938
4944 4939 /*
4945 4940 * reset all Tx rings
4946 4941 */
4947 4942 for (i = 0; i < IWH_NUM_QUEUES; i++) {
4948 4943 iwh_reset_tx_ring(sc, &sc->sc_txq[i]);
4949 4944 }
4950 4945
4951 4946 /*
4952 4947 * reset Rx ring
4953 4948 */
4954 4949 iwh_reset_rx_ring(sc);
4955 4950
4956 4951 iwh_mac_access_enter(sc);
4957 4952 iwh_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4958 4953 iwh_mac_access_exit(sc);
4959 4954
4960 4955 DELAY(5);
4961 4956
4962 4957 iwh_stop_master(sc);
4963 4958
4964 4959 mutex_enter(&sc->sc_mt_lock);
4965 4960 sc->sc_tx_timer = 0;
4966 4961 mutex_exit(&sc->sc_mt_lock);
4967 4962
4968 4963 tmp = IWH_READ(sc, CSR_RESET);
4969 4964 IWH_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);
4970 4965
4971 4966 /*
4972 4967 * by pass if it's quiesced
4973 4968 */
4974 4969 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
4975 4970 mutex_exit(&sc->sc_glock);
4976 4971 }
4977 4972 }
4978 4973
4979 4974 /*
4980 4975 * Naive implementation of the Adaptive Multi Rate Retry algorithm:
4981 4976 * "IEEE 802.11 Rate Adaptation: A Practical Approach"
4982 4977 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti
4983 4978 * INRIA Sophia - Projet Planete
4984 4979 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html
4985 4980 */
4986 4981 #define is_success(amrr) \
4987 4982 ((amrr)->retrycnt < (amrr)->txcnt / 10)
4988 4983 #define is_failure(amrr) \
4989 4984 ((amrr)->retrycnt > (amrr)->txcnt / 3)
4990 4985 #define is_enough(amrr) \
4991 4986 ((amrr)->txcnt > 200)
4992 4987 #define not_very_few(amrr) \
4993 4988 ((amrr)->txcnt > 40)
4994 4989 #define is_min_rate(in) \
4995 4990 (0 == (in)->in_txrate)
4996 4991 #define is_max_rate(in) \
4997 4992 ((in)->in_rates.ir_nrates - 1 == (in)->in_txrate)
4998 4993 #define increase_rate(in) \
4999 4994 ((in)->in_txrate++)
5000 4995 #define decrease_rate(in) \
5001 4996 ((in)->in_txrate--)
5002 4997 #define reset_cnt(amrr) \
5003 4998 { (amrr)->txcnt = (amrr)->retrycnt = 0; }
5004 4999
5005 5000 #define IWH_AMRR_MIN_SUCCESS_THRESHOLD 1
5006 5001 #define IWH_AMRR_MAX_SUCCESS_THRESHOLD 15
5007 5002
5008 5003 static void
5009 5004 iwh_amrr_init(iwh_amrr_t *amrr)
5010 5005 {
5011 5006 amrr->success = 0;
5012 5007 amrr->recovery = 0;
5013 5008 amrr->txcnt = amrr->retrycnt = 0;
5014 5009 amrr->success_threshold = IWH_AMRR_MIN_SUCCESS_THRESHOLD;
5015 5010 amrr->ht_mcs_idx = 0; /* 6Mbps */
5016 5011 }
5017 5012
5018 5013 static void
5019 5014 iwh_amrr_timeout(iwh_sc_t *sc)
5020 5015 {
5021 5016 ieee80211com_t *ic = &sc->sc_ic;
5022 5017
5023 5018 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_amrr_timeout(): "
5024 5019 "enter\n"));
5025 5020
5026 5021 if (IEEE80211_M_STA == ic->ic_opmode) {
5027 5022 iwh_amrr_ratectl(NULL, ic->ic_bss);
5028 5023 } else {
5029 5024 ieee80211_iterate_nodes(&ic->ic_sta, iwh_amrr_ratectl, NULL);
5030 5025 }
5031 5026
5032 5027 sc->sc_clk = ddi_get_lbolt();
5033 5028 }
5034 5029
5035 5030 static int
5036 5031 iwh_is_max_rate(ieee80211_node_t *in)
5037 5032 {
5038 5033 int i;
5039 5034 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5040 5035 uint8_t r = (uint8_t)amrr->ht_mcs_idx;
5041 5036 ieee80211com_t *ic = in->in_ic;
5042 5037 iwh_sc_t *sc = (iwh_sc_t *)ic;
5043 5038
5044 5039 if (in->in_flags & IEEE80211_NODE_HT) {
5045 5040 for (i = in->in_htrates.rs_nrates - 1; i >= 0; i--) {
5046 5041 r = in->in_htrates.rs_rates[i] &
5047 5042 IEEE80211_RATE_VAL;
5048 5043 if (sc->sc_ht_conf.tx_support_mcs[r/8] &
5049 5044 (1 << (r%8))) {
5050 5045 break;
5051 5046 }
5052 5047 }
5053 5048
5054 5049 return (r == (uint8_t)amrr->ht_mcs_idx);
5055 5050 } else {
5056 5051 return (is_max_rate(in));
5057 5052 }
5058 5053 }
5059 5054
5060 5055 static int
5061 5056 iwh_is_min_rate(ieee80211_node_t *in)
5062 5057 {
5063 5058 int i;
5064 5059 uint8_t r = 0;
5065 5060 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5066 5061 ieee80211com_t *ic = in->in_ic;
5067 5062 iwh_sc_t *sc = (iwh_sc_t *)ic;
5068 5063
5069 5064 if (in->in_flags & IEEE80211_NODE_HT) {
5070 5065 for (i = 0; i < in->in_htrates.rs_nrates; i++) {
5071 5066 r = in->in_htrates.rs_rates[i] &
5072 5067 IEEE80211_RATE_VAL;
5073 5068 if (sc->sc_ht_conf.tx_support_mcs[r/8] &
5074 5069 (1 << (r%8))) {
5075 5070 break;
5076 5071 }
5077 5072 }
5078 5073
5079 5074 return (r == (uint8_t)amrr->ht_mcs_idx);
5080 5075 } else {
5081 5076 return (is_min_rate(in));
5082 5077 }
5083 5078 }
5084 5079
5085 5080 static void
5086 5081 iwh_increase_rate(ieee80211_node_t *in)
5087 5082 {
5088 5083 int i;
5089 5084 uint8_t r;
5090 5085 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5091 5086 ieee80211com_t *ic = in->in_ic;
5092 5087 iwh_sc_t *sc = (iwh_sc_t *)ic;
5093 5088
5094 5089 if (in->in_flags & IEEE80211_NODE_HT) {
5095 5090 again:
5096 5091 amrr->ht_mcs_idx++;
5097 5092
5098 5093 for (i = 0; i < in->in_htrates.rs_nrates; i++) {
5099 5094 r = in->in_htrates.rs_rates[i] &
5100 5095 IEEE80211_RATE_VAL;
5101 5096 if ((r == (uint8_t)amrr->ht_mcs_idx) &&
5102 5097 (sc->sc_ht_conf.tx_support_mcs[r/8] &
5103 5098 (1 << (r%8)))) {
5104 5099 break;
5105 5100 }
5106 5101 }
5107 5102
5108 5103 if (i >= in->in_htrates.rs_nrates) {
5109 5104 goto again;
5110 5105 }
5111 5106 } else {
5112 5107 increase_rate(in);
5113 5108 }
5114 5109 }
5115 5110
5116 5111 static void
5117 5112 iwh_decrease_rate(ieee80211_node_t *in)
5118 5113 {
5119 5114 int i;
5120 5115 uint8_t r;
5121 5116 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5122 5117 ieee80211com_t *ic = in->in_ic;
5123 5118 iwh_sc_t *sc = (iwh_sc_t *)ic;
5124 5119
5125 5120 if (in->in_flags & IEEE80211_NODE_HT) {
5126 5121 again:
5127 5122 amrr->ht_mcs_idx--;
5128 5123
5129 5124 for (i = 0; i < in->in_htrates.rs_nrates; i++) {
5130 5125 r = in->in_htrates.rs_rates[i] &
5131 5126 IEEE80211_RATE_VAL;
5132 5127 if ((r == (uint8_t)amrr->ht_mcs_idx) &&
5133 5128 (sc->sc_ht_conf.tx_support_mcs[r/8] &
5134 5129 (1 << (r%8)))) {
5135 5130 break;
5136 5131 }
5137 5132 }
5138 5133
5139 5134 if (i >= in->in_htrates.rs_nrates) {
5140 5135 goto again;
5141 5136 }
5142 5137 } else {
5143 5138 decrease_rate(in);
5144 5139 }
5145 5140 }
5146 5141
5147 5142 /* ARGSUSED */
5148 5143 static void
5149 5144 iwh_amrr_ratectl(void *arg, ieee80211_node_t *in)
5150 5145 {
5151 5146 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5152 5147 int need_change = 0;
5153 5148
5154 5149 if (is_success(amrr) && is_enough(amrr)) {
5155 5150 amrr->success++;
5156 5151 if (amrr->success >= amrr->success_threshold &&
5157 5152 !iwh_is_max_rate(in)) {
5158 5153 amrr->recovery = 1;
5159 5154 amrr->success = 0;
5160 5155 iwh_increase_rate(in);
5161 5156 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_amrr_ratectl(): "
5162 5157 "AMRR increasing rate %d "
5163 5158 "(txcnt=%d retrycnt=%d), mcs_idx=%d\n",
5164 5159 in->in_txrate, amrr->txcnt,
5165 5160 amrr->retrycnt, amrr->ht_mcs_idx));
5166 5161 need_change = 1;
5167 5162 } else {
5168 5163 amrr->recovery = 0;
5169 5164 }
5170 5165 } else if (not_very_few(amrr) && is_failure(amrr)) {
5171 5166 amrr->success = 0;
5172 5167 if (!iwh_is_min_rate(in)) {
5173 5168 if (amrr->recovery) {
5174 5169 amrr->success_threshold++;
5175 5170 if (amrr->success_threshold >
5176 5171 IWH_AMRR_MAX_SUCCESS_THRESHOLD) {
5177 5172 amrr->success_threshold =
5178 5173 IWH_AMRR_MAX_SUCCESS_THRESHOLD;
5179 5174 }
5180 5175 } else {
5181 5176 amrr->success_threshold =
5182 5177 IWH_AMRR_MIN_SUCCESS_THRESHOLD;
5183 5178 }
5184 5179 iwh_decrease_rate(in);
5185 5180 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_amrr_ratectl(): "
5186 5181 "AMRR decreasing rate %d "
5187 5182 "(txcnt=%d retrycnt=%d), mcs_idx=%d\n",
5188 5183 in->in_txrate, amrr->txcnt,
5189 5184 amrr->retrycnt, amrr->ht_mcs_idx));
5190 5185 need_change = 1;
5191 5186 }
5192 5187 amrr->recovery = 0; /* paper is incorrect */
5193 5188 }
5194 5189
5195 5190 if (is_enough(amrr) || need_change) {
5196 5191 reset_cnt(amrr);
5197 5192 }
5198 5193 }
5199 5194
5200 5195 /*
5201 5196 * translate indirect address in eeprom to direct address
5202 5197 * in eeprom and return address of entry whos indirect address
5203 5198 * is indi_addr
5204 5199 */
5205 5200 static uint8_t *
5206 5201 iwh_eep_addr_trans(iwh_sc_t *sc, uint32_t indi_addr)
5207 5202 {
5208 5203 uint32_t di_addr;
5209 5204 uint16_t temp;
5210 5205
5211 5206 if (!(indi_addr & INDIRECT_ADDRESS)) {
5212 5207 di_addr = indi_addr;
5213 5208 return (&sc->sc_eep_map[di_addr]);
5214 5209 }
5215 5210
5216 5211 switch (indi_addr & INDIRECT_TYPE_MSK) {
5217 5212 case INDIRECT_GENERAL:
5218 5213 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_GENERAL);
5219 5214 break;
5220 5215
5221 5216 case INDIRECT_HOST:
5222 5217 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_HOST);
5223 5218 break;
5224 5219
5225 5220 case INDIRECT_REGULATORY:
5226 5221 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY);
5227 5222 break;
5228 5223
5229 5224 case INDIRECT_CALIBRATION:
5230 5225 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION);
5231 5226 break;
5232 5227
5233 5228 case INDIRECT_PROCESS_ADJST:
5234 5229 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST);
5235 5230 break;
5236 5231
5237 5232 case INDIRECT_OTHERS:
5238 5233 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_OTHERS);
5239 5234 break;
5240 5235
5241 5236 default:
5242 5237 temp = 0;
5243 5238 cmn_err(CE_WARN, "iwh_eep_addr_trans(): "
5244 5239 "incorrect indirect eeprom address.\n");
5245 5240 break;
5246 5241 }
5247 5242
5248 5243 di_addr = (indi_addr & ADDRESS_MSK) + (temp << 1);
5249 5244
5250 5245 return (&sc->sc_eep_map[di_addr]);
5251 5246 }
5252 5247
5253 5248 /*
5254 5249 * loade a section of ucode into NIC
5255 5250 */
5256 5251 static int
5257 5252 iwh_put_seg_fw(iwh_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len)
5258 5253 {
5259 5254
5260 5255 iwh_mac_access_enter(sc);
5261 5256
5262 5257 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(IWH_FH_SRVC_CHNL),
5263 5258 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
5264 5259
5265 5260 IWH_WRITE(sc, IWH_FH_SRVC_CHNL_SRAM_ADDR_REG(IWH_FH_SRVC_CHNL), addr_d);
5266 5261
5267 5262 IWH_WRITE(sc, IWH_FH_TFDIB_CTRL0_REG(IWH_FH_SRVC_CHNL),
5268 5263 (addr_s & FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK));
5269 5264
5270 5265 IWH_WRITE(sc, IWH_FH_TFDIB_CTRL1_REG(IWH_FH_SRVC_CHNL), len);
5271 5266
5272 5267 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_BUF_STS_REG(IWH_FH_SRVC_CHNL),
5273 5268 (1 << IWH_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
5274 5269 (1 << IWH_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
5275 5270 IWH_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
5276 5271
5277 5272 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(IWH_FH_SRVC_CHNL),
5278 5273 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5279 5274 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
5280 5275 IWH_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
5281 5276
5282 5277 iwh_mac_access_exit(sc);
5283 5278
5284 5279 return (IWH_SUCCESS);
5285 5280 }
5286 5281
5287 5282 /*
5288 5283 * necessary setting during alive notification
5289 5284 */
5290 5285 static int
5291 5286 iwh_alive_common(iwh_sc_t *sc)
5292 5287 {
5293 5288 uint32_t base;
5294 5289 uint32_t i;
5295 5290 iwh_wimax_coex_cmd_t w_cmd;
5296 5291 iwh_calibration_crystal_cmd_t c_cmd;
5297 5292 uint32_t rv = IWH_FAIL;
5298 5293
5299 5294 /*
5300 5295 * initialize SCD related registers to make TX work.
5301 5296 */
5302 5297 iwh_mac_access_enter(sc);
5303 5298
5304 5299 /*
5305 5300 * read sram address of data base.
5306 5301 */
5307 5302 sc->sc_scd_base = iwh_reg_read(sc, IWH_SCD_SRAM_BASE_ADDR);
5308 5303
5309 5304 for (base = sc->sc_scd_base + IWH_SCD_CONTEXT_DATA_OFFSET;
5310 5305 base < sc->sc_scd_base + IWH_SCD_TX_STTS_BITMAP_OFFSET;
5311 5306 base += 4) {
5312 5307 iwh_mem_write(sc, base, 0);
5313 5308 }
5314 5309
5315 5310 for (; base < sc->sc_scd_base + IWH_SCD_TRANSLATE_TBL_OFFSET;
5316 5311 base += 4) {
5317 5312 iwh_mem_write(sc, base, 0);
5318 5313 }
5319 5314
5320 5315 for (i = 0; i < sizeof (uint16_t) * IWH_NUM_QUEUES; i += 4) {
5321 5316 iwh_mem_write(sc, base + i, 0);
5322 5317 }
5323 5318
5324 5319 iwh_reg_write(sc, IWH_SCD_DRAM_BASE_ADDR,
5325 5320 sc->sc_dma_sh.cookie.dmac_address >> 10);
5326 5321
5327 5322 iwh_reg_write(sc, IWH_SCD_QUEUECHAIN_SEL,
5328 5323 IWH_SCD_QUEUECHAIN_SEL_ALL(IWH_NUM_QUEUES));
5329 5324
5330 5325 iwh_reg_write(sc, IWH_SCD_AGGR_SEL, 0);
5331 5326
5332 5327 for (i = 0; i < IWH_NUM_QUEUES; i++) {
5333 5328 iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(i), 0);
5334 5329 IWH_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8));
5335 5330 iwh_mem_write(sc, sc->sc_scd_base +
5336 5331 IWH_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
5337 5332 iwh_mem_write(sc, sc->sc_scd_base +
5338 5333 IWH_SCD_CONTEXT_QUEUE_OFFSET(i) +
5339 5334 sizeof (uint32_t),
5340 5335 ((SCD_WIN_SIZE << IWH_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
5341 5336 IWH_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
5342 5337 ((SCD_FRAME_LIMIT <<
5343 5338 IWH_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5344 5339 IWH_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
5345 5340 }
5346 5341
5347 5342 iwh_reg_write(sc, IWH_SCD_INTERRUPT_MASK, (1 << IWH_NUM_QUEUES) - 1);
5348 5343
5349 5344 iwh_reg_write(sc, (IWH_SCD_BASE + 0x10),
5350 5345 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
5351 5346
5352 5347 IWH_WRITE(sc, HBUS_TARG_WRPTR, (IWH_CMD_QUEUE_NUM << 8));
5353 5348 iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(IWH_CMD_QUEUE_NUM), 0);
5354 5349
5355 5350 /*
5356 5351 * queue 0-7 map to FIFO 0-7 and
5357 5352 * all queues work under FIFO mode(none-scheduler_ack)
5358 5353 */
5359 5354 for (i = 0; i < 4; i++) {
5360 5355 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),
5361 5356 (1 << IWH_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5362 5357 ((3-i) << IWH_SCD_QUEUE_STTS_REG_POS_TXF) |
5363 5358 (1 << IWH_SCD_QUEUE_STTS_REG_POS_WSL) |
5364 5359 IWH_SCD_QUEUE_STTS_REG_MSK);
5365 5360 }
5366 5361
5367 5362 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(IWH_CMD_QUEUE_NUM),
5368 5363 (1 << IWH_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5369 5364 (IWH_CMD_FIFO_NUM << IWH_SCD_QUEUE_STTS_REG_POS_TXF) |
5370 5365 (1 << IWH_SCD_QUEUE_STTS_REG_POS_WSL) |
5371 5366 IWH_SCD_QUEUE_STTS_REG_MSK);
5372 5367
5373 5368 for (i = 5; i < 7; i++) {
5374 5369 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),
5375 5370 (1 << IWH_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5376 5371 (i << IWH_SCD_QUEUE_STTS_REG_POS_TXF) |
5377 5372 (1 << IWH_SCD_QUEUE_STTS_REG_POS_WSL) |
5378 5373 IWH_SCD_QUEUE_STTS_REG_MSK);
5379 5374 }
5380 5375
5381 5376 iwh_mac_access_exit(sc);
5382 5377
5383 5378 (void) memset(&w_cmd, 0, sizeof (w_cmd));
5384 5379
5385 5380 rv = iwh_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1);
5386 5381 if (rv != IWH_SUCCESS) {
5387 5382 cmn_err(CE_WARN, "iwh_alive_common(): "
5388 5383 "failed to send wimax coexist command.\n");
5389 5384 return (rv);
5390 5385 }
5391 5386
5392 5387 if ((sc->sc_dev_id != 0x423c) &&
5393 5388 (sc->sc_dev_id != 0x423d)) {
5394 5389 (void) memset(&c_cmd, 0, sizeof (c_cmd));
5395 5390
5396 5391 c_cmd.opCode = PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
5397 5392 c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]);
5398 5393 c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]);
5399 5394
5400 5395 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
5401 5396 &c_cmd, sizeof (c_cmd), 1);
5402 5397 if (rv != IWH_SUCCESS) {
5403 5398 cmn_err(CE_WARN, "iwh_alive_common(): "
5404 5399 "failed to send crystal"
5405 5400 "frq calibration command.\n");
5406 5401 return (rv);
5407 5402 }
5408 5403
5409 5404 /*
5410 5405 * make sure crystal frequency calibration ready
5411 5406 * before next operations.
5412 5407 */
5413 5408 DELAY(1000);
5414 5409 }
5415 5410
5416 5411 return (IWH_SUCCESS);
5417 5412 }
5418 5413
5419 5414 /*
5420 5415 * save results of calibration from ucode
5421 5416 */
5422 5417 static void
5423 5418 iwh_save_calib_result(iwh_sc_t *sc, iwh_rx_desc_t *desc)
5424 5419 {
5425 5420 struct iwh_calib_results *res_p = &sc->sc_calib_results;
5426 5421 struct iwh_calib_hdr *calib_hdr = (struct iwh_calib_hdr *)(desc + 1);
5427 5422 int len = LE_32(desc->len);
5428 5423
5429 5424 /*
5430 5425 * ensure the size of buffer is not too big
5431 5426 */
5432 5427 len = (len & FH_RSCSR_FRAME_SIZE_MASK) - 4;
5433 5428
5434 5429 switch (calib_hdr->op_code) {
5435 5430 case PHY_CALIBRATE_LO_CMD:
5436 5431 if (NULL == res_p->lo_res) {
5437 5432 res_p->lo_res = kmem_alloc(len, KM_NOSLEEP);
5438 5433 }
5439 5434
5440 5435 if (NULL == res_p->lo_res) {
5441 5436 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5442 5437 "failed to allocate memory.\n");
5443 5438 return;
5444 5439 }
5445 5440
5446 5441 res_p->lo_res_len = len;
5447 5442 bcopy(calib_hdr, res_p->lo_res, len);
5448 5443 break;
5449 5444
5450 5445 case PHY_CALIBRATE_TX_IQ_CMD:
5451 5446 if (NULL == res_p->tx_iq_res) {
5452 5447 res_p->tx_iq_res = kmem_alloc(len, KM_NOSLEEP);
5453 5448 }
5454 5449
5455 5450 if (NULL == res_p->tx_iq_res) {
5456 5451 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5457 5452 "failed to allocate memory.\n");
5458 5453 return;
5459 5454 }
5460 5455
5461 5456 res_p->tx_iq_res_len = len;
5462 5457 bcopy(calib_hdr, res_p->tx_iq_res, len);
5463 5458 break;
5464 5459
5465 5460 case PHY_CALIBRATE_TX_IQ_PERD_CMD:
5466 5461 if (NULL == res_p->tx_iq_perd_res) {
5467 5462 res_p->tx_iq_perd_res = kmem_alloc(len, KM_NOSLEEP);
5468 5463 }
5469 5464
5470 5465 if (NULL == res_p->tx_iq_perd_res) {
5471 5466 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5472 5467 "failed to allocate memory.\n");
5473 5468 return;
5474 5469 }
5475 5470
5476 5471 res_p->tx_iq_perd_res_len = len;
5477 5472 bcopy(calib_hdr, res_p->tx_iq_perd_res, len);
5478 5473 break;
5479 5474
5480 5475 case PHY_CALIBRATE_DC_CMD:
5481 5476 if (NULL == res_p->dc_res) {
5482 5477 res_p->dc_res = kmem_alloc(len, KM_NOSLEEP);
5483 5478 }
5484 5479
5485 5480 if (NULL == res_p->dc_res) {
5486 5481 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5487 5482 "failed to allocate memory.\n");
5488 5483 return;
5489 5484 }
5490 5485
5491 5486 res_p->dc_res_len = len;
5492 5487 bcopy(calib_hdr, res_p->dc_res, len);
5493 5488 break;
5494 5489
5495 5490 case PHY_CALIBRATE_BASE_BAND_CMD:
5496 5491 if (NULL == res_p->base_band_res) {
5497 5492 res_p->base_band_res = kmem_alloc(len, KM_NOSLEEP);
5498 5493 }
5499 5494
5500 5495 if (NULL == res_p->base_band_res) {
5501 5496 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5502 5497 "failed to allocate memory.\n");
5503 5498 return;
5504 5499 }
5505 5500
5506 5501 res_p->base_band_res_len = len;
5507 5502 bcopy(calib_hdr, res_p->base_band_res, len);
5508 5503 break;
5509 5504
5510 5505 default:
5511 5506 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5512 5507 "incorrect calibration type(%d).\n", calib_hdr->op_code);
5513 5508 break;
5514 5509 }
5515 5510
5516 5511 }
5517 5512
5518 5513 /*
5519 5514 * configure TX pwoer table
5520 5515 */
5521 5516 static int
5522 5517 iwh_tx_power_table(iwh_sc_t *sc, int async)
5523 5518 {
5524 5519 iwh_tx_power_table_cmd_t txpower;
5525 5520 int i, err = IWH_FAIL;
5526 5521
5527 5522 (void) memset(&txpower, 0, sizeof (txpower));
5528 5523
5529 5524 txpower.band = 1; /* for 2.4G */
5530 5525 txpower.channel = (uint8_t)LE_16(sc->sc_config.chan);
5531 5526 txpower.pa_measurements = 1;
5532 5527 txpower.max_mcs = 23;
5533 5528
5534 5529 for (i = 0; i < 24; i++) {
5535 5530 txpower.db.ht_ofdm_power[i].s.radio_tx_gain[0] = 0x16;
5536 5531 txpower.db.ht_ofdm_power[i].s.radio_tx_gain[1] = 0x16;
5537 5532 txpower.db.ht_ofdm_power[i].s.radio_tx_gain[2] = 0x16;
5538 5533 txpower.db.ht_ofdm_power[i].s.dsp_predis_atten[0] = 0x6E;
5539 5534 txpower.db.ht_ofdm_power[i].s.dsp_predis_atten[1] = 0x6E;
5540 5535 txpower.db.ht_ofdm_power[i].s.dsp_predis_atten[2] = 0x6E;
5541 5536 }
5542 5537
5543 5538 for (i = 0; i < 2; i++) {
5544 5539 txpower.db.cck_power[i].s.radio_tx_gain[0] = 0x16;
5545 5540 txpower.db.cck_power[i].s.radio_tx_gain[1] = 0x16;
5546 5541 txpower.db.cck_power[i].s.radio_tx_gain[2] = 0x16;
5547 5542 txpower.db.cck_power[i].s.dsp_predis_atten[0] = 0x6E;
5548 5543 txpower.db.cck_power[i].s.dsp_predis_atten[1] = 0x6E;
5549 5544 txpower.db.cck_power[i].s.dsp_predis_atten[2] = 0x6E;
5550 5545 }
5551 5546
5552 5547 err = iwh_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &txpower,
5553 5548 sizeof (txpower), async);
5554 5549 if (err != IWH_SUCCESS) {
5555 5550 cmn_err(CE_WARN, "iwh_tx_power_table(): "
5556 5551 "failed to set tx power table.\n");
5557 5552 return (err);
5558 5553 }
5559 5554
5560 5555 return (err);
5561 5556 }
5562 5557
5563 5558 static void
5564 5559 iwh_release_calib_buffer(iwh_sc_t *sc)
5565 5560 {
5566 5561 if (sc->sc_calib_results.lo_res != NULL) {
5567 5562 kmem_free(sc->sc_calib_results.lo_res,
5568 5563 sc->sc_calib_results.lo_res_len);
5569 5564 sc->sc_calib_results.lo_res = NULL;
5570 5565 }
5571 5566
5572 5567 if (sc->sc_calib_results.tx_iq_res != NULL) {
5573 5568 kmem_free(sc->sc_calib_results.tx_iq_res,
5574 5569 sc->sc_calib_results.tx_iq_res_len);
5575 5570 sc->sc_calib_results.tx_iq_res = NULL;
5576 5571 }
5577 5572
5578 5573 if (sc->sc_calib_results.tx_iq_perd_res != NULL) {
5579 5574 kmem_free(sc->sc_calib_results.tx_iq_perd_res,
5580 5575 sc->sc_calib_results.tx_iq_perd_res_len);
5581 5576 sc->sc_calib_results.tx_iq_perd_res = NULL;
5582 5577 }
5583 5578
5584 5579 if (sc->sc_calib_results.dc_res != NULL) {
5585 5580 kmem_free(sc->sc_calib_results.dc_res,
5586 5581 sc->sc_calib_results.dc_res_len);
5587 5582 sc->sc_calib_results.dc_res = NULL;
5588 5583 }
5589 5584
5590 5585 if (sc->sc_calib_results.base_band_res != NULL) {
5591 5586 kmem_free(sc->sc_calib_results.base_band_res,
5592 5587 sc->sc_calib_results.base_band_res_len);
5593 5588 sc->sc_calib_results.base_band_res = NULL;
5594 5589 }
5595 5590 }
5596 5591
5597 5592 /*
5598 5593 * common section of intialization
5599 5594 */
5600 5595 static int
5601 5596 iwh_init_common(iwh_sc_t *sc)
5602 5597 {
5603 5598 int32_t qid;
5604 5599 uint32_t tmp;
5605 5600
5606 5601 if (iwh_reset_hw(sc) != IWH_SUCCESS) {
5607 5602 cmn_err(CE_WARN, "iwh_init_common(): "
5608 5603 "failed to reset hardware\n");
5609 5604 return (IWH_FAIL);
5610 5605 }
5611 5606
5612 5607 (void) iwh_preinit(sc);
5613 5608
5614 5609 tmp = IWH_READ(sc, CSR_GP_CNTRL);
5615 5610 if (!(tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) {
5616 5611 cmn_err(CE_NOTE, "iwh_init_common(): "
5617 5612 "radio transmitter is off\n");
5618 5613 return (IWH_FAIL);
5619 5614 }
5620 5615
5621 5616 /*
5622 5617 * init Rx ring
5623 5618 */
5624 5619 iwh_mac_access_enter(sc);
5625 5620 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
5626 5621
5627 5622 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
5628 5623 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
5629 5624 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8);
5630 5625
5631 5626 IWH_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
5632 5627 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address +
5633 5628 offsetof(struct iwh_shared, val0)) >> 4));
5634 5629
5635 5630 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
5636 5631 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
5637 5632 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
5638 5633 IWH_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K |
5639 5634 (RX_QUEUE_SIZE_LOG <<
5640 5635 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
5641 5636 iwh_mac_access_exit(sc);
5642 5637 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
5643 5638 (RX_QUEUE_SIZE - 1) & ~0x7);
5644 5639
5645 5640 /*
5646 5641 * init Tx rings
5647 5642 */
5648 5643 iwh_mac_access_enter(sc);
5649 5644 iwh_reg_write(sc, IWH_SCD_TXFACT, 0);
5650 5645
5651 5646 /*
5652 5647 * keep warm page
5653 5648 */
5654 5649 IWH_WRITE(sc, IWH_FH_KW_MEM_ADDR_REG,
5655 5650 sc->sc_dma_kw.cookie.dmac_address >> 4);
5656 5651
5657 5652 for (qid = 0; qid < IWH_NUM_QUEUES; qid++) {
5658 5653 IWH_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
5659 5654 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);
5660 5655 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
5661 5656 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5662 5657 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
5663 5658 }
5664 5659
5665 5660 iwh_mac_access_exit(sc);
5666 5661
5667 5662 /*
5668 5663 * clear "radio off" and "disable command" bits
5669 5664 */
5670 5665 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5671 5666 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
5672 5667 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5673 5668
5674 5669 /*
5675 5670 * clear any pending interrupts
5676 5671 */
5677 5672 IWH_WRITE(sc, CSR_INT, 0xffffffff);
5678 5673
5679 5674 /*
5680 5675 * enable interrupts
5681 5676 */
5682 5677 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
5683 5678
5684 5679 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5685 5680 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5686 5681
5687 5682 return (IWH_SUCCESS);
5688 5683 }
5689 5684
5690 5685 static int
5691 5686 iwh_fast_recover(iwh_sc_t *sc)
5692 5687 {
5693 5688 ieee80211com_t *ic = &sc->sc_ic;
5694 5689 int err = IWH_FAIL;
5695 5690
5696 5691 mutex_enter(&sc->sc_glock);
5697 5692
5698 5693 /*
5699 5694 * restore runtime configuration
5700 5695 */
5701 5696 bcopy(&sc->sc_config_save, &sc->sc_config,
5702 5697 sizeof (sc->sc_config));
5703 5698
5704 5699 sc->sc_config.assoc_id = 0;
5705 5700 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
5706 5701
5707 5702 if ((err = iwh_hw_set_before_auth(sc)) != IWH_SUCCESS) {
5708 5703 cmn_err(CE_WARN, "iwh_fast_recover(): "
5709 5704 "could not setup authentication\n");
5710 5705 mutex_exit(&sc->sc_glock);
5711 5706 return (err);
5712 5707 }
5713 5708
5714 5709 bcopy(&sc->sc_config_save, &sc->sc_config,
5715 5710 sizeof (sc->sc_config));
5716 5711
5717 5712 /*
5718 5713 * update adapter's configuration
5719 5714 */
5720 5715 err = iwh_run_state_config(sc);
5721 5716 if (err != IWH_SUCCESS) {
5722 5717 cmn_err(CE_WARN, "iwh_fast_recover(): "
5723 5718 "failed to setup association\n");
5724 5719 mutex_exit(&sc->sc_glock);
5725 5720 return (err);
5726 5721 }
5727 5722
5728 5723 /*
5729 5724 * set LED on
5730 5725 */
5731 5726 iwh_set_led(sc, 2, 0, 1);
5732 5727
5733 5728 mutex_exit(&sc->sc_glock);
5734 5729
5735 5730 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
5736 5731
5737 5732 /*
5738 5733 * start queue
5739 5734 */
5740 5735 IWH_DBG((IWH_DEBUG_FW, "iwh_fast_recover(): "
5741 5736 "resume xmit\n"));
5742 5737 mac_tx_update(ic->ic_mach);
5743 5738
5744 5739 return (IWH_SUCCESS);
5745 5740 }
5746 5741
5747 5742 static int
5748 5743 iwh_run_state_config(iwh_sc_t *sc)
5749 5744 {
5750 5745 struct ieee80211com *ic = &sc->sc_ic;
5751 5746 ieee80211_node_t *in = ic->ic_bss;
5752 5747 uint32_t ht_protec = (uint32_t)(-1);
5753 5748 int err = IWH_FAIL;
5754 5749
5755 5750 /*
5756 5751 * update adapter's configuration
5757 5752 */
5758 5753 sc->sc_config.assoc_id = in->in_associd & 0x3fff;
5759 5754
5760 5755 /*
5761 5756 * short preamble/slot time are
5762 5757 * negotiated when associating
5763 5758 */
5764 5759 sc->sc_config.flags &=
5765 5760 ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
5766 5761 RXON_FLG_SHORT_SLOT_MSK);
5767 5762
5768 5763 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
5769 5764 sc->sc_config.flags |=
5770 5765 LE_32(RXON_FLG_SHORT_SLOT_MSK);
5771 5766 }
5772 5767
5773 5768 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) {
5774 5769 sc->sc_config.flags |=
5775 5770 LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
5776 5771 }
5777 5772
5778 5773 if (in->in_flags & IEEE80211_NODE_HT) {
5779 5774 ht_protec = in->in_htopmode;
5780 5775 if (ht_protec > 3) {
5781 5776 cmn_err(CE_WARN, "iwh_run_state_config(): "
5782 5777 "HT protection mode is not correct.\n");
5783 5778 return (IWH_FAIL);
5784 5779 } else if (NO_HT_PROT == ht_protec) {
5785 5780 ht_protec = sc->sc_ht_conf.ht_protection;
5786 5781 }
5787 5782
5788 5783 sc->sc_config.flags |=
5789 5784 LE_32(ht_protec << RXON_FLG_HT_OPERATING_MODE_POS);
5790 5785 }
5791 5786
5792 5787 /*
5793 5788 * set RX chains/antennas.
5794 5789 */
5795 5790 iwh_config_rxon_chain(sc);
5796 5791
5797 5792 sc->sc_config.filter_flags |=
5798 5793 LE_32(RXON_FILTER_ASSOC_MSK);
5799 5794
5800 5795 if (ic->ic_opmode != IEEE80211_M_STA) {
5801 5796 sc->sc_config.filter_flags |=
5802 5797 LE_32(RXON_FILTER_BCON_AWARE_MSK);
5803 5798 }
5804 5799
5805 5800 IWH_DBG((IWH_DEBUG_80211, "iwh_run_state_config(): "
5806 5801 "config chan %d flags %x"
5807 5802 " filter_flags %x\n",
5808 5803 sc->sc_config.chan, sc->sc_config.flags,
5809 5804 sc->sc_config.filter_flags));
5810 5805
5811 5806 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
5812 5807 sizeof (iwh_rxon_cmd_t), 1);
5813 5808 if (err != IWH_SUCCESS) {
5814 5809 cmn_err(CE_WARN, "iwh_run_state_config(): "
5815 5810 "could not update configuration\n");
5816 5811 return (err);
5817 5812 }
5818 5813
5819 5814 if ((sc->sc_dev_id != 0x423c) &&
5820 5815 (sc->sc_dev_id != 0x423d)) {
5821 5816 /*
5822 5817 * send tx power table command
5823 5818 */
5824 5819 err = iwh_tx_power_table(sc, 1);
5825 5820 if (err != IWH_SUCCESS) {
5826 5821 return (err);
5827 5822 }
5828 5823 }
5829 5824
5830 5825 /*
5831 5826 * Not need to update retry rate table for AP node
5832 5827 */
5833 5828 err = iwh_qosparam_to_hw(sc, 1);
5834 5829 if (err != IWH_SUCCESS) {
5835 5830 return (err);
5836 5831 }
5837 5832
5838 5833 return (err);
5839 5834 }
5840 5835
5841 5836 /*
5842 5837 * This function is only for compatibility with Net80211 module.
5843 5838 * iwh_qosparam_to_hw() is the actual function updating EDCA
5844 5839 * parameters to hardware.
5845 5840 */
5846 5841 /* ARGSUSED */
5847 5842 static int
5848 5843 iwh_wme_update(ieee80211com_t *ic)
5849 5844 {
5850 5845 return (0);
5851 5846 }
5852 5847
5853 5848 static int
5854 5849 iwh_wme_to_qos_ac(int wme_ac)
5855 5850 {
5856 5851 int qos_ac = QOS_AC_INVALID;
5857 5852
5858 5853 if (wme_ac < WME_AC_BE || wme_ac > WME_AC_VO) {
5859 5854 cmn_err(CE_WARN, "iwh_wme_to_qos_ac(): "
5860 5855 "WME AC index is not in suitable range.\n");
5861 5856 return (qos_ac);
5862 5857 }
5863 5858
5864 5859 switch (wme_ac) {
5865 5860 case WME_AC_BE:
5866 5861 qos_ac = QOS_AC_BK;
5867 5862 break;
5868 5863 case WME_AC_BK:
5869 5864 qos_ac = QOS_AC_BE;
5870 5865 break;
5871 5866 case WME_AC_VI:
5872 5867 qos_ac = QOS_AC_VI;
5873 5868 break;
5874 5869 case WME_AC_VO:
5875 5870 qos_ac = QOS_AC_VO;
5876 5871 break;
5877 5872 }
5878 5873
5879 5874 return (qos_ac);
5880 5875 }
5881 5876
5882 5877 static uint16_t
5883 5878 iwh_cw_e_to_cw(uint8_t cw_e)
5884 5879 {
5885 5880 uint16_t cw = 1;
5886 5881
5887 5882 while (cw_e > 0) {
5888 5883 cw <<= 1;
5889 5884 cw_e--;
5890 5885 }
5891 5886
5892 5887 cw -= 1;
5893 5888 return (cw);
5894 5889 }
5895 5890
5896 5891 static int
5897 5892 iwh_wmeparam_check(struct wmeParams *wmeparam)
5898 5893 {
5899 5894 int i;
5900 5895
5901 5896 for (i = 0; i < WME_NUM_AC; i++) {
5902 5897
5903 5898 if ((wmeparam[i].wmep_logcwmax > QOS_CW_RANGE_MAX) ||
5904 5899 (wmeparam[i].wmep_logcwmin >= wmeparam[i].wmep_logcwmax)) {
5905 5900 cmn_err(CE_WARN, "iwh_wmeparam_check(): "
5906 5901 "Contention window is not in suitable range.\n");
5907 5902 return (IWH_FAIL);
5908 5903 }
5909 5904
5910 5905 if ((wmeparam[i].wmep_aifsn < QOS_AIFSN_MIN) ||
5911 5906 (wmeparam[i].wmep_aifsn > QOS_AIFSN_MAX)) {
5912 5907 cmn_err(CE_WARN, "iwh_wmeparam_check(): "
5913 5908 "Arbitration interframe space number"
5914 5909 "is not in suitable range.\n");
5915 5910 return (IWH_FAIL);
5916 5911 }
5917 5912 }
5918 5913
5919 5914 return (IWH_SUCCESS);
5920 5915 }
5921 5916
5922 5917 /*
5923 5918 * This function updates EDCA parameters into hardware.
5924 5919 * FIFO0-background, FIFO1-best effort, FIFO2-viedo, FIFO3-voice.
5925 5920 */
5926 5921 static int
5927 5922 iwh_qosparam_to_hw(iwh_sc_t *sc, int async)
5928 5923 {
5929 5924 ieee80211com_t *ic = &sc->sc_ic;
5930 5925 ieee80211_node_t *in = ic->ic_bss;
5931 5926 struct wmeParams *wmeparam;
5932 5927 iwh_qos_param_cmd_t qosparam_cmd;
5933 5928 int i, j;
5934 5929 int err = IWH_FAIL;
5935 5930
5936 5931 if ((in->in_flags & IEEE80211_NODE_QOS) &&
5937 5932 (IEEE80211_M_STA == ic->ic_opmode)) {
5938 5933 wmeparam = ic->ic_wme.wme_chanParams.cap_wmeParams;
5939 5934 } else {
5940 5935 return (IWH_SUCCESS);
5941 5936 }
5942 5937
5943 5938 (void) memset(&qosparam_cmd, 0, sizeof (qosparam_cmd));
5944 5939
5945 5940 err = iwh_wmeparam_check(wmeparam);
5946 5941 if (err != IWH_SUCCESS) {
5947 5942 return (err);
5948 5943 }
5949 5944
5950 5945 if (in->in_flags & IEEE80211_NODE_QOS) {
5951 5946 qosparam_cmd.flags |= QOS_PARAM_FLG_UPDATE_EDCA;
5952 5947 }
5953 5948
5954 5949 if (in->in_flags & (IEEE80211_NODE_QOS | IEEE80211_NODE_HT)) {
5955 5950 qosparam_cmd.flags |= QOS_PARAM_FLG_TGN;
5956 5951 }
5957 5952
5958 5953 for (i = 0; i < WME_NUM_AC; i++) {
5959 5954
5960 5955 j = iwh_wme_to_qos_ac(i);
5961 5956 if (j < QOS_AC_BK || j > QOS_AC_VO) {
5962 5957 return (IWH_FAIL);
5963 5958 }
5964 5959
5965 5960 qosparam_cmd.ac[j].cw_min =
5966 5961 iwh_cw_e_to_cw(wmeparam[i].wmep_logcwmin);
5967 5962 qosparam_cmd.ac[j].cw_max =
5968 5963 iwh_cw_e_to_cw(wmeparam[i].wmep_logcwmax);
5969 5964 qosparam_cmd.ac[j].aifsn =
5970 5965 wmeparam[i].wmep_aifsn;
5971 5966 qosparam_cmd.ac[j].txop =
5972 5967 (uint16_t)(wmeparam[i].wmep_txopLimit * 32);
5973 5968 }
5974 5969
5975 5970 err = iwh_cmd(sc, REPLY_QOS_PARAM, &qosparam_cmd,
5976 5971 sizeof (qosparam_cmd), async);
5977 5972 if (err != IWH_SUCCESS) {
5978 5973 cmn_err(CE_WARN, "iwh_qosparam_to_hw(): "
5979 5974 "failed to update QoS parameters into hardware.\n");
5980 5975 return (err);
5981 5976 }
5982 5977
5983 5978 #ifdef DEBUG
5984 5979 IWH_DBG((IWH_DEBUG_QOS, "iwh_qosparam_to_hw(): "
5985 5980 "EDCA parameters are as follows:\n"));
5986 5981
5987 5982 IWH_DBG((IWH_DEBUG_QOS, "BK parameters are: "
5988 5983 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
5989 5984 qosparam_cmd.ac[0].cw_min, qosparam_cmd.ac[0].cw_max,
5990 5985 qosparam_cmd.ac[0].aifsn, qosparam_cmd.ac[0].txop));
5991 5986
5992 5987 IWH_DBG((IWH_DEBUG_QOS, "BE parameters are: "
5993 5988 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
5994 5989 qosparam_cmd.ac[1].cw_min, qosparam_cmd.ac[1].cw_max,
5995 5990 qosparam_cmd.ac[1].aifsn, qosparam_cmd.ac[1].txop));
5996 5991
5997 5992 IWH_DBG((IWH_DEBUG_QOS, "VI parameters are: "
5998 5993 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
5999 5994 qosparam_cmd.ac[2].cw_min, qosparam_cmd.ac[2].cw_max,
6000 5995 qosparam_cmd.ac[2].aifsn, qosparam_cmd.ac[2].txop));
6001 5996
6002 5997 IWH_DBG((IWH_DEBUG_QOS, "VO parameters are: "
6003 5998 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
6004 5999 qosparam_cmd.ac[3].cw_min, qosparam_cmd.ac[3].cw_max,
6005 6000 qosparam_cmd.ac[3].aifsn, qosparam_cmd.ac[3].txop));
6006 6001 #endif
6007 6002 return (err);
6008 6003 }
6009 6004
6010 6005 static inline int
6011 6006 iwh_wme_tid_qos_ac(int tid)
6012 6007 {
6013 6008 switch (tid) {
6014 6009 case 1:
6015 6010 case 2:
6016 6011 return (QOS_AC_BK);
6017 6012 case 0:
6018 6013 case 3:
6019 6014 return (QOS_AC_BE);
6020 6015 case 4:
6021 6016 case 5:
6022 6017 return (QOS_AC_VI);
6023 6018 case 6:
6024 6019 case 7:
6025 6020 return (QOS_AC_VO);
6026 6021 }
6027 6022
6028 6023 return (QOS_AC_BE);
6029 6024 }
6030 6025
6031 6026 static inline int
6032 6027 iwh_qos_ac_to_txq(int qos_ac)
6033 6028 {
6034 6029 switch (qos_ac) {
6035 6030 case QOS_AC_BK:
6036 6031 return (QOS_AC_BK_TO_TXQ);
6037 6032 case QOS_AC_BE:
6038 6033 return (QOS_AC_BE_TO_TXQ);
6039 6034 case QOS_AC_VI:
6040 6035 return (QOS_AC_VI_TO_TXQ);
6041 6036 case QOS_AC_VO:
6042 6037 return (QOS_AC_VO_TO_TXQ);
6043 6038 }
6044 6039
6045 6040 return (QOS_AC_BE_TO_TXQ);
6046 6041 }
6047 6042
6048 6043 static int
6049 6044 iwh_wme_tid_to_txq(int tid)
6050 6045 {
6051 6046 int queue_n = TXQ_FOR_AC_INVALID;
6052 6047 int qos_ac;
6053 6048
6054 6049 if (tid < WME_TID_MIN ||
6055 6050 tid > WME_TID_MAX) {
6056 6051 cmn_err(CE_WARN, "wme_tid_to_txq(): "
6057 6052 "TID is not in suitable range.\n");
6058 6053 return (queue_n);
6059 6054 }
6060 6055
6061 6056 qos_ac = iwh_wme_tid_qos_ac(tid);
6062 6057 queue_n = iwh_qos_ac_to_txq(qos_ac);
6063 6058
6064 6059 return (queue_n);
6065 6060 }
6066 6061
6067 6062 /*
6068 6063 * This function is used for intializing HT relevant configurations.
6069 6064 */
6070 6065 static void
6071 6066 iwh_init_ht_conf(iwh_sc_t *sc)
6072 6067 {
6073 6068 (void) memset(&sc->sc_ht_conf, 0, sizeof (iwh_ht_conf_t));
6074 6069
6075 6070 if ((0x4235 == sc->sc_dev_id) ||
6076 6071 (0x4236 == sc->sc_dev_id) ||
6077 6072 (0x423a == sc->sc_dev_id)) {
6078 6073 sc->sc_ht_conf.ht_support = 1;
6079 6074
6080 6075 sc->sc_ht_conf.valid_chains = 3;
6081 6076 sc->sc_ht_conf.tx_stream_count = 2;
6082 6077 sc->sc_ht_conf.rx_stream_count = 2;
6083 6078
6084 6079 sc->sc_ht_conf.tx_support_mcs[0] = 0xff;
6085 6080 sc->sc_ht_conf.tx_support_mcs[1] = 0xff;
6086 6081 sc->sc_ht_conf.rx_support_mcs[0] = 0xff;
6087 6082 sc->sc_ht_conf.rx_support_mcs[1] = 0xff;
6088 6083 } else {
6089 6084 sc->sc_ht_conf.ht_support = 1;
6090 6085
6091 6086 sc->sc_ht_conf.valid_chains = 2;
6092 6087 sc->sc_ht_conf.tx_stream_count = 1;
6093 6088 sc->sc_ht_conf.rx_stream_count = 2;
6094 6089
6095 6090 sc->sc_ht_conf.tx_support_mcs[0] = 0xff;
6096 6091 sc->sc_ht_conf.rx_support_mcs[0] = 0xff;
6097 6092 sc->sc_ht_conf.rx_support_mcs[1] = 0xff;
6098 6093 }
6099 6094
6100 6095 if (sc->sc_ht_conf.ht_support) {
6101 6096 sc->sc_ht_conf.cap |= HT_CAP_GRN_FLD;
6102 6097 sc->sc_ht_conf.cap |= HT_CAP_SGI_20;
6103 6098 sc->sc_ht_conf.cap |= HT_CAP_MAX_AMSDU;
6104 6099 /* should disable MIMO */
6105 6100 sc->sc_ht_conf.cap |= HT_CAP_MIMO_PS;
6106 6101
6107 6102 sc->sc_ht_conf.ampdu_p.factor = HT_RX_AMPDU_FACTOR;
6108 6103 sc->sc_ht_conf.ampdu_p.density = HT_MPDU_DENSITY;
6109 6104
6110 6105 sc->sc_ht_conf.ht_protection = HT_PROT_CHAN_NON_HT;
6111 6106 }
6112 6107 }
6113 6108
6114 6109 /*
6115 6110 * This function overwrites default ieee80211_rateset_11n struc.
6116 6111 */
6117 6112 static void
6118 6113 iwh_overwrite_11n_rateset(iwh_sc_t *sc)
6119 6114 {
6120 6115 uint8_t *ht_rs = sc->sc_ht_conf.rx_support_mcs;
6121 6116 int mcs_idx, mcs_count = 0;
6122 6117 int i, j;
6123 6118
6124 6119 for (i = 0; i < HT_RATESET_NUM; i++) {
6125 6120 for (j = 0; j < 8; j++) {
6126 6121 if (ht_rs[i] & (1 << j)) {
6127 6122 mcs_idx = i * 8 + j;
6128 6123 if (mcs_idx >= IEEE80211_HTRATE_MAXSIZE) {
6129 6124 break;
6130 6125 }
6131 6126
6132 6127 ieee80211_rateset_11n.rs_rates[mcs_idx] =
6133 6128 (uint8_t)mcs_idx;
6134 6129 mcs_count++;
6135 6130 }
6136 6131 }
6137 6132 }
6138 6133
6139 6134 ieee80211_rateset_11n.rs_nrates = (uint8_t)mcs_count;
6140 6135
6141 6136 #ifdef DEBUG
6142 6137 IWH_DBG((IWH_DEBUG_HTRATE, "iwh_overwrite_11n_rateset(): "
6143 6138 "HT rates supported by this station is as follows:\n"));
6144 6139
6145 6140 for (i = 0; i < ieee80211_rateset_11n.rs_nrates; i++) {
6146 6141 IWH_DBG((IWH_DEBUG_HTRATE, "Rate %d is %d\n",
6147 6142 i, ieee80211_rateset_11n.rs_rates[i]));
6148 6143 }
6149 6144 #endif
6150 6145 }
6151 6146
6152 6147 /*
6153 6148 * This function overwrites default configurations of
6154 6149 * ieee80211com structure in Net80211 module.
6155 6150 */
6156 6151 static void
6157 6152 iwh_overwrite_ic_default(iwh_sc_t *sc)
6158 6153 {
6159 6154 ieee80211com_t *ic = &sc->sc_ic;
6160 6155
6161 6156 sc->sc_newstate = ic->ic_newstate;
6162 6157 ic->ic_newstate = iwh_newstate;
6163 6158 ic->ic_node_alloc = iwh_node_alloc;
6164 6159 ic->ic_node_free = iwh_node_free;
6165 6160
6166 6161 if (sc->sc_ht_conf.ht_support) {
6167 6162 sc->sc_recv_action = ic->ic_recv_action;
6168 6163 ic->ic_recv_action = iwh_recv_action;
6169 6164 sc->sc_send_action = ic->ic_send_action;
6170 6165 ic->ic_send_action = iwh_send_action;
6171 6166
6172 6167 ic->ic_ampdu_rxmax = sc->sc_ht_conf.ampdu_p.factor;
6173 6168 ic->ic_ampdu_density = sc->sc_ht_conf.ampdu_p.density;
6174 6169 ic->ic_ampdu_limit = ic->ic_ampdu_rxmax;
6175 6170 }
6176 6171 }
6177 6172
6178 6173 /*
6179 6174 * This function sets "RX chain selection" feild
6180 6175 * in RXON command during plumb driver.
6181 6176 */
6182 6177 static void
6183 6178 iwh_config_rxon_chain(iwh_sc_t *sc)
6184 6179 {
6185 6180 ieee80211com_t *ic = &sc->sc_ic;
6186 6181 ieee80211_node_t *in = ic->ic_bss;
6187 6182
6188 6183 if (3 == sc->sc_ht_conf.valid_chains) {
6189 6184 sc->sc_config.rx_chain = LE_16((RXON_RX_CHAIN_A_MSK |
6190 6185 RXON_RX_CHAIN_B_MSK | RXON_RX_CHAIN_C_MSK) <<
6191 6186 RXON_RX_CHAIN_VALID_POS);
6192 6187
6193 6188 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6194 6189 RXON_RX_CHAIN_B_MSK | RXON_RX_CHAIN_C_MSK) <<
6195 6190 RXON_RX_CHAIN_FORCE_SEL_POS);
6196 6191
6197 6192 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6198 6193 RXON_RX_CHAIN_B_MSK | RXON_RX_CHAIN_C_MSK) <<
6199 6194 RXON_RX_CHAIN_FORCE_MIMO_SEL_POS);
6200 6195 } else {
6201 6196 sc->sc_config.rx_chain = LE_16((RXON_RX_CHAIN_A_MSK |
6202 6197 RXON_RX_CHAIN_B_MSK) << RXON_RX_CHAIN_VALID_POS);
6203 6198
6204 6199 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6205 6200 RXON_RX_CHAIN_B_MSK) << RXON_RX_CHAIN_FORCE_SEL_POS);
6206 6201
6207 6202 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6208 6203 RXON_RX_CHAIN_B_MSK) <<
6209 6204 RXON_RX_CHAIN_FORCE_MIMO_SEL_POS);
6210 6205 }
6211 6206
6212 6207 sc->sc_config.rx_chain |= LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK);
6213 6208
6214 6209 if ((in != NULL) &&
6215 6210 (in->in_flags & IEEE80211_NODE_HT) &&
6216 6211 sc->sc_ht_conf.ht_support) {
6217 6212 if (3 == sc->sc_ht_conf.valid_chains) {
6218 6213 sc->sc_config.rx_chain |= LE_16(3 <<
6219 6214 RXON_RX_CHAIN_CNT_POS);
6220 6215 sc->sc_config.rx_chain |= LE_16(3 <<
6221 6216 RXON_RX_CHAIN_MIMO_CNT_POS);
6222 6217 } else {
6223 6218 sc->sc_config.rx_chain |= LE_16(2 <<
6224 6219 RXON_RX_CHAIN_CNT_POS);
6225 6220 sc->sc_config.rx_chain |= LE_16(2 <<
6226 6221 RXON_RX_CHAIN_MIMO_CNT_POS);
6227 6222 }
6228 6223
6229 6224 sc->sc_config.rx_chain |= LE_16(1 <<
6230 6225 RXON_RX_CHAIN_MIMO_FORCE_POS);
6231 6226 }
6232 6227
6233 6228 IWH_DBG((IWH_DEBUG_RXON, "iwh_config_rxon_chain(): "
6234 6229 "rxon->rx_chain = %x\n", sc->sc_config.rx_chain));
6235 6230 }
6236 6231
6237 6232 /*
6238 6233 * This function adds AP station into hardware.
6239 6234 */
6240 6235 static int
6241 6236 iwh_add_ap_sta(iwh_sc_t *sc)
6242 6237 {
6243 6238 ieee80211com_t *ic = &sc->sc_ic;
6244 6239 ieee80211_node_t *in = ic->ic_bss;
6245 6240 iwh_add_sta_t node;
6246 6241 uint32_t ampdu_factor, ampdu_density;
6247 6242 int err = IWH_FAIL;
6248 6243
6249 6244 /*
6250 6245 * Add AP node into hardware.
6251 6246 */
6252 6247 (void) memset(&node, 0, sizeof (node));
6253 6248 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6254 6249 node.mode = STA_MODE_ADD_MSK;
6255 6250 node.sta.sta_id = IWH_AP_ID;
6256 6251
6257 6252 if (sc->sc_ht_conf.ht_support &&
6258 6253 (in->in_htcap_ie != NULL) &&
6259 6254 (in->in_htcap != 0) &&
6260 6255 (in->in_htparam != 0)) {
6261 6256
6262 6257 if (((in->in_htcap & HT_CAP_MIMO_PS) >> 2)
6263 6258 == HT_CAP_MIMO_PS_DYNAMIC) {
6264 6259 node.station_flags |= LE_32(STA_FLG_RTS_MIMO_PROT);
6265 6260 }
6266 6261
6267 6262 ampdu_factor = in->in_htparam & HT_RX_AMPDU_FACTOR_MSK;
6268 6263 node.station_flags |=
6269 6264 LE_32(ampdu_factor << STA_FLG_MAX_AMPDU_POS);
6270 6265
6271 6266 ampdu_density = (in->in_htparam & HT_MPDU_DENSITY_MSK) >>
6272 6267 HT_MPDU_DENSITY_POS;
6273 6268 node.station_flags |=
6274 6269 LE_32(ampdu_density << STA_FLG_AMPDU_DENSITY_POS);
6275 6270
6276 6271 if (in->in_htcap & LE_16(HT_CAP_SUP_WIDTH)) {
6277 6272 node.station_flags |=
6278 6273 LE_32(STA_FLG_FAT_EN);
6279 6274 }
6280 6275 }
6281 6276
6282 6277 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6283 6278 if (err != IWH_SUCCESS) {
6284 6279 cmn_err(CE_WARN, "iwh_add_ap_lq(): "
6285 6280 "failed to add AP node\n");
6286 6281 return (err);
6287 6282 }
6288 6283
6289 6284 return (err);
6290 6285 }
6291 6286
6292 6287 /*
6293 6288 * Each station in the Shirley Peak's internal station table has
6294 6289 * its own table of 16 TX rates and modulation modes for retrying
6295 6290 * TX when an ACK is not received. This function replaces the entire
6296 6291 * table for one station.Station must already be in Shirley Peak's
6297 6292 * station talbe.
6298 6293 */
6299 6294 static int
6300 6295 iwh_ap_lq(iwh_sc_t *sc)
6301 6296 {
6302 6297 ieee80211com_t *ic = &sc->sc_ic;
6303 6298 ieee80211_node_t *in = ic->ic_bss;
6304 6299 iwh_link_quality_cmd_t link_quality;
6305 6300 const struct ieee80211_rateset *rs_sup = NULL;
6306 6301 uint32_t masks = 0, rate;
6307 6302 int i, err = IWH_FAIL;
6308 6303
6309 6304 /*
6310 6305 * TX_LINK_QUALITY cmd
6311 6306 */
6312 6307 (void) memset(&link_quality, 0, sizeof (link_quality));
6313 6308 if (in->in_chan == IEEE80211_CHAN_ANYC) /* skip null node */
6314 6309 return (err);
6315 6310 rs_sup = ieee80211_get_suprates(ic, in->in_chan);
6316 6311
6317 6312 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
6318 6313 if (i < rs_sup->ir_nrates) {
6319 6314 rate = rs_sup->ir_rates[rs_sup->ir_nrates - i] &
6320 6315 IEEE80211_RATE_VAL;
6321 6316 } else {
6322 6317 rate = 2;
6323 6318 }
6324 6319
6325 6320 if (2 == rate || 4 == rate ||
6326 6321 11 == rate || 22 == rate) {
6327 6322 masks |= LE_32(RATE_MCS_CCK_MSK);
6328 6323 }
6329 6324
6330 6325 masks |= LE_32(RATE_MCS_ANT_B_MSK);
6331 6326
6332 6327 link_quality.rate_n_flags[i] =
6333 6328 LE_32(iwh_rate_to_plcp(rate) | masks);
6334 6329 }
6335 6330
6336 6331 link_quality.general_params.single_stream_ant_msk = LINK_QUAL_ANT_B_MSK;
6337 6332 link_quality.general_params.dual_stream_ant_msk = LINK_QUAL_ANT_MSK;
6338 6333 link_quality.agg_params.agg_dis_start_th = 3;
6339 6334 link_quality.agg_params.agg_time_limit = LE_16(4000);
6340 6335 link_quality.sta_id = IWH_AP_ID;
6341 6336 err = iwh_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
6342 6337 sizeof (link_quality), 1);
6343 6338 if (err != IWH_SUCCESS) {
6344 6339 cmn_err(CE_WARN, "iwh_ap_lq(): "
6345 6340 "failed to config link quality table\n");
6346 6341 return (err);
6347 6342 }
6348 6343
6349 6344 #ifdef DEBUG
6350 6345 IWH_DBG((IWH_DEBUG_HWRATE, "iwh_ap_lq(): "
6351 6346 "Rates in HW are as follows:\n"));
6352 6347
6353 6348 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
6354 6349 IWH_DBG((IWH_DEBUG_HWRATE,
6355 6350 "Rate %d in HW is %x\n", i, link_quality.rate_n_flags[i]));
6356 6351 }
6357 6352 #endif
6358 6353
6359 6354 return (err);
6360 6355 }
6361 6356
6362 6357 /*
6363 6358 * When block ACK agreement has been set up between station and AP,
6364 6359 * Net80211 module will call this function to inform hardware about
6365 6360 * informations of this BA agreement.
6366 6361 * When AP wants to delete BA agreement that was originated by it,
6367 6362 * Net80211 modele will call this function to clean up relevant
6368 6363 * information in hardware.
6369 6364 */
6370 6365 static void
6371 6366 iwh_recv_action(struct ieee80211_node *in,
6372 6367 const uint8_t *frm, const uint8_t *efrm)
6373 6368 {
6374 6369 struct ieee80211com *ic;
6375 6370 iwh_sc_t *sc;
6376 6371 const struct ieee80211_action *ia;
6377 6372 uint16_t baparamset, baseqctl;
6378 6373 uint32_t tid, ssn;
6379 6374 iwh_add_sta_t node;
6380 6375 int err = IWH_FAIL;
6381 6376
6382 6377 if ((NULL == in) || (NULL == frm)) {
6383 6378 return;
6384 6379 }
6385 6380
6386 6381 ic = in->in_ic;
6387 6382 if (NULL == ic) {
6388 6383 return;
6389 6384 }
6390 6385
6391 6386 sc = (iwh_sc_t *)ic;
6392 6387
6393 6388 sc->sc_recv_action(in, frm, efrm);
6394 6389
6395 6390 ia = (const struct ieee80211_action *)frm;
6396 6391 if (ia->ia_category != IEEE80211_ACTION_CAT_BA) {
6397 6392 return;
6398 6393 }
6399 6394
6400 6395 switch (ia->ia_action) {
6401 6396 case IEEE80211_ACTION_BA_ADDBA_REQUEST:
6402 6397 baparamset = *(uint16_t *)(frm + 3);
6403 6398 baseqctl = *(uint16_t *)(frm + 7);
6404 6399
6405 6400 tid = MS(baparamset, IEEE80211_BAPS_TID);
6406 6401 ssn = MS(baseqctl, IEEE80211_BASEQ_START);
6407 6402
6408 6403 (void) memset(&node, 0, sizeof (node));
6409 6404 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6410 6405 node.mode = STA_MODE_MODIFY_MSK;
6411 6406 node.sta.sta_id = IWH_AP_ID;
6412 6407
6413 6408 node.station_flags_msk = 0;
6414 6409 node.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
6415 6410 node.add_immediate_ba_tid = (uint8_t)tid;
6416 6411 node.add_immediate_ba_ssn = LE_16(ssn);
6417 6412
6418 6413 mutex_enter(&sc->sc_glock);
6419 6414 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6420 6415 if (err != IWH_SUCCESS) {
6421 6416 cmn_err(CE_WARN, "iwh_recv_action(): "
6422 6417 "failed to setup RX block ACK\n");
6423 6418 mutex_exit(&sc->sc_glock);
6424 6419 return;
6425 6420 }
6426 6421 mutex_exit(&sc->sc_glock);
6427 6422
6428 6423 IWH_DBG((IWH_DEBUG_BA, "iwh_recv_action(): "
6429 6424 "RX block ACK "
6430 6425 "was setup on TID %d and SSN is %d.\n", tid, ssn));
6431 6426
6432 6427 return;
6433 6428
6434 6429 case IEEE80211_ACTION_BA_DELBA:
6435 6430 baparamset = *(uint16_t *)(frm + 2);
6436 6431
6437 6432 if ((baparamset & IEEE80211_DELBAPS_INIT) == 0) {
6438 6433 return;
6439 6434 }
6440 6435
6441 6436 tid = MS(baparamset, IEEE80211_DELBAPS_TID);
6442 6437
6443 6438 (void) memset(&node, 0, sizeof (node));
6444 6439 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6445 6440 node.mode = STA_MODE_MODIFY_MSK;
6446 6441 node.sta.sta_id = IWH_AP_ID;
6447 6442
6448 6443 node.station_flags_msk = 0;
6449 6444 node.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
6450 6445 node.add_immediate_ba_tid = (uint8_t)tid;
6451 6446
6452 6447 mutex_enter(&sc->sc_glock);
6453 6448 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6454 6449 if (err != IWH_SUCCESS) {
6455 6450 cmn_err(CE_WARN, "iwh_recv_action(): "
6456 6451 "failed to delete RX block ACK\n");
6457 6452 mutex_exit(&sc->sc_glock);
6458 6453 return;
6459 6454 }
6460 6455 mutex_exit(&sc->sc_glock);
6461 6456
6462 6457 IWH_DBG((IWH_DEBUG_BA, "iwh_recv_action(): "
6463 6458 "RX block ACK "
6464 6459 "was deleted on TID %d.\n", tid));
6465 6460
6466 6461 return;
6467 6462 }
6468 6463 }
6469 6464
6470 6465 /*
6471 6466 * When local station wants to delete BA agreement that was originated by AP,
6472 6467 * Net80211 module will call this function to clean up relevant information
6473 6468 * in hardware.
6474 6469 */
6475 6470 static int
6476 6471 iwh_send_action(struct ieee80211_node *in,
6477 6472 int category, int action, uint16_t args[4])
6478 6473 {
6479 6474 struct ieee80211com *ic;
6480 6475 iwh_sc_t *sc;
6481 6476 uint32_t tid;
6482 6477 iwh_add_sta_t node;
6483 6478 int ret = EIO;
6484 6479 int err = IWH_FAIL;
6485 6480
6486 6481
6487 6482 if (NULL == in) {
6488 6483 return (ret);
6489 6484 }
6490 6485
6491 6486 ic = in->in_ic;
6492 6487 if (NULL == ic) {
6493 6488 return (ret);
6494 6489 }
6495 6490
6496 6491 sc = (iwh_sc_t *)ic;
6497 6492
6498 6493 ret = sc->sc_send_action(in, category, action, args);
6499 6494
6500 6495 if (category != IEEE80211_ACTION_CAT_BA) {
6501 6496 return (ret);
6502 6497 }
6503 6498
6504 6499 switch (action) {
6505 6500 case IEEE80211_ACTION_BA_DELBA:
6506 6501 if (IEEE80211_DELBAPS_INIT == args[1]) {
6507 6502 return (ret);
6508 6503 }
6509 6504
6510 6505 tid = args[0];
6511 6506
6512 6507 (void) memset(&node, 0, sizeof (node));
6513 6508 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6514 6509 node.mode = STA_MODE_MODIFY_MSK;
6515 6510 node.sta.sta_id = IWH_AP_ID;
6516 6511
6517 6512 node.station_flags_msk = 0;
6518 6513 node.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
6519 6514 node.add_immediate_ba_tid = (uint8_t)tid;
6520 6515
6521 6516 mutex_enter(&sc->sc_glock);
6522 6517 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6523 6518 if (err != IWH_SUCCESS) {
6524 6519 cmn_err(CE_WARN, "iwh_send_action(): "
6525 6520 "failed to delete RX balock ACK\n");
6526 6521 mutex_exit(&sc->sc_glock);
6527 6522 return (EIO);
6528 6523 }
6529 6524 mutex_exit(&sc->sc_glock);
6530 6525
6531 6526 IWH_DBG((IWH_DEBUG_BA, "iwh_send_action(): "
6532 6527 "RX block ACK "
6533 6528 "was deleted on TID %d.\n", tid));
6534 6529
6535 6530 break;
6536 6531 }
6537 6532
6538 6533 return (ret);
6539 6534 }
6540 6535
6541 6536 static int
6542 6537 iwh_reset_hw(iwh_sc_t *sc)
6543 6538 {
6544 6539 uint32_t tmp;
6545 6540 int n;
6546 6541
6547 6542 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6548 6543 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6549 6544 tmp | CSR_HW_IF_CONFIG_REG_BITS_NIC_READY);
6550 6545
6551 6546 /*
6552 6547 * wait for HW ready
6553 6548 */
6554 6549 for (n = 0; n < 5; n++) {
6555 6550 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6556 6551 CSR_HW_IF_CONFIG_REG_BITS_NIC_READY) {
6557 6552 break;
6558 6553 }
6559 6554 DELAY(10);
6560 6555 }
6561 6556
6562 6557 if (n != 5) {
6563 6558 return (IWH_SUCCESS);
6564 6559 }
6565 6560
6566 6561 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6567 6562 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6568 6563 tmp | CSR_HW_IF_CONFIG_REG_BITS_PREPARE);
6569 6564
6570 6565 for (n = 0; n < 15000; n++) {
6571 6566 if (0 == (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6572 6567 CSR_HW_IF_CONFIG_REG_BITS_NIC_PREPARE_DONE)) {
6573 6568 break;
6574 6569 }
6575 6570 DELAY(10);
6576 6571 }
6577 6572
6578 6573 if (15000 == n) {
6579 6574 return (ETIMEDOUT);
6580 6575 }
6581 6576
6582 6577 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6583 6578 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6584 6579 tmp | CSR_HW_IF_CONFIG_REG_BITS_NIC_READY);
6585 6580
6586 6581 /*
6587 6582 * wait for HW ready
6588 6583 */
6589 6584 for (n = 0; n < 5; n++) {
6590 6585 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6591 6586 CSR_HW_IF_CONFIG_REG_BITS_NIC_READY) {
6592 6587 break;
6593 6588 }
6594 6589 DELAY(10);
6595 6590 }
6596 6591
6597 6592 if (n != 5) {
6598 6593 return (IWH_SUCCESS);
6599 6594 } else {
6600 6595 return (ETIMEDOUT);
6601 6596 }
6602 6597 }
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