799 ecr = RTW_READ8(regs, RTW_9346CR);
800
801 if ((flags & RTW_F_9356SROM) != 0) {
802 RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: 93c56 SROM\n", dvname);
803 sr->sr_size = 256;
804 sd.sd_chip = C56_66;
805 } else {
806 RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: 93c46 SROM\n", dvname);
807 sr->sr_size = 128;
808 sd.sd_chip = C46;
809 }
810
811 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
812 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
813 ecr |= RTW_9346CR_EEM_PROGRAM;
814
815 RTW_WRITE8(regs, RTW_9346CR, ecr);
816
817 sr->sr_content = kmem_zalloc(sr->sr_size, KM_SLEEP);
818
819 if (sr->sr_content == NULL) {
820 cmn_err(CE_WARN, "%s: unable to allocate SROM buffer\n",
821 dvname);
822 return (ENOMEM);
823 }
824
825 (void) memset(sr->sr_content, 0, sr->sr_size);
826
827 /*
828 * RTL8180 has a single 8-bit register for controlling the
829 * 93cx6 SROM. There is no "ready" bit. The RTL8180
830 * input/output sense is the reverse of read_seeprom's.
831 */
832 sd.sd_handle = regs->r_handle;
833 sd.sd_base = regs->r_base;
834 sd.sd_regsize = 1;
835 sd.sd_control_offset = RTW_9346CR;
836 sd.sd_status_offset = RTW_9346CR;
837 sd.sd_dataout_offset = RTW_9346CR;
838 sd.sd_CK = RTW_9346CR_EESK;
839 sd.sd_CS = RTW_9346CR_EECS;
840 sd.sd_DI = RTW_9346CR_EEDO;
841 sd.sd_DO = RTW_9346CR_EEDI;
842 /*
843 * make read_seeprom enter EEPROM read/write mode
844 */
|
799 ecr = RTW_READ8(regs, RTW_9346CR);
800
801 if ((flags & RTW_F_9356SROM) != 0) {
802 RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: 93c56 SROM\n", dvname);
803 sr->sr_size = 256;
804 sd.sd_chip = C56_66;
805 } else {
806 RTW_DPRINTF(RTW_DEBUG_ATTACH, "%s: 93c46 SROM\n", dvname);
807 sr->sr_size = 128;
808 sd.sd_chip = C46;
809 }
810
811 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
812 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
813 ecr |= RTW_9346CR_EEM_PROGRAM;
814
815 RTW_WRITE8(regs, RTW_9346CR, ecr);
816
817 sr->sr_content = kmem_zalloc(sr->sr_size, KM_SLEEP);
818
819 (void) memset(sr->sr_content, 0, sr->sr_size);
820
821 /*
822 * RTL8180 has a single 8-bit register for controlling the
823 * 93cx6 SROM. There is no "ready" bit. The RTL8180
824 * input/output sense is the reverse of read_seeprom's.
825 */
826 sd.sd_handle = regs->r_handle;
827 sd.sd_base = regs->r_base;
828 sd.sd_regsize = 1;
829 sd.sd_control_offset = RTW_9346CR;
830 sd.sd_status_offset = RTW_9346CR;
831 sd.sd_dataout_offset = RTW_9346CR;
832 sd.sd_CK = RTW_9346CR_EESK;
833 sd.sd_CS = RTW_9346CR_EECS;
834 sd.sd_DI = RTW_9346CR_EEDO;
835 sd.sd_DO = RTW_9346CR_EEDI;
836 /*
837 * make read_seeprom enter EEPROM read/write mode
838 */
|