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5255 uts shouldn't open-code ISP2
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--- old/usr/src/uts/common/io/ib/adapters/tavor/tavor_cfg.c
+++ new/usr/src/uts/common/io/ib/adapters/tavor/tavor_cfg.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
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25 25 */
26 26
27 27 /*
28 28 * tavor_cfg.c
29 29 * Tavor Configuration Profile Routines
30 30 *
31 31 * Implements the routines necessary for initializing and (later) tearing
32 32 * down the list of Tavor configuration information.
33 33 */
34 34
35 +#include <sys/sysmacros.h>
35 36 #include <sys/types.h>
36 37 #include <sys/conf.h>
37 38 #include <sys/ddi.h>
38 39 #include <sys/sunddi.h>
39 40 #include <sys/modctl.h>
40 41 #include <sys/bitmap.h>
41 42
42 43 #include <sys/ib/adapters/tavor/tavor.h>
43 44
44 45 /* Set to enable alternative configurations: 0 = automatic config, 1 = manual */
45 46 uint32_t tavor_alt_config_enable = 0;
46 47
47 48 /* Number of supported QPs and their maximum size */
48 49 uint32_t tavor_log_num_qp = TAVOR_NUM_QP_SHIFT_128;
49 50 uint32_t tavor_log_max_qp_sz = TAVOR_QP_SZ_SHIFT;
50 51
51 52 /* Number of supported SGL per WQE */
52 53 uint32_t tavor_wqe_max_sgl = TAVOR_NUM_WQE_SGL;
53 54
54 55 /* Number of supported CQs and their maximum size */
55 56 uint32_t tavor_log_num_cq = TAVOR_NUM_CQ_SHIFT_128;
56 57 uint32_t tavor_log_max_cq_sz = TAVOR_CQ_SZ_SHIFT;
57 58
58 59 /* Select to enable SRQ or not; NOTE: 0 for disabled, 1 for enabled */
59 60 uint32_t tavor_srq_enable = 1;
60 61
61 62 /* Number of supported SRQs and their maximum size */
62 63 uint32_t tavor_log_num_srq = TAVOR_NUM_SRQ_SHIFT_128;
63 64 uint32_t tavor_log_max_srq_sz = TAVOR_SRQ_SZ_SHIFT;
64 65 uint32_t tavor_srq_max_sgl = TAVOR_SRQ_MAX_SGL;
65 66
66 67 /* Default size for all EQs */
67 68 uint32_t tavor_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
68 69
69 70 /* Number of supported RDB (for incoming RDMA Read/Atomic) */
70 71 uint32_t tavor_log_num_rdb = TAVOR_NUM_RDB_SHIFT_128;
71 72
72 73 /*
73 74 * Number of support multicast groups, number of QP per multicast group, and
74 75 * the number of entries (from the total number) in the multicast group "hash
75 76 * table"
76 77 */
77 78 uint32_t tavor_log_num_mcg = TAVOR_NUM_MCG_SHIFT;
78 79 uint32_t tavor_num_qp_per_mcg = TAVOR_NUM_QP_PER_MCG;
79 80 uint32_t tavor_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT;
80 81
81 82 /*
82 83 * Number of supported MPTs (memory regions and windows) and their maximum
83 84 * size. Also the number of MTT per "MTT segment" (see tavor_mr.h for more
84 85 * details)
85 86 */
86 87 uint32_t tavor_log_num_mpt = TAVOR_NUM_MPT_SHIFT_128;
87 88 uint32_t tavor_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_128;
88 89 uint32_t tavor_log_num_mttseg = TAVOR_NUM_MTTSEG_SHIFT;
89 90
90 91 /*
91 92 * Number of supported Tavor mailboxes ("In" and "Out") and their maximum
92 93 * sizes, respectively
93 94 */
94 95 uint32_t tavor_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
95 96 uint32_t tavor_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
96 97 uint32_t tavor_log_num_intr_inmbox = TAVOR_NUM_INTR_MAILBOXES_SHIFT;
97 98 uint32_t tavor_log_num_intr_outmbox = TAVOR_NUM_INTR_MAILBOXES_SHIFT;
98 99 uint32_t tavor_log_inmbox_size = TAVOR_MBOX_SIZE_SHIFT;
99 100 uint32_t tavor_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
100 101
101 102 /* Number of supported UAR pages */
102 103 uint32_t tavor_log_num_uar = TAVOR_NUM_UAR_SHIFT;
103 104
104 105 /* Number of supported Protection Domains (PD) */
105 106 uint32_t tavor_log_num_pd = TAVOR_NUM_PD_SHIFT;
106 107
107 108 /* Number of supported Address Handles (AH) */
108 109 uint32_t tavor_log_num_ah = TAVOR_NUM_AH_SHIFT;
109 110
110 111 /*
111 112 * Number of total supported PKeys per PKey table (i.e.
112 113 * per port). Also the number of SGID per GID table.
113 114 */
114 115 uint32_t tavor_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
115 116 uint32_t tavor_log_max_gidtbl = TAVOR_NUM_GIDTBL_SHIFT;
116 117
117 118 /* Maximum "responder resources" (in) and "initiator depth" (out) per QP */
118 119 uint32_t tavor_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
119 120 uint32_t tavor_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
120 121
121 122 /* Maximum supported MTU and portwidth */
122 123 uint32_t tavor_max_mtu = TAVOR_MAX_MTU;
123 124 uint32_t tavor_max_port_width = TAVOR_MAX_PORT_WIDTH;
124 125
125 126 /* Number of supported Virtual Lanes (VL) */
126 127 uint32_t tavor_max_vlcap = TAVOR_MAX_VLCAP;
127 128
128 129 /* Number of supported ports (1 or 2) */
129 130 uint32_t tavor_num_ports = TAVOR_NUM_PORTS;
130 131
131 132 /*
132 133 * Whether or not to use the built-in (i.e. in firmware) agents for QP0 and
133 134 * QP1, respectively.
134 135 */
135 136 uint32_t tavor_qp0_agents_in_fw = 1;
136 137 uint32_t tavor_qp1_agents_in_fw = 0;
137 138
138 139 /*
139 140 * Whether DMA mappings should be made with DDI_DMA_STREAMING or with
140 141 * DDI_DMA_CONSISTENT mode. Note: 0 for "streaming", 1 for "consistent"
141 142 */
142 143 uint32_t tavor_streaming_consistent = 1;
143 144
144 145 /*
145 146 * For DMA mappings made with DDI_DMA_CONSISTENT, this flag determines
146 147 * whether to override the necessity for calls to ddi_dma_sync().
147 148 */
148 149 uint32_t tavor_consistent_syncoverride = 0;
149 150
150 151 /*
151 152 * Whether DMA mappings should bypass the PCI IOMMU or not.
152 153 * tavor_iommu_bypass is a global setting for all memory addresses. However,
153 154 * if set to BYPASS, memory attempted to be registered for streaming (ie:
154 155 * NON-COHERENT) will necessarily turn off BYPASS for that registration. To
155 156 * instead disable streaming in this situation the
156 157 * 'tavor_disable_streaming_on_bypass' can be set to 1. This setting will
157 158 * change the memory mapping to be implicitly consistent (ie: COHERENT), and
158 159 * will still perform the iommu BYPASS operation.
159 160 */
160 161 uint32_t tavor_iommu_bypass = 1;
161 162 uint32_t tavor_disable_streaming_on_bypass = 0;
162 163
163 164 /*
164 165 * Whether QP work queues should be allocated from system memory or
165 166 * from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
166 167 */
167 168 uint32_t tavor_qp_wq_inddr = 0;
168 169
169 170 /*
170 171 * Whether SRQ work queues should be allocated from system memory or
171 172 * from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
172 173 */
173 174 uint32_t tavor_srq_wq_inddr = 0;
174 175
175 176 /*
176 177 * Whether Tavor should use MSI (Message Signaled Interrupts), if available.
177 178 * Note: 0 indicates 'legacy interrupt', 1 indicates MSI (if available)
178 179 */
179 180 uint32_t tavor_use_msi_if_avail = 1;
180 181
181 182 /*
182 183 * This is a patchable variable that determines the time we will wait after
183 184 * initiating SW reset before we do our first read from Tavor config space.
184 185 * If this value is set too small (less than the default 100ms), it is
185 186 * possible for Tavor hardware to be unready to respond to the config cycle
186 187 * reads. This could cause master abort on the PCI bridge. Note: If
187 188 * "tavor_sw_reset_delay" is set to zero, then no software reset of the Tavor
188 189 * device will be attempted.
189 190 */
190 191 uint32_t tavor_sw_reset_delay = TAVOR_SW_RESET_DELAY;
191 192
192 193 /*
193 194 * These are patchable variables for tavor command polling. The poll_delay is
194 195 * the number of usec to wait in-between calls to poll the 'go' bit. The
195 196 * poll_max is the total number of usec to loop in waiting for the 'go' bit to
196 197 * clear.
197 198 */
198 199 uint32_t tavor_cmd_poll_delay = TAVOR_CMD_POLL_DELAY;
199 200 uint32_t tavor_cmd_poll_max = TAVOR_CMD_POLL_MAX;
200 201
201 202 /*
202 203 * This is a patchable variable that determines the frequency with which
203 204 * the AckReq bit will be set in outgoing RC packets. The AckReq bit will be
204 205 * set in at least every 2^tavor_qp_ackreq_freq packets (but at least once
205 206 * per message, i.e. in the last packet). Tuning this value can increase
206 207 * IB fabric utilization by cutting down on the number of unnecessary ACKs.
207 208 */
208 209 uint32_t tavor_qp_ackreq_freq = TAVOR_QP_ACKREQ_FREQ;
209 210
210 211 /*
211 212 * This is a patchable variable that determines the default value for the
212 213 * maximum number of outstanding split transactions. The number of
213 214 * outstanding split transations (i.e. PCI reads) has an affect on device
214 215 * throughput. The value here should not be modified as it defines the
215 216 * default (least common denominator - one (1) PCI read) behavior that is
216 217 * guaranteed to work, regardless of how the Tavor firmware has been
217 218 * initialized. The format for this variable is the same as the corresponding
218 219 * field in the "PCI-X Command Register".
219 220 */
220 221 #ifdef __sparc
221 222 /*
222 223 * Default SPARC platforms to be 1 outstanding PCI read.
223 224 */
224 225 int tavor_max_out_splt_trans = 0;
225 226 #else
226 227 /*
227 228 * Default non-SPARC platforms to be the default as set in tavor firmware
228 229 * number of outstanding PCI reads.
229 230 */
230 231 int tavor_max_out_splt_trans = -1;
231 232 #endif
232 233
233 234 /*
234 235 * This is a patchable variable that determines the default value for the
235 236 * maximum size of PCI read burst. This maximum size has an affect on
236 237 * device throughput. The value here should not be modified as it defines
237 238 * the default (least common denominator - 512B read) behavior that is
238 239 * guaranteed to work, regardless of how the Tavor device has been
239 240 * initialized. The format for this variable is the same as the corresponding
240 241 * field in the "PCI-X Command Register".
241 242 */
242 243 #ifdef __sparc
243 244 /*
244 245 * Default SPARC platforms to be 512B read.
245 246 */
246 247 int tavor_max_mem_rd_byte_cnt = 0;
247 248 static void tavor_check_iommu_bypass(tavor_state_t *state,
248 249 tavor_cfg_profile_t *cp);
249 250 #else
250 251 /*
251 252 * Default non-SPARC platforms to be the default as set in tavor firmware.
252 253 *
253 254 */
254 255 int tavor_max_mem_rd_byte_cnt = -1;
255 256 #endif
256 257
257 258 static void tavor_cfg_wqe_sizes(tavor_cfg_profile_t *cp);
258 259 static void tavor_cfg_prop_lookup(tavor_state_t *state,
259 260 tavor_cfg_profile_t *cp);
260 261
261 262 /*
262 263 * tavor_cfg_profile_init_phase1()
263 264 * Context: Only called from attach() path context
264 265 */
265 266 int
266 267 tavor_cfg_profile_init_phase1(tavor_state_t *state)
267 268 {
268 269 tavor_cfg_profile_t *cp;
269 270
270 271 TAVOR_TNF_ENTER(tavor_cfg_profile_init_phase1);
271 272
272 273 /*
273 274 * Allocate space for the configuration profile structure
274 275 */
275 276 cp = (tavor_cfg_profile_t *)kmem_zalloc(sizeof (tavor_cfg_profile_t),
276 277 KM_SLEEP);
277 278
278 279 cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
279 280 cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
280 281 cp->cp_sw_reset_delay = tavor_sw_reset_delay;
281 282 cp->cp_cmd_poll_delay = tavor_cmd_poll_delay;
282 283 cp->cp_cmd_poll_max = tavor_cmd_poll_max;
283 284 cp->cp_ackreq_freq = tavor_qp_ackreq_freq;
284 285 cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
285 286 cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
286 287 cp->cp_srq_enable = tavor_srq_enable;
287 288 cp->cp_fmr_enable = 0;
288 289 cp->cp_fmr_max_remaps = 0;
289 290
290 291 /*
291 292 * Although most of the configuration is enabled in "phase2" of the
292 293 * cfg_profile_init, we have to setup the OUT mailboxes here, since
293 294 * they are used immediately after this "phase1" completes. Check for
294 295 * alt_config_enable, and set the values appropriately. Otherwise, the
295 296 * config profile is setup using the values based on the dimm size.
296 297 * While it is expected that the mailbox size and number will remain
297 298 * the same independent of dimm size, we separate it out here anyway
298 299 * for completeness.
299 300 *
300 301 * We have to setup SRQ settings here because MOD_STAT_CFG must be
301 302 * called before our call to QUERY_DEVLIM. If SRQ is enabled, then we
302 303 * must enable it in the firmware so that the phase2 settings will have
303 304 * the right device limits.
304 305 */
305 306 if (tavor_alt_config_enable) {
306 307 cp->cp_log_num_outmbox = tavor_log_num_outmbox;
307 308 cp->cp_log_num_intr_outmbox = tavor_log_num_intr_outmbox;
308 309 cp->cp_log_outmbox_size = tavor_log_outmbox_size;
309 310 cp->cp_log_num_inmbox = tavor_log_num_inmbox;
310 311 cp->cp_log_num_intr_inmbox = tavor_log_num_intr_inmbox;
311 312 cp->cp_log_inmbox_size = tavor_log_inmbox_size;
312 313 cp->cp_log_num_srq = tavor_log_num_srq;
313 314 cp->cp_log_max_srq_sz = tavor_log_max_srq_sz;
314 315
315 316 } else if (state->ts_cfg_profile_setting >= TAVOR_DDR_SIZE_256) {
316 317 cp->cp_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
317 318 cp->cp_log_num_intr_outmbox =
318 319 TAVOR_NUM_INTR_MAILBOXES_SHIFT;
319 320 cp->cp_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
320 321 cp->cp_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
321 322 cp->cp_log_num_intr_inmbox =
322 323 TAVOR_NUM_INTR_MAILBOXES_SHIFT;
323 324 cp->cp_log_inmbox_size = TAVOR_MBOX_SIZE_SHIFT;
324 325 cp->cp_log_num_srq = TAVOR_NUM_SRQ_SHIFT_256;
325 326 cp->cp_log_max_srq_sz = TAVOR_SRQ_SZ_SHIFT;
326 327
327 328 } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_128) {
328 329 cp->cp_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
329 330 cp->cp_log_num_intr_outmbox =
330 331 TAVOR_NUM_INTR_MAILBOXES_SHIFT;
331 332 cp->cp_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
332 333 cp->cp_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
333 334 cp->cp_log_num_intr_inmbox =
334 335 TAVOR_NUM_INTR_MAILBOXES_SHIFT;
335 336 cp->cp_log_inmbox_size = TAVOR_MBOX_SIZE_SHIFT;
336 337 cp->cp_log_num_srq = TAVOR_NUM_SRQ_SHIFT_128;
337 338 cp->cp_log_max_srq_sz = TAVOR_SRQ_SZ_SHIFT;
338 339
339 340 } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_MIN) {
340 341 cp->cp_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
341 342 cp->cp_log_num_intr_outmbox =
342 343 TAVOR_NUM_INTR_MAILBOXES_SHIFT;
343 344 cp->cp_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
344 345 cp->cp_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
345 346 cp->cp_log_num_intr_inmbox =
346 347 TAVOR_NUM_INTR_MAILBOXES_SHIFT;
347 348 cp->cp_log_inmbox_size = TAVOR_MBOX_SIZE_SHIFT;
348 349 cp->cp_log_num_srq = TAVOR_NUM_SRQ_SHIFT_MIN;
349 350 cp->cp_log_max_srq_sz = TAVOR_SRQ_SZ_SHIFT_MIN;
350 351
351 352 } else {
352 353 TNF_PROBE_0(tavor_cfg_profile_invalid_dimmsz_fail,
353 354 TAVOR_TNF_ERROR, "");
354 355 return (DDI_FAILURE);
355 356 }
356 357
357 358 /*
358 359 * Set default DMA mapping mode. Ensure consistency of flags
359 360 * with both architecture type and other configuration flags.
360 361 */
361 362 if (tavor_streaming_consistent == 0) {
362 363 #ifdef __sparc
363 364 cp->cp_streaming_consistent = DDI_DMA_STREAMING;
364 365
365 366 /* Can't do both "streaming" and IOMMU bypass */
366 367 if (tavor_iommu_bypass != 0) {
367 368 TNF_PROBE_0(tavor_cfg_profile_streamingbypass_fail,
368 369 TAVOR_TNF_ERROR, "");
369 370 kmem_free(cp, sizeof (tavor_cfg_profile_t));
370 371 return (DDI_FAILURE);
371 372 }
372 373 #else
373 374 cp->cp_streaming_consistent = DDI_DMA_CONSISTENT;
374 375 #endif
375 376 } else {
376 377 cp->cp_streaming_consistent = DDI_DMA_CONSISTENT;
377 378 }
378 379
379 380 /* Determine whether to override ddi_dma_sync() */
380 381 cp->cp_consistent_syncoverride = tavor_consistent_syncoverride;
381 382
382 383 /* Attach the configuration profile to Tavor softstate */
383 384 state->ts_cfg_profile = cp;
384 385
385 386 TAVOR_TNF_EXIT(tavor_cfg_profile_init_phase1);
386 387 return (DDI_SUCCESS);
387 388 }
388 389
389 390 /*
390 391 * tavor_cfg_profile_init_phase2()
391 392 * Context: Only called from attach() path context
392 393 */
393 394 int
394 395 tavor_cfg_profile_init_phase2(tavor_state_t *state)
395 396 {
396 397 tavor_cfg_profile_t *cp;
397 398
398 399 TAVOR_TNF_ENTER(tavor_cfg_profile_init_phase2);
399 400
400 401 /* Read the configuration profile from Tavor softstate */
401 402 cp = state->ts_cfg_profile;
402 403
403 404 /*
404 405 * Verify the config profile setting. The 'setting' should already be
405 406 * set, during a call to ddi_dev_regsize() to get the size of DDR
406 407 * memory, or during a fallback to a smaller supported size. If it is
407 408 * not set, we should not have reached this 'phase2'. So we assert
408 409 * here.
409 410 */
410 411 ASSERT(state->ts_cfg_profile_setting != 0);
411 412
412 413 /*
413 414 * The automatic configuration override is the
414 415 * 'tavor_alt_config_enable' variable. If this is set, we no longer
415 416 * use the DIMM size to enable the correct profile. Instead, all of
416 417 * the tavor config options at the top of this file are used directly.
417 418 *
418 419 * This allows customization for a user who knows what they are doing
419 420 * to set tavor configuration values manually.
420 421 *
421 422 * If this variable is 0, we do automatic config for both 128MB and
422 423 * 256MB DIMM sizes.
423 424 */
424 425 if (tavor_alt_config_enable) {
425 426 /*
426 427 * Initialize the configuration profile
427 428 */
428 429 cp->cp_log_num_qp = tavor_log_num_qp;
429 430 cp->cp_log_max_qp_sz = tavor_log_max_qp_sz;
430 431
431 432 /* Determine WQE sizes from requested max SGLs */
432 433 tavor_cfg_wqe_sizes(cp);
433 434
434 435 cp->cp_log_num_cq = tavor_log_num_cq;
435 436 cp->cp_log_max_cq_sz = tavor_log_max_cq_sz;
436 437 cp->cp_log_default_eq_sz = tavor_log_default_eq_sz;
437 438 cp->cp_log_num_rdb = tavor_log_num_rdb;
438 439 cp->cp_log_num_mcg = tavor_log_num_mcg;
439 440 cp->cp_num_qp_per_mcg = tavor_num_qp_per_mcg;
440 441 cp->cp_log_num_mcg_hash = tavor_log_num_mcg_hash;
441 442 cp->cp_log_num_mpt = tavor_log_num_mpt;
442 443 cp->cp_log_max_mrw_sz = tavor_log_max_mrw_sz;
443 444 cp->cp_log_num_mttseg = tavor_log_num_mttseg;
444 445 cp->cp_log_num_uar = tavor_log_num_uar;
445 446 cp->cp_log_num_pd = tavor_log_num_pd;
446 447 cp->cp_log_num_ah = tavor_log_num_ah;
447 448 cp->cp_log_max_pkeytbl = tavor_log_max_pkeytbl;
448 449 cp->cp_log_max_gidtbl = tavor_log_max_gidtbl;
449 450 cp->cp_hca_max_rdma_in_qp = tavor_hca_max_rdma_in_qp;
450 451 cp->cp_hca_max_rdma_out_qp = tavor_hca_max_rdma_out_qp;
451 452 cp->cp_max_mtu = tavor_max_mtu;
452 453 cp->cp_max_port_width = tavor_max_port_width;
453 454 cp->cp_max_vlcap = tavor_max_vlcap;
454 455 cp->cp_num_ports = tavor_num_ports;
455 456 cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
456 457 cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
457 458 cp->cp_sw_reset_delay = tavor_sw_reset_delay;
458 459 cp->cp_ackreq_freq = tavor_qp_ackreq_freq;
459 460 cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
460 461 cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
461 462
462 463 } else if (state->ts_cfg_profile_setting >= TAVOR_DDR_SIZE_256) {
463 464 /*
464 465 * Initialize the configuration profile
465 466 */
466 467 cp->cp_log_num_qp = TAVOR_NUM_QP_SHIFT_256;
467 468 cp->cp_log_max_qp_sz = TAVOR_QP_SZ_SHIFT;
468 469
469 470 /* Determine WQE sizes from requested max SGLs */
470 471 tavor_cfg_wqe_sizes(cp);
471 472
472 473 cp->cp_log_num_cq = TAVOR_NUM_CQ_SHIFT_256;
473 474 cp->cp_log_max_cq_sz = TAVOR_CQ_SZ_SHIFT;
474 475 cp->cp_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
475 476 cp->cp_log_num_rdb = TAVOR_NUM_RDB_SHIFT_256;
476 477 cp->cp_log_num_mcg = TAVOR_NUM_MCG_SHIFT;
477 478 cp->cp_num_qp_per_mcg = TAVOR_NUM_QP_PER_MCG;
478 479 cp->cp_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT;
479 480 cp->cp_log_num_mpt = TAVOR_NUM_MPT_SHIFT_256;
480 481 cp->cp_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_256;
481 482 cp->cp_log_num_mttseg = TAVOR_NUM_MTTSEG_SHIFT;
482 483 cp->cp_log_num_uar = TAVOR_NUM_UAR_SHIFT;
483 484 cp->cp_log_num_pd = TAVOR_NUM_PD_SHIFT;
484 485 cp->cp_log_num_ah = TAVOR_NUM_AH_SHIFT;
485 486 cp->cp_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
486 487 cp->cp_log_max_gidtbl = TAVOR_NUM_GIDTBL_SHIFT;
487 488 cp->cp_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
488 489 cp->cp_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
489 490 cp->cp_max_mtu = TAVOR_MAX_MTU;
490 491 cp->cp_max_port_width = TAVOR_MAX_PORT_WIDTH;
491 492 cp->cp_max_vlcap = TAVOR_MAX_VLCAP;
492 493 cp->cp_num_ports = TAVOR_NUM_PORTS;
493 494 cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
494 495 cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
495 496 cp->cp_sw_reset_delay = tavor_sw_reset_delay;
496 497 cp->cp_ackreq_freq = tavor_qp_ackreq_freq;
497 498 cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
498 499 cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
499 500
500 501 } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_128) {
501 502 /*
502 503 * Initialize the configuration profile
503 504 */
504 505 cp->cp_log_num_qp = TAVOR_NUM_QP_SHIFT_128;
505 506 cp->cp_log_max_qp_sz = TAVOR_QP_SZ_SHIFT;
506 507
507 508 /* Determine WQE sizes from requested max SGLs */
508 509 tavor_cfg_wqe_sizes(cp);
509 510
510 511 cp->cp_log_num_cq = TAVOR_NUM_CQ_SHIFT_128;
511 512 cp->cp_log_max_cq_sz = TAVOR_CQ_SZ_SHIFT;
512 513 cp->cp_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
513 514 cp->cp_log_num_rdb = TAVOR_NUM_RDB_SHIFT_128;
514 515 cp->cp_log_num_mcg = TAVOR_NUM_MCG_SHIFT;
515 516 cp->cp_num_qp_per_mcg = TAVOR_NUM_QP_PER_MCG;
516 517 cp->cp_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT;
517 518 cp->cp_log_num_mpt = TAVOR_NUM_MPT_SHIFT_128;
518 519 cp->cp_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_128;
519 520 cp->cp_log_num_mttseg = TAVOR_NUM_MTTSEG_SHIFT;
520 521 cp->cp_log_num_uar = TAVOR_NUM_UAR_SHIFT;
521 522 cp->cp_log_num_pd = TAVOR_NUM_PD_SHIFT;
522 523 cp->cp_log_num_ah = TAVOR_NUM_AH_SHIFT;
523 524 cp->cp_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
524 525 cp->cp_log_max_gidtbl = TAVOR_NUM_GIDTBL_SHIFT;
525 526 cp->cp_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
526 527 cp->cp_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
527 528 cp->cp_max_mtu = TAVOR_MAX_MTU;
528 529 cp->cp_max_port_width = TAVOR_MAX_PORT_WIDTH;
529 530 cp->cp_max_vlcap = TAVOR_MAX_VLCAP;
530 531 cp->cp_num_ports = TAVOR_NUM_PORTS;
531 532 cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
532 533 cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
533 534 cp->cp_sw_reset_delay = tavor_sw_reset_delay;
534 535 cp->cp_ackreq_freq = tavor_qp_ackreq_freq;
535 536 cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
536 537 cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
537 538
538 539 } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_MIN) {
539 540 /*
540 541 * Initialize the configuration profile for minimal footprint.
541 542 */
542 543
543 544 cp->cp_log_num_qp = TAVOR_NUM_QP_SHIFT_MIN;
544 545 cp->cp_log_max_qp_sz = TAVOR_QP_SZ_SHIFT_MIN;
545 546
546 547 /* Determine WQE sizes from requested max SGLs */
547 548 tavor_cfg_wqe_sizes(cp);
548 549
549 550 cp->cp_log_num_cq = TAVOR_NUM_CQ_SHIFT_MIN;
550 551 cp->cp_log_max_cq_sz = TAVOR_CQ_SZ_SHIFT_MIN;
551 552 cp->cp_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
552 553 cp->cp_log_num_rdb = TAVOR_NUM_RDB_SHIFT_MIN;
553 554 cp->cp_log_num_mcg = TAVOR_NUM_MCG_SHIFT_MIN;
554 555 cp->cp_num_qp_per_mcg = TAVOR_NUM_QP_PER_MCG_MIN;
555 556 cp->cp_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT_MIN;
556 557 cp->cp_log_num_mpt = TAVOR_NUM_MPT_SHIFT_MIN;
557 558 cp->cp_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_MIN;
558 559 cp->cp_log_num_mttseg = TAVOR_NUM_MTTSEG_SHIFT_MIN;
559 560 cp->cp_log_num_uar = TAVOR_NUM_UAR_SHIFT_MIN;
560 561 cp->cp_log_num_pd = TAVOR_NUM_PD_SHIFT;
561 562 cp->cp_log_num_ah = TAVOR_NUM_AH_SHIFT_MIN;
562 563 cp->cp_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
563 564 cp->cp_log_max_gidtbl = TAVOR_NUM_GIDTBL_SHIFT;
564 565 cp->cp_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
565 566 cp->cp_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
566 567 cp->cp_max_mtu = TAVOR_MAX_MTU;
567 568 cp->cp_max_port_width = TAVOR_MAX_PORT_WIDTH;
568 569 cp->cp_max_vlcap = TAVOR_MAX_VLCAP;
569 570 cp->cp_num_ports = TAVOR_NUM_PORTS;
570 571 cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
571 572 cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
572 573 cp->cp_sw_reset_delay = tavor_sw_reset_delay;
573 574 cp->cp_ackreq_freq = tavor_qp_ackreq_freq;
574 575 cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
575 576 cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
576 577
577 578 } else {
578 579 TNF_PROBE_0(tavor_cfg_profile_invalid_dimmsz_fail,
579 580 TAVOR_TNF_ERROR, "");
580 581 return (DDI_FAILURE);
581 582 }
582 583
583 584 /*
584 585 * Set IOMMU bypass or not. Ensure consistency of flags with
585 586 * architecture type.
586 587 */
587 588 #ifdef __sparc
588 589 if (tavor_iommu_bypass == 1) {
589 590 tavor_check_iommu_bypass(state, cp);
590 591 } else {
591 592 cp->cp_iommu_bypass = TAVOR_BINDMEM_NORMAL;
592 593 cp->cp_disable_streaming_on_bypass = 0;
593 594 }
594 595 #else
595 596 cp->cp_iommu_bypass = TAVOR_BINDMEM_NORMAL;
596 597 cp->cp_disable_streaming_on_bypass = 0;
597 598 #endif
598 599 /* Set whether QP WQEs will be in DDR or not */
599 600 cp->cp_qp_wq_inddr = (tavor_qp_wq_inddr == 0) ?
600 601 TAVOR_QUEUE_LOCATION_NORMAL : TAVOR_QUEUE_LOCATION_INDDR;
601 602
602 603 /* Set whether SRQ WQEs will be in DDR or not */
603 604 cp->cp_srq_wq_inddr = (tavor_srq_wq_inddr == 0) ?
604 605 TAVOR_QUEUE_LOCATION_NORMAL : TAVOR_QUEUE_LOCATION_INDDR;
605 606
606 607 cp->cp_use_msi_if_avail = tavor_use_msi_if_avail;
607 608
608 609 /* Determine additional configuration from optional properties */
609 610 tavor_cfg_prop_lookup(state, cp);
610 611
611 612 TAVOR_TNF_EXIT(tavor_cfg_profile_init_phase2);
612 613 return (DDI_SUCCESS);
613 614 }
614 615
615 616
616 617 /*
617 618 * tavor_cfg_profile_fini()
618 619 * Context: Only called from attach() and/or detach() path contexts
619 620 */
620 621 void
621 622 tavor_cfg_profile_fini(tavor_state_t *state)
622 623 {
623 624 TAVOR_TNF_ENTER(tavor_cfg_profile_fini);
624 625
625 626 /*
626 627 * Free up the space for configuration profile
627 628 */
628 629 kmem_free(state->ts_cfg_profile, sizeof (tavor_cfg_profile_t));
629 630
630 631 TAVOR_TNF_EXIT(tavor_cfg_profile_fini);
631 632 }
632 633
633 634
634 635 /*
635 636 * tavor_cfg_wqe_sizes()
636 637 * Context: Only called from attach() path context
637 638 */
638 639 static void
639 640 tavor_cfg_wqe_sizes(tavor_cfg_profile_t *cp)
640 641 {
641 642 uint_t max_size, log2;
642 643 uint_t max_sgl, real_max_sgl;
643 644
644 645 /*
645 646 * Get the requested maximum number SGL per WQE from the Tavor
646 647 * patchable variable
647 648 */
648 649 max_sgl = tavor_wqe_max_sgl;
649 650
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650 651 /*
651 652 * Use requested maximum number of SGL to calculate the max descriptor
652 653 * size (while guaranteeing that the descriptor size is a power-of-2
653 654 * cachelines). We have to use the calculation for QP1 MLX transport
654 655 * because the possibility that we might need to inline a GRH, along
655 656 * with all the other headers and alignment restrictions, sets the
656 657 * maximum for the number of SGLs that we can advertise support for.
657 658 */
658 659 max_size = (TAVOR_QP_WQE_MLX_QP1_HDRS + (max_sgl << 4));
659 660 log2 = highbit(max_size);
660 - if ((max_size & (max_size - 1)) == 0) {
661 + if (ISP2(max_size)) {
661 662 log2 = log2 - 1;
662 663 }
663 664 max_size = (1 << log2);
664 665
665 666 /*
666 667 * Now clip the maximum descriptor size based on Tavor HW maximum
667 668 */
668 669 max_size = min(max_size, TAVOR_QP_WQE_MAX_SIZE);
669 670
670 671 /*
671 672 * Then use the calculated max descriptor size to determine the "real"
672 673 * maximum SGL (the number beyond which we would roll over to the next
673 674 * power-of-2).
674 675 */
675 676 real_max_sgl = (max_size - TAVOR_QP_WQE_MLX_QP1_HDRS) >> 4;
676 677
677 678 /* Then save away this configuration information */
678 679 cp->cp_wqe_max_sgl = max_sgl;
679 680 cp->cp_wqe_real_max_sgl = real_max_sgl;
680 681
681 682 /* SRQ SGL gets set to it's own patchable variable value */
682 683 cp->cp_srq_max_sgl = tavor_srq_max_sgl;
683 684 }
684 685
685 686
686 687 /*
687 688 * tavor_cfg_prop_lookup()
688 689 * Context: Only called from attach() path context
689 690 */
690 691 static void
691 692 tavor_cfg_prop_lookup(tavor_state_t *state, tavor_cfg_profile_t *cp)
692 693 {
693 694 uint_t num_ports, nelementsp;
694 695 uchar_t *datap;
695 696 int status;
696 697
697 698 /*
698 699 * Read the property defining the number of Tavor ports to
699 700 * support. If the property is undefined or invalid, then return.
700 701 * We return here assuming also that OBP is not supposed to be setting
701 702 * up other properties in this case (eg: HCA plugin cards). But if
702 703 * this property is valid, then we print out a message for the other
703 704 * properties to show an OBP error.
704 705 */
705 706 num_ports = ddi_prop_get_int(DDI_DEV_T_ANY, state->ts_dip,
706 707 DDI_PROP_DONTPASS, "#ports", 0);
707 708 if ((num_ports > TAVOR_NUM_PORTS) || (num_ports == 0)) {
708 709 return;
709 710 }
710 711 cp->cp_num_ports = num_ports;
711 712
712 713 /*
713 714 * The system image guid is not currently supported in the 1275
714 715 * binding. So we leave this commented out for now.
715 716 */
716 717 #ifdef SUPPORTED_IN_1275_BINDING
717 718 /*
718 719 * Read the property defining the value to use later to override the
719 720 * default SystemImageGUID (in firmware). If the property is
720 721 * undefined, then return.
721 722 */
722 723 status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, state->ts_dip,
723 724 DDI_PROP_DONTPASS, "system-image-guid", &datap, &nelementsp);
724 725 if (status == DDI_PROP_SUCCESS) {
725 726 cp->cp_sysimgguid = ((uint64_t *)datap)[0];
726 727 ddi_prop_free(datap);
727 728 } else {
728 729 cmn_err(CE_NOTE,
729 730 "Unable to read OBP system-image-guid property");
730 731 }
731 732 #endif
732 733
733 734 /*
734 735 * Read the property defining the value to use later to override
735 736 * the default SystemImageGUID (in firmware). If the property is
736 737 * undefined, then return.
737 738 */
738 739 status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, state->ts_dip,
739 740 DDI_PROP_DONTPASS, "node-guid", &datap, &nelementsp);
740 741 if (status == DDI_PROP_SUCCESS) {
741 742 cp->cp_nodeguid = ((uint64_t *)datap)[0];
742 743 ddi_prop_free(datap);
743 744 } else {
744 745 cmn_err(CE_NOTE, "Unable to read OBP node-guid property");
745 746 }
746 747
747 748 /*
748 749 * Using the value for the number of ports (above) read the properties
749 750 * used to later to override the default PortGUIDs for each Tavor port.
750 751 * If either of these properties are undefined, then return.
751 752 */
752 753 if (num_ports == TAVOR_NUM_PORTS) {
753 754 status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY,
754 755 state->ts_dip, DDI_PROP_DONTPASS, "port-2-guid", &datap,
755 756 &nelementsp);
756 757 if (status == DDI_PROP_SUCCESS) {
757 758 cp->cp_portguid[1] = ((uint64_t *)datap)[0];
758 759 ddi_prop_free(datap);
759 760 } else {
760 761 cmn_err(CE_NOTE,
761 762 "Unable to read OBP port-2-guid property");
762 763 }
763 764 }
764 765 status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, state->ts_dip,
765 766 DDI_PROP_DONTPASS, "port-1-guid", &datap, &nelementsp);
766 767 if (status == DDI_PROP_SUCCESS) {
767 768 cp->cp_portguid[0] = ((uint64_t *)datap)[0];
768 769 ddi_prop_free(datap);
769 770 } else {
770 771 cmn_err(CE_NOTE, "Unable to read OBP port-1-guid property");
771 772 }
772 773 }
773 774
774 775 #ifdef __sparc
775 776 /*
776 777 * tavor_check_iommu_bypass()
777 778 * Context: Only called from attach() path context
778 779 */
779 780 static void
780 781 tavor_check_iommu_bypass(tavor_state_t *state, tavor_cfg_profile_t *cp)
781 782 {
782 783 ddi_dma_handle_t dmahdl;
783 784 ddi_dma_attr_t dma_attr;
784 785 int status;
785 786
786 787 tavor_dma_attr_init(&dma_attr);
787 788
788 789 /* Try mapping for IOMMU bypass (Force Physical) */
789 790 dma_attr.dma_attr_flags = DDI_DMA_FORCE_PHYSICAL;
790 791
791 792 /*
792 793 * Call ddi_dma_alloc_handle(). If this returns DDI_DMA_BADATTR then
793 794 * it is not possible to use IOMMU bypass with our PCI bridge parent.
794 795 * For example, certain versions of Tomatillo do not support IOMMU
795 796 * bypass. Since the function we are in can only be called if iommu
796 797 * bypass was requested in the config profile, we configure for bypass
797 798 * if the ddi_dma_alloc_handle() was successful. Otherwise, we
798 799 * configure for non-bypass (ie: normal) mapping.
799 800 */
800 801 status = ddi_dma_alloc_handle(state->ts_dip, &dma_attr,
801 802 DDI_DMA_SLEEP, NULL, &dmahdl);
802 803 if (status == DDI_DMA_BADATTR) {
803 804 cp->cp_iommu_bypass = TAVOR_BINDMEM_NORMAL;
804 805 cp->cp_disable_streaming_on_bypass = 0;
805 806 } else {
806 807 cp->cp_iommu_bypass = TAVOR_BINDMEM_BYPASS;
807 808 cp->cp_disable_streaming_on_bypass =
808 809 tavor_disable_streaming_on_bypass;
809 810
810 811 if (status == DDI_SUCCESS) {
811 812 ddi_dma_free_handle(&dmahdl);
812 813 }
813 814 }
814 815 }
815 816 #endif
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