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5255 uts shouldn't open-code ISP2
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--- old/usr/src/uts/intel/io/drm/i915_gem_tiling.c
+++ new/usr/src/uts/intel/io/drm/i915_gem_tiling.c
1 1 /* BEGIN CSTYLED */
2 2
3 3 /*
4 4 * Copyright (c) 2009, Intel Corporation.
5 5 * All Rights Reserved.
6 6 *
7 7 * Permission is hereby granted, free of charge, to any person obtaining a
8 8 * copy of this software and associated documentation files (the "Software"),
9 9 * to deal in the Software without restriction, including without limitation
10 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 11 * and/or sell copies of the Software, and to permit persons to whom the
12 12 * Software is furnished to do so, subject to the following conditions:
13 13 *
14 14 * The above copyright notice and this permission notice (including the next
15 15 * paragraph) shall be included in all copies or substantial portions of the
16 16 * Software.
17 17 *
18 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 24 * IN THE SOFTWARE.
25 25 *
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26 26 * Authors:
27 27 * Eric Anholt <eric@anholt.net>
28 28 *
29 29 */
30 30
31 31 /*
32 32 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
33 33 * Use is subject to license terms.
34 34 */
35 35
36 +#include <sys/sysmacros.h>
36 37 #include "drmP.h"
37 38 #include "drm.h"
38 39 #include "i915_drm.h"
39 40 #include "i915_drv.h"
40 41
41 42 /** @file i915_gem_tiling.c
42 43 *
43 44 * Support for managing tiling state of buffer objects.
44 45 *
45 46 * The idea behind tiling is to increase cache hit rates by rearranging
46 47 * pixel data so that a group of pixel accesses are in the same cacheline.
47 48 * Performance improvement from doing this on the back/depth buffer are on
48 49 * the order of 30%.
49 50 *
50 51 * Intel architectures make this somewhat more complicated, though, by
51 52 * adjustments made to addressing of data when the memory is in interleaved
52 53 * mode (matched pairs of DIMMS) to improve memory bandwidth.
53 54 * For interleaved memory, the CPU sends every sequential 64 bytes
54 55 * to an alternate memory channel so it can get the bandwidth from both.
55 56 *
56 57 * The GPU also rearranges its accesses for increased bandwidth to interleaved
57 58 * memory, and it matches what the CPU does for non-tiled. However, when tiled
58 59 * it does it a little differently, since one walks addresses not just in the
59 60 * X direction but also Y. So, along with alternating channels when bit
60 61 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
61 62 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
62 63 * are common to both the 915 and 965-class hardware.
63 64 *
64 65 * The CPU also sometimes XORs in higher bits as well, to improve
65 66 * bandwidth doing strided access like we do so frequently in graphics. This
66 67 * is called "Channel XOR Randomization" in the MCH documentation. The result
67 68 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
68 69 * decode.
69 70 *
70 71 * All of this bit 6 XORing has an effect on our memory management,
71 72 * as we need to make sure that the 3d driver can correctly address object
72 73 * contents.
73 74 *
74 75 * If we don't have interleaved memory, all tiling is safe and no swizzling is
75 76 * required.
76 77 *
77 78 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
78 79 * 17 is not just a page offset, so as we page an objet out and back in,
79 80 * individual pages in it will have different bit 17 addresses, resulting in
80 81 * each 64 bytes being swapped with its neighbor!
81 82 *
82 83 * Otherwise, if interleaved, we have to tell the 3d driver what the address
83 84 * swizzling it needs to do is, since it's writing with the CPU to the pages
84 85 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
85 86 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
86 87 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
87 88 * to match what the GPU expects.
88 89 */
89 90
90 91 /**
91 92 * Detects bit 6 swizzling of address lookup between IGD access and CPU
92 93 * access through main memory.
93 94 */
94 95 void
95 96 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
96 97 {
97 98 drm_i915_private_t *dev_priv = dev->dev_private;
98 99 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
99 100 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
100 101
101 102 if (!IS_I9XX(dev)) {
102 103 /* As far as we know, the 865 doesn't have these bit 6
103 104 * swizzling issues.
104 105 */
105 106 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
106 107 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
107 108 } else if (IS_MOBILE(dev)) {
108 109 uint32_t dcc;
109 110
110 111 /* On mobile 9xx chipsets, channel interleave by the CPU is
111 112 * determined by DCC. For single-channel, neither the CPU
112 113 * nor the GPU do swizzling. For dual channel interleaved,
113 114 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
114 115 * 9 for Y tiled. The CPU's interleave is independent, and
115 116 * can be based on either bit 11 (haven't seen this yet) or
116 117 * bit 17 (common).
117 118 */
118 119
119 120 dcc = I915_READ(DCC);
120 121 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
121 122 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
122 123 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
123 124 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
124 125 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
125 126 break;
126 127 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
127 128 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
128 129 /* This is the base swizzling by the GPU for
129 130 * tiled buffers.
130 131 */
131 132 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
132 133 swizzle_y = I915_BIT_6_SWIZZLE_9;
133 134 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
134 135 /* Bit 11 swizzling by the CPU in addition. */
135 136 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
136 137 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
137 138 } else {
138 139 /* Bit 17 swizzling by the CPU in addition. */
139 140 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
140 141 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
141 142 }
142 143 break;
143 144 }
144 145 if (dcc == 0xffffffff) {
145 146 DRM_ERROR("Couldn't read from MCHBAR. "
146 147 "Disabling tiling.\n");
147 148 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
148 149 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
149 150 }
150 151 } else {
151 152 /* The 965, G33, and newer, have a very flexible memory
152 153 * configuration. It will enable dual-channel mode
153 154 * (interleaving) on as much memory as it can, and the GPU
154 155 * will additionally sometimes enable different bit 6
155 156 * swizzling for tiled objects from the CPU.
156 157 *
157 158 * Here's what I found on the G965:
158 159 * slot fill memory size swizzling
159 160 * 0A 0B 1A 1B 1-ch 2-ch
160 161 * 512 0 0 0 512 0 O
161 162 * 512 0 512 0 16 1008 X
162 163 * 512 0 0 512 16 1008 X
163 164 * 0 512 0 512 16 1008 X
164 165 * 1024 1024 1024 0 2048 1024 O
165 166 *
166 167 * We could probably detect this based on either the DRB
167 168 * matching, which was the case for the swizzling required in
168 169 * the table above, or from the 1-ch value being less than
169 170 * the minimum size of a rank.
170 171 */
171 172 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
172 173 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
173 174 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
174 175 } else {
175 176 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
176 177 swizzle_y = I915_BIT_6_SWIZZLE_9;
177 178 }
178 179 }
179 180
180 181 /* FIXME: check with memory config on IGDNG */
181 182 if (IS_IGDNG(dev)) {
182 183 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
183 184 swizzle_y = I915_BIT_6_SWIZZLE_9;
184 185 }
185 186
186 187 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
187 188 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
188 189 }
189 190
190 191
191 192 /**
192 193 * Returns the size of the fence for a tiled object of the given size.
193 194 */
194 195 static int
195 196 i915_get_fence_size(struct drm_device *dev, int size)
196 197 {
197 198 int i;
198 199 int start;
199 200
200 201 if (IS_I965G(dev)) {
201 202 /* The 965 can have fences at any page boundary. */
202 203
203 204 return (size + PAGE_SIZE-1) & ~(PAGE_SIZE-1);
204 205 } else {
205 206 /* Align the size to a power of two greater than the smallest
206 207 * fence size.
207 208 */
208 209 if (IS_I9XX(dev))
209 210 start = 1024 * 1024;
210 211 else
211 212 start = 512 * 1024;
212 213
213 214 for (i = start; i < size; i <<= 1)
214 215 ;
215 216
216 217 return i;
217 218 }
218 219 }
219 220
220 221 /* Check pitch constriants for all chips & tiling formats */
221 222 static int
222 223 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
223 224 {
224 225 int tile_width;
225 226
226 227 /* Linear is always fine */
227 228 if (tiling_mode == I915_TILING_NONE)
228 229 return 1;
229 230
230 231 if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
231 232 tile_width = 128;
232 233 else
233 234 tile_width = 512;
234 235
235 236 if (stride == 0)
236 237 return 0;
237 238
238 239 /* 965+ just needs multiples of tile width */
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239 240 if (IS_I965G(dev)) {
240 241 if (stride & (tile_width - 1))
241 242 return 0;
242 243 return 1;
243 244 }
244 245
245 246 /* Pre-965 needs power of two tile widths */
246 247 if (stride < tile_width)
247 248 return 0;
248 249
249 - if (stride & (stride - 1))
250 + if (!ISP2(stride))
250 251 return 0;
251 252
252 253 /* We don't handle the aperture area covered by the fence being bigger
253 254 * than the object size.
254 255 */
255 256 if (i915_get_fence_size(dev, size) != size)
256 257 return 0;
257 258
258 259 return 1;
259 260 }
260 261
261 262 /**
262 263 * Sets the tiling mode of an object, returning the required swizzling of
263 264 * bit 6 of addresses in the object.
264 265 */
265 266 /*ARGSUSED*/
266 267 int
267 268 i915_gem_set_tiling(DRM_IOCTL_ARGS)
268 269 {
269 270 DRM_DEVICE;
270 271 struct drm_i915_gem_set_tiling args;
271 272 drm_i915_private_t *dev_priv = dev->dev_private;
272 273 struct drm_gem_object *obj;
273 274 struct drm_i915_gem_object *obj_priv;
274 275 int ret;
275 276
276 277 if (dev->driver->use_gem != 1)
277 278 return ENODEV;
278 279
279 280 DRM_COPYFROM_WITH_RETURN(&args,
280 281 (struct drm_i915_gem_set_tiling __user *) data, sizeof(args));
281 282
282 283 obj = drm_gem_object_lookup(fpriv, args.handle);
283 284 if (obj == NULL)
284 285 return EINVAL;
285 286 obj_priv = obj->driver_private;
286 287
287 288 if (!i915_tiling_ok(dev, args.stride, obj->size, args.tiling_mode)) {
288 289 drm_gem_object_unreference(obj);
289 290 DRM_DEBUG("i915 tiling is not OK");
290 291 return EINVAL;
291 292 }
292 293
293 294 spin_lock(&dev->struct_mutex);
294 295
295 296 if (args.tiling_mode == I915_TILING_NONE) {
296 297 args.swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
297 298 } else {
298 299 if (args.tiling_mode == I915_TILING_X)
299 300 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
300 301 else
301 302 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
302 303 /* If we can't handle the swizzling, make it untiled. */
303 304 if (args.swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
304 305 args.tiling_mode = I915_TILING_NONE;
305 306 args.swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
306 307 }
307 308 }
308 309
309 310 if (args.tiling_mode != obj_priv->tiling_mode) {
310 311 int ret;
311 312
312 313 /* Unbind the object, as switching tiling means we're
313 314 * switching the cache organization due to fencing, probably.
314 315 */
315 316 ret = i915_gem_object_unbind(obj, 1);
316 317 if (ret != 0) {
317 318 args.tiling_mode = obj_priv->tiling_mode;
318 319 spin_unlock(&dev->struct_mutex);
319 320 drm_gem_object_unreference(obj);
320 321 DRM_ERROR("tiling switch!! unbind error %d", ret);
321 322 return ret;
322 323 }
323 324 obj_priv->tiling_mode = args.tiling_mode;
324 325 }
325 326 obj_priv->stride = args.stride;
326 327
327 328 ret = DRM_COPY_TO_USER((struct drm_i915_gem_set_tiling __user *) data, &args, sizeof(args));
328 329 if ( ret != 0)
329 330 DRM_ERROR(" gem set tiling error! %d", ret);
330 331
331 332 drm_gem_object_unreference(obj);
332 333 spin_unlock(&dev->struct_mutex);
333 334
334 335 return 0;
335 336 }
336 337
337 338 /**
338 339 * Returns the current tiling mode and required bit 6 swizzling for the object.
339 340 */
340 341 /*ARGSUSED*/
341 342 int
342 343 i915_gem_get_tiling(DRM_IOCTL_ARGS)
343 344 {
344 345 DRM_DEVICE;
345 346 struct drm_i915_gem_get_tiling args;
346 347 drm_i915_private_t *dev_priv = dev->dev_private;
347 348 struct drm_gem_object *obj;
348 349 struct drm_i915_gem_object *obj_priv;
349 350 int ret;
350 351
351 352 if (dev->driver->use_gem != 1)
352 353 return ENODEV;
353 354
354 355 DRM_COPYFROM_WITH_RETURN(&args,
355 356 (struct drm_i915_gem_get_tiling __user *) data, sizeof(args));
356 357
357 358 obj = drm_gem_object_lookup(fpriv, args.handle);
358 359 if (obj == NULL)
359 360 return EINVAL;
360 361 obj_priv = obj->driver_private;
361 362
362 363 spin_lock(&dev->struct_mutex);
363 364
364 365 args.tiling_mode = obj_priv->tiling_mode;
365 366 switch (obj_priv->tiling_mode) {
366 367 case I915_TILING_X:
367 368 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
368 369 break;
369 370 case I915_TILING_Y:
370 371 args.swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
371 372 break;
372 373 case I915_TILING_NONE:
373 374 args.swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
374 375 break;
375 376 default:
376 377 DRM_ERROR("unknown tiling mode\n");
377 378 }
378 379
379 380
380 381
381 382 ret = DRM_COPY_TO_USER((struct drm_i915_gem_get_tiling __user *) data, &args, sizeof(args));
382 383 if ( ret != 0)
383 384 DRM_ERROR(" gem get tiling error! %d", ret);
384 385
385 386 drm_gem_object_unreference(obj);
386 387 spin_unlock(&dev->struct_mutex);
387 388
388 389 return 0;
389 390 }
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