Print this page
5255 uts shouldn't open-code ISP2

Split Close
Expand all
Collapse all
          --- old/usr/src/uts/intel/io/drm/i915_gem_tiling.c
          +++ new/usr/src/uts/intel/io/drm/i915_gem_tiling.c
↓ open down ↓ 25 lines elided ↑ open up ↑
  26   26   * Authors:
  27   27   *    Eric Anholt <eric@anholt.net>
  28   28   *
  29   29   */
  30   30  
  31   31  /*
  32   32   * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  33   33   * Use is subject to license terms.
  34   34   */
  35   35  
       36 +#include <sys/sysmacros.h>
  36   37  #include "drmP.h"
  37   38  #include "drm.h"
  38   39  #include "i915_drm.h"
  39   40  #include "i915_drv.h"
  40   41  
  41   42  /** @file i915_gem_tiling.c
  42   43   *
  43   44   * Support for managing tiling state of buffer objects.
  44   45   *
  45   46   * The idea behind tiling is to increase cache hit rates by rearranging
↓ open down ↓ 193 lines elided ↑ open up ↑
 239  240          if (IS_I965G(dev)) {
 240  241                  if (stride & (tile_width - 1))
 241  242                          return 0;
 242  243                  return 1;
 243  244          }
 244  245  
 245  246          /* Pre-965 needs power of two tile widths */
 246  247          if (stride < tile_width)
 247  248                  return 0;
 248  249  
 249      -        if (stride & (stride - 1))
      250 +        if (!ISP2(stride))
 250  251                  return 0;
 251  252  
 252  253          /* We don't handle the aperture area covered by the fence being bigger
 253  254           * than the object size.
 254  255           */
 255  256          if (i915_get_fence_size(dev, size) != size)
 256  257                  return 0;
 257  258  
 258  259          return 1;
 259  260  }
↓ open down ↓ 130 lines elided ↑ open up ↑
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX