984 if (devaccp != NULL) {
985 if (devaccp->devacc_attr_endian_flags == DDI_STRUCTURE_LE_ACC) {
986 *hataccp &= ~HAT_ENDIAN_MASK;
987 *hataccp |= HAT_STRUCTURE_LE;
988 }
989 }
990 }
991
992 /*
993 * Check if the specified cache attribute is supported on the platform.
994 * This function must be called before i_ddi_cacheattr_to_hatacc().
995 */
996 boolean_t
997 i_ddi_check_cache_attr(uint_t flags)
998 {
999 /*
1000 * The cache attributes are mutually exclusive. Any combination of
1001 * the attributes leads to a failure.
1002 */
1003 uint_t cache_attr = IOMEM_CACHE_ATTR(flags);
1004 if ((cache_attr != 0) && ((cache_attr & (cache_attr - 1)) != 0))
1005 return (B_FALSE);
1006
1007 /*
1008 * On the sparc architecture, only IOMEM_DATA_CACHED is meaningful,
1009 * but others lead to a failure.
1010 */
1011 if (cache_attr & IOMEM_DATA_CACHED)
1012 return (B_TRUE);
1013 else
1014 return (B_FALSE);
1015 }
1016
1017 /* set HAT cache attributes from the cache attributes */
1018 void
1019 i_ddi_cacheattr_to_hatacc(uint_t flags, uint_t *hataccp)
1020 {
1021 uint_t cache_attr = IOMEM_CACHE_ATTR(flags);
1022 static char *fname = "i_ddi_cacheattr_to_hatacc";
1023 #if defined(lint)
1024 *hataccp = *hataccp;
1126 size_t *saddr = addr;
1127
1128 if (saddr[-3] == DDI_STRUCTURE_LE_ACC)
1129 vmem_free(little_endian_arena, (void *)saddr[-2], saddr[-1]);
1130 else
1131 vmem_free(big_endian_arena, (void *)saddr[-2], saddr[-1]);
1132 }
1133
1134 /*
1135 * This used to be ddi_iomin, but we were the only remaining caller, so
1136 * we've made it private and moved it here.
1137 */
1138 static int
1139 i_ddi_iomin(dev_info_t *a, int i, int stream)
1140 {
1141 int r;
1142
1143 /*
1144 * Make sure that the initial value is sane
1145 */
1146 if (i & (i - 1))
1147 return (0);
1148 if (i == 0)
1149 i = (stream) ? 4 : 1;
1150
1151 r = ddi_ctlops(a, a,
1152 DDI_CTLOPS_IOMIN, (void *)(uintptr_t)stream, (void *)&i);
1153 if (r != DDI_SUCCESS || (i & (i - 1)))
1154 return (0);
1155 return (i);
1156 }
1157
1158 int
1159 i_ddi_mem_alloc(dev_info_t *dip, ddi_dma_attr_t *attr,
1160 size_t length, int cansleep, int flags,
1161 ddi_device_acc_attr_t *accattrp,
1162 caddr_t *kaddrp, size_t *real_length, ddi_acc_hdl_t *handlep)
1163 {
1164 caddr_t a;
1165 int iomin, align, streaming;
1166 uint_t endian_flags = DDI_NEVERSWAP_ACC;
1167
1168 #if defined(lint)
1169 *handlep = *handlep;
1170 #endif
1171
1172 /*
1173 * Check legality of arguments
1174 */
1175 if (length == 0 || kaddrp == NULL || attr == NULL) {
1176 return (DDI_FAILURE);
1177 }
1178
1179 if (attr->dma_attr_minxfer == 0 || attr->dma_attr_align == 0 ||
1180 (attr->dma_attr_align & (attr->dma_attr_align - 1)) ||
1181 (attr->dma_attr_minxfer & (attr->dma_attr_minxfer - 1))) {
1182 return (DDI_FAILURE);
1183 }
1184
1185 /*
1186 * check if a streaming sequential xfer is requested.
1187 */
1188 streaming = (flags & DDI_DMA_STREAMING) ? 1 : 0;
1189
1190 /*
1191 * Drivers for 64-bit capable SBus devices will encode
1192 * the burtsizes for 64-bit xfers in the upper 16-bits.
1193 * For DMA alignment, we use the most restrictive
1194 * alignment of 32-bit and 64-bit xfers.
1195 */
1196 iomin = (attr->dma_attr_burstsizes & 0xffff) |
1197 ((attr->dma_attr_burstsizes >> 16) & 0xffff);
1198 /*
1199 * If a driver set burtsizes to 0, we give him byte alignment.
1200 * Otherwise align at the burtsizes boundary.
1201 */
|
984 if (devaccp != NULL) {
985 if (devaccp->devacc_attr_endian_flags == DDI_STRUCTURE_LE_ACC) {
986 *hataccp &= ~HAT_ENDIAN_MASK;
987 *hataccp |= HAT_STRUCTURE_LE;
988 }
989 }
990 }
991
992 /*
993 * Check if the specified cache attribute is supported on the platform.
994 * This function must be called before i_ddi_cacheattr_to_hatacc().
995 */
996 boolean_t
997 i_ddi_check_cache_attr(uint_t flags)
998 {
999 /*
1000 * The cache attributes are mutually exclusive. Any combination of
1001 * the attributes leads to a failure.
1002 */
1003 uint_t cache_attr = IOMEM_CACHE_ATTR(flags);
1004 if ((cache_attr != 0) && !ISP2(cache_attr))
1005 return (B_FALSE);
1006
1007 /*
1008 * On the sparc architecture, only IOMEM_DATA_CACHED is meaningful,
1009 * but others lead to a failure.
1010 */
1011 if (cache_attr & IOMEM_DATA_CACHED)
1012 return (B_TRUE);
1013 else
1014 return (B_FALSE);
1015 }
1016
1017 /* set HAT cache attributes from the cache attributes */
1018 void
1019 i_ddi_cacheattr_to_hatacc(uint_t flags, uint_t *hataccp)
1020 {
1021 uint_t cache_attr = IOMEM_CACHE_ATTR(flags);
1022 static char *fname = "i_ddi_cacheattr_to_hatacc";
1023 #if defined(lint)
1024 *hataccp = *hataccp;
1126 size_t *saddr = addr;
1127
1128 if (saddr[-3] == DDI_STRUCTURE_LE_ACC)
1129 vmem_free(little_endian_arena, (void *)saddr[-2], saddr[-1]);
1130 else
1131 vmem_free(big_endian_arena, (void *)saddr[-2], saddr[-1]);
1132 }
1133
1134 /*
1135 * This used to be ddi_iomin, but we were the only remaining caller, so
1136 * we've made it private and moved it here.
1137 */
1138 static int
1139 i_ddi_iomin(dev_info_t *a, int i, int stream)
1140 {
1141 int r;
1142
1143 /*
1144 * Make sure that the initial value is sane
1145 */
1146 if (!ISP2(i))
1147 return (0);
1148 if (i == 0)
1149 i = (stream) ? 4 : 1;
1150
1151 r = ddi_ctlops(a, a,
1152 DDI_CTLOPS_IOMIN, (void *)(uintptr_t)stream, (void *)&i);
1153 if (r != DDI_SUCCESS || !ISP2(i))
1154 return (0);
1155 return (i);
1156 }
1157
1158 int
1159 i_ddi_mem_alloc(dev_info_t *dip, ddi_dma_attr_t *attr,
1160 size_t length, int cansleep, int flags,
1161 ddi_device_acc_attr_t *accattrp,
1162 caddr_t *kaddrp, size_t *real_length, ddi_acc_hdl_t *handlep)
1163 {
1164 caddr_t a;
1165 int iomin, align, streaming;
1166 uint_t endian_flags = DDI_NEVERSWAP_ACC;
1167
1168 #if defined(lint)
1169 *handlep = *handlep;
1170 #endif
1171
1172 /*
1173 * Check legality of arguments
1174 */
1175 if (length == 0 || kaddrp == NULL || attr == NULL) {
1176 return (DDI_FAILURE);
1177 }
1178
1179 if (attr->dma_attr_minxfer == 0 || attr->dma_attr_align == 0 ||
1180 !ISP2(attr->dma_attr_align) || !ISP2(attr->dma_attr_minxfer)) {
1181 return (DDI_FAILURE);
1182 }
1183
1184 /*
1185 * check if a streaming sequential xfer is requested.
1186 */
1187 streaming = (flags & DDI_DMA_STREAMING) ? 1 : 0;
1188
1189 /*
1190 * Drivers for 64-bit capable SBus devices will encode
1191 * the burtsizes for 64-bit xfers in the upper 16-bits.
1192 * For DMA alignment, we use the most restrictive
1193 * alignment of 32-bit and 64-bit xfers.
1194 */
1195 iomin = (attr->dma_attr_burstsizes & 0xffff) |
1196 ((attr->dma_attr_burstsizes >> 16) & 0xffff);
1197 /*
1198 * If a driver set burtsizes to 0, we give him byte alignment.
1199 * Otherwise align at the burtsizes boundary.
1200 */
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