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--- old/usr/src/uts/i86pc/vm/hat_i86.c
+++ new/usr/src/uts/i86pc/vm/hat_i86.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24 /*
25 25 * Copyright (c) 2010, Intel Corporation.
26 26 * All rights reserved.
27 27 */
28 28 /*
29 29 * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
30 30 * Copyright (c) 2014, 2015 by Delphix. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * VM - Hardware Address Translation management for i386 and amd64
35 35 *
36 36 * Implementation of the interfaces described in <common/vm/hat.h>
37 37 *
38 38 * Nearly all the details of how the hardware is managed should not be
39 39 * visible outside this layer except for misc. machine specific functions
40 40 * that work in conjunction with this code.
41 41 *
42 42 * Routines used only inside of i86pc/vm start with hati_ for HAT Internal.
43 43 */
44 44
45 45 #include <sys/machparam.h>
46 46 #include <sys/machsystm.h>
47 47 #include <sys/mman.h>
48 48 #include <sys/types.h>
49 49 #include <sys/systm.h>
50 50 #include <sys/cpuvar.h>
51 51 #include <sys/thread.h>
52 52 #include <sys/proc.h>
53 53 #include <sys/cpu.h>
54 54 #include <sys/kmem.h>
55 55 #include <sys/disp.h>
56 56 #include <sys/shm.h>
57 57 #include <sys/sysmacros.h>
58 58 #include <sys/machparam.h>
59 59 #include <sys/vmem.h>
60 60 #include <sys/vmsystm.h>
61 61 #include <sys/promif.h>
62 62 #include <sys/var.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/atomic.h>
65 65 #include <sys/bitmap.h>
66 66 #include <sys/controlregs.h>
67 67 #include <sys/bootconf.h>
68 68 #include <sys/bootsvcs.h>
69 69 #include <sys/bootinfo.h>
70 70 #include <sys/archsystm.h>
71 71
72 72 #include <vm/seg_kmem.h>
73 73 #include <vm/hat_i86.h>
74 74 #include <vm/as.h>
75 75 #include <vm/seg.h>
76 76 #include <vm/page.h>
77 77 #include <vm/seg_kp.h>
78 78 #include <vm/seg_kpm.h>
79 79 #include <vm/vm_dep.h>
80 80 #ifdef __xpv
81 81 #include <sys/hypervisor.h>
82 82 #endif
83 83 #include <vm/kboot_mmu.h>
84 84 #include <vm/seg_spt.h>
85 85
86 86 #include <sys/cmn_err.h>
87 87
88 88 /*
89 89 * Basic parameters for hat operation.
90 90 */
91 91 struct hat_mmu_info mmu;
92 92
93 93 /*
94 94 * The page that is the kernel's top level pagetable.
95 95 *
96 96 * For 32 bit PAE support on i86pc, the kernel hat will use the 1st 4 entries
97 97 * on this 4K page for its top level page table. The remaining groups of
98 98 * 4 entries are used for per processor copies of user VLP pagetables for
99 99 * running threads. See hat_switch() and reload_pae32() for details.
100 100 *
101 101 * vlp_page[0..3] - level==2 PTEs for kernel HAT
102 102 * vlp_page[4..7] - level==2 PTEs for user thread on cpu 0
103 103 * vlp_page[8..11] - level==2 PTE for user thread on cpu 1
104 104 * etc...
105 105 */
106 106 static x86pte_t *vlp_page;
107 107
108 108 /*
109 109 * forward declaration of internal utility routines
110 110 */
111 111 static x86pte_t hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected,
112 112 x86pte_t new);
113 113
114 114 /*
115 115 * The kernel address space exists in all HATs. To implement this the
116 116 * kernel reserves a fixed number of entries in the topmost level(s) of page
117 117 * tables. The values are setup during startup and then copied to every user
118 118 * hat created by hat_alloc(). This means that kernelbase must be:
119 119 *
120 120 * 4Meg aligned for 32 bit kernels
121 121 * 512Gig aligned for x86_64 64 bit kernel
122 122 *
123 123 * The hat_kernel_range_ts describe what needs to be copied from kernel hat
124 124 * to each user hat.
125 125 */
126 126 typedef struct hat_kernel_range {
127 127 level_t hkr_level;
128 128 uintptr_t hkr_start_va;
129 129 uintptr_t hkr_end_va; /* zero means to end of memory */
130 130 } hat_kernel_range_t;
131 131 #define NUM_KERNEL_RANGE 2
132 132 static hat_kernel_range_t kernel_ranges[NUM_KERNEL_RANGE];
133 133 static int num_kernel_ranges;
134 134
135 135 uint_t use_boot_reserve = 1; /* cleared after early boot process */
136 136 uint_t can_steal_post_boot = 0; /* set late in boot to enable stealing */
137 137
138 138 /*
139 139 * enable_1gpg: controls 1g page support for user applications.
140 140 * By default, 1g pages are exported to user applications. enable_1gpg can
141 141 * be set to 0 to not export.
142 142 */
143 143 int enable_1gpg = 1;
144 144
145 145 /*
146 146 * AMD shanghai processors provide better management of 1gb ptes in its tlb.
147 147 * By default, 1g page support will be disabled for pre-shanghai AMD
148 148 * processors that don't have optimal tlb support for the 1g page size.
149 149 * chk_optimal_1gtlb can be set to 0 to force 1g page support on sub-optimal
150 150 * processors.
151 151 */
152 152 int chk_optimal_1gtlb = 1;
153 153
154 154
155 155 #ifdef DEBUG
156 156 uint_t map1gcnt;
157 157 #endif
158 158
159 159
160 160 /*
161 161 * A cpuset for all cpus. This is used for kernel address cross calls, since
162 162 * the kernel addresses apply to all cpus.
163 163 */
164 164 cpuset_t khat_cpuset;
165 165
166 166 /*
167 167 * management stuff for hat structures
168 168 */
169 169 kmutex_t hat_list_lock;
170 170 kcondvar_t hat_list_cv;
171 171 kmem_cache_t *hat_cache;
172 172 kmem_cache_t *hat_hash_cache;
173 173 kmem_cache_t *vlp_hash_cache;
174 174
175 175 /*
176 176 * Simple statistics
177 177 */
178 178 struct hatstats hatstat;
179 179
180 180 /*
181 181 * Some earlier hypervisor versions do not emulate cmpxchg of PTEs
182 182 * correctly. For such hypervisors we must set PT_USER for kernel
183 183 * entries ourselves (normally the emulation would set PT_USER for
184 184 * kernel entries and PT_USER|PT_GLOBAL for user entries). pt_kern is
185 185 * thus set appropriately. Note that dboot/kbm is OK, as only the full
186 186 * HAT uses cmpxchg() and the other paths (hypercall etc.) were never
187 187 * incorrect.
188 188 */
189 189 int pt_kern;
190 190
191 191 /*
192 192 * useful stuff for atomic access/clearing/setting REF/MOD/RO bits in page_t's.
193 193 */
194 194 extern void atomic_orb(uchar_t *addr, uchar_t val);
195 195 extern void atomic_andb(uchar_t *addr, uchar_t val);
196 196
197 197 #ifndef __xpv
198 198 extern pfn_t memseg_get_start(struct memseg *);
199 199 #endif
200 200
201 201 #define PP_GETRM(pp, rmmask) (pp->p_nrm & rmmask)
202 202 #define PP_ISMOD(pp) PP_GETRM(pp, P_MOD)
203 203 #define PP_ISREF(pp) PP_GETRM(pp, P_REF)
204 204 #define PP_ISRO(pp) PP_GETRM(pp, P_RO)
205 205
206 206 #define PP_SETRM(pp, rm) atomic_orb(&(pp->p_nrm), rm)
207 207 #define PP_SETMOD(pp) PP_SETRM(pp, P_MOD)
208 208 #define PP_SETREF(pp) PP_SETRM(pp, P_REF)
209 209 #define PP_SETRO(pp) PP_SETRM(pp, P_RO)
210 210
211 211 #define PP_CLRRM(pp, rm) atomic_andb(&(pp->p_nrm), ~(rm))
212 212 #define PP_CLRMOD(pp) PP_CLRRM(pp, P_MOD)
213 213 #define PP_CLRREF(pp) PP_CLRRM(pp, P_REF)
214 214 #define PP_CLRRO(pp) PP_CLRRM(pp, P_RO)
215 215 #define PP_CLRALL(pp) PP_CLRRM(pp, P_MOD | P_REF | P_RO)
216 216
217 217 /*
218 218 * kmem cache constructor for struct hat
219 219 */
220 220 /*ARGSUSED*/
221 221 static int
222 222 hati_constructor(void *buf, void *handle, int kmflags)
223 223 {
224 224 hat_t *hat = buf;
225 225
226 226 mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
227 227 bzero(hat->hat_pages_mapped,
228 228 sizeof (pgcnt_t) * (mmu.max_page_level + 1));
229 229 hat->hat_ism_pgcnt = 0;
230 230 hat->hat_stats = 0;
231 231 hat->hat_flags = 0;
232 232 CPUSET_ZERO(hat->hat_cpus);
233 233 hat->hat_htable = NULL;
234 234 hat->hat_ht_hash = NULL;
235 235 return (0);
236 236 }
237 237
238 238 /*
239 239 * Allocate a hat structure for as. We also create the top level
240 240 * htable and initialize it to contain the kernel hat entries.
241 241 */
242 242 hat_t *
243 243 hat_alloc(struct as *as)
244 244 {
245 245 hat_t *hat;
246 246 htable_t *ht; /* top level htable */
247 247 uint_t use_vlp;
248 248 uint_t r;
249 249 hat_kernel_range_t *rp;
250 250 uintptr_t va;
251 251 uintptr_t eva;
252 252 uint_t start;
253 253 uint_t cnt;
254 254 htable_t *src;
255 255
256 256 /*
257 257 * Once we start creating user process HATs we can enable
258 258 * the htable_steal() code.
259 259 */
260 260 if (can_steal_post_boot == 0)
261 261 can_steal_post_boot = 1;
262 262
263 263 ASSERT(AS_WRITE_HELD(as));
264 264 hat = kmem_cache_alloc(hat_cache, KM_SLEEP);
265 265 hat->hat_as = as;
266 266 mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
267 267 ASSERT(hat->hat_flags == 0);
268 268
269 269 #if defined(__xpv)
270 270 /*
271 271 * No VLP stuff on the hypervisor due to the 64-bit split top level
272 272 * page tables. On 32-bit it's not needed as the hypervisor takes
273 273 * care of copying the top level PTEs to a below 4Gig page.
274 274 */
275 275 use_vlp = 0;
276 276 #else /* __xpv */
277 277 /* 32 bit processes uses a VLP style hat when running with PAE */
278 278 #if defined(__amd64)
279 279 use_vlp = (ttoproc(curthread)->p_model == DATAMODEL_ILP32);
280 280 #elif defined(__i386)
281 281 use_vlp = mmu.pae_hat;
282 282 #endif
283 283 #endif /* __xpv */
284 284 if (use_vlp) {
285 285 hat->hat_flags = HAT_VLP;
286 286 bzero(hat->hat_vlp_ptes, VLP_SIZE);
287 287 }
288 288
289 289 /*
290 290 * Allocate the htable hash
291 291 */
292 292 if ((hat->hat_flags & HAT_VLP)) {
293 293 hat->hat_num_hash = mmu.vlp_hash_cnt;
294 294 hat->hat_ht_hash = kmem_cache_alloc(vlp_hash_cache, KM_SLEEP);
295 295 } else {
296 296 hat->hat_num_hash = mmu.hash_cnt;
297 297 hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_SLEEP);
298 298 }
299 299 bzero(hat->hat_ht_hash, hat->hat_num_hash * sizeof (htable_t *));
300 300
301 301 /*
302 302 * Initialize Kernel HAT entries at the top of the top level page
303 303 * tables for the new hat.
304 304 */
305 305 hat->hat_htable = NULL;
306 306 hat->hat_ht_cached = NULL;
307 307 XPV_DISALLOW_MIGRATE();
308 308 ht = htable_create(hat, (uintptr_t)0, TOP_LEVEL(hat), NULL);
309 309 hat->hat_htable = ht;
310 310
311 311 #if defined(__amd64)
312 312 if (hat->hat_flags & HAT_VLP)
313 313 goto init_done;
314 314 #endif
315 315
316 316 for (r = 0; r < num_kernel_ranges; ++r) {
317 317 rp = &kernel_ranges[r];
318 318 for (va = rp->hkr_start_va; va != rp->hkr_end_va;
319 319 va += cnt * LEVEL_SIZE(rp->hkr_level)) {
320 320
321 321 if (rp->hkr_level == TOP_LEVEL(hat))
322 322 ht = hat->hat_htable;
323 323 else
324 324 ht = htable_create(hat, va, rp->hkr_level,
325 325 NULL);
326 326
327 327 start = htable_va2entry(va, ht);
328 328 cnt = HTABLE_NUM_PTES(ht) - start;
329 329 eva = va +
330 330 ((uintptr_t)cnt << LEVEL_SHIFT(rp->hkr_level));
331 331 if (rp->hkr_end_va != 0 &&
332 332 (eva > rp->hkr_end_va || eva == 0))
333 333 cnt = htable_va2entry(rp->hkr_end_va, ht) -
334 334 start;
335 335
336 336 #if defined(__i386) && !defined(__xpv)
337 337 if (ht->ht_flags & HTABLE_VLP) {
338 338 bcopy(&vlp_page[start],
339 339 &hat->hat_vlp_ptes[start],
340 340 cnt * sizeof (x86pte_t));
341 341 continue;
342 342 }
343 343 #endif
344 344 src = htable_lookup(kas.a_hat, va, rp->hkr_level);
345 345 ASSERT(src != NULL);
346 346 x86pte_copy(src, ht, start, cnt);
347 347 htable_release(src);
348 348 }
349 349 }
350 350
351 351 init_done:
352 352
353 353 #if defined(__xpv)
354 354 /*
355 355 * Pin top level page tables after initializing them
356 356 */
357 357 xen_pin(hat->hat_htable->ht_pfn, mmu.max_level);
358 358 #if defined(__amd64)
359 359 xen_pin(hat->hat_user_ptable, mmu.max_level);
360 360 #endif
361 361 #endif
362 362 XPV_ALLOW_MIGRATE();
363 363
364 364 /*
365 365 * Put it at the start of the global list of all hats (used by stealing)
366 366 *
367 367 * kas.a_hat is not in the list but is instead used to find the
368 368 * first and last items in the list.
369 369 *
370 370 * - kas.a_hat->hat_next points to the start of the user hats.
371 371 * The list ends where hat->hat_next == NULL
372 372 *
373 373 * - kas.a_hat->hat_prev points to the last of the user hats.
374 374 * The list begins where hat->hat_prev == NULL
375 375 */
376 376 mutex_enter(&hat_list_lock);
377 377 hat->hat_prev = NULL;
378 378 hat->hat_next = kas.a_hat->hat_next;
379 379 if (hat->hat_next)
380 380 hat->hat_next->hat_prev = hat;
381 381 else
382 382 kas.a_hat->hat_prev = hat;
383 383 kas.a_hat->hat_next = hat;
384 384 mutex_exit(&hat_list_lock);
385 385
386 386 return (hat);
387 387 }
388 388
389 389 /*
390 390 * process has finished executing but as has not been cleaned up yet.
391 391 */
392 392 /*ARGSUSED*/
393 393 void
394 394 hat_free_start(hat_t *hat)
395 395 {
396 396 ASSERT(AS_WRITE_HELD(hat->hat_as));
397 397
398 398 /*
399 399 * If the hat is currently a stealing victim, wait for the stealing
400 400 * to finish. Once we mark it as HAT_FREEING, htable_steal()
401 401 * won't look at its pagetables anymore.
402 402 */
403 403 mutex_enter(&hat_list_lock);
404 404 while (hat->hat_flags & HAT_VICTIM)
405 405 cv_wait(&hat_list_cv, &hat_list_lock);
406 406 hat->hat_flags |= HAT_FREEING;
407 407 mutex_exit(&hat_list_lock);
408 408 }
409 409
410 410 /*
411 411 * An address space is being destroyed, so we destroy the associated hat.
412 412 */
413 413 void
414 414 hat_free_end(hat_t *hat)
415 415 {
416 416 kmem_cache_t *cache;
417 417
418 418 ASSERT(hat->hat_flags & HAT_FREEING);
419 419
420 420 /*
421 421 * must not be running on the given hat
422 422 */
423 423 ASSERT(CPU->cpu_current_hat != hat);
424 424
425 425 /*
426 426 * Remove it from the list of HATs
427 427 */
428 428 mutex_enter(&hat_list_lock);
429 429 if (hat->hat_prev)
430 430 hat->hat_prev->hat_next = hat->hat_next;
431 431 else
432 432 kas.a_hat->hat_next = hat->hat_next;
433 433 if (hat->hat_next)
434 434 hat->hat_next->hat_prev = hat->hat_prev;
435 435 else
436 436 kas.a_hat->hat_prev = hat->hat_prev;
437 437 mutex_exit(&hat_list_lock);
438 438 hat->hat_next = hat->hat_prev = NULL;
439 439
440 440 #if defined(__xpv)
441 441 /*
442 442 * On the hypervisor, unpin top level page table(s)
443 443 */
444 444 xen_unpin(hat->hat_htable->ht_pfn);
445 445 #if defined(__amd64)
446 446 xen_unpin(hat->hat_user_ptable);
447 447 #endif
448 448 #endif
449 449
450 450 /*
451 451 * Make a pass through the htables freeing them all up.
452 452 */
453 453 htable_purge_hat(hat);
454 454
455 455 /*
456 456 * Decide which kmem cache the hash table came from, then free it.
457 457 */
458 458 if (hat->hat_flags & HAT_VLP)
459 459 cache = vlp_hash_cache;
460 460 else
461 461 cache = hat_hash_cache;
462 462 kmem_cache_free(cache, hat->hat_ht_hash);
463 463 hat->hat_ht_hash = NULL;
464 464
465 465 hat->hat_flags = 0;
466 466 kmem_cache_free(hat_cache, hat);
467 467 }
468 468
469 469 /*
470 470 * round kernelbase down to a supported value to use for _userlimit
471 471 *
472 472 * userlimit must be aligned down to an entry in the top level htable.
473 473 * The one exception is for 32 bit HAT's running PAE.
474 474 */
475 475 uintptr_t
476 476 hat_kernelbase(uintptr_t va)
477 477 {
478 478 #if defined(__i386)
479 479 va &= LEVEL_MASK(1);
480 480 #endif
481 481 if (IN_VA_HOLE(va))
482 482 panic("_userlimit %p will fall in VA hole\n", (void *)va);
483 483 return (va);
484 484 }
485 485
486 486 /*
487 487 *
488 488 */
489 489 static void
490 490 set_max_page_level()
491 491 {
492 492 level_t lvl;
493 493
494 494 if (!kbm_largepage_support) {
495 495 lvl = 0;
496 496 } else {
497 497 if (is_x86_feature(x86_featureset, X86FSET_1GPG)) {
498 498 lvl = 2;
499 499 if (chk_optimal_1gtlb &&
500 500 cpuid_opteron_erratum(CPU, 6671130)) {
501 501 lvl = 1;
502 502 }
503 503 if (plat_mnode_xcheck(LEVEL_SIZE(2) >>
504 504 LEVEL_SHIFT(0))) {
505 505 lvl = 1;
506 506 }
507 507 } else {
508 508 lvl = 1;
509 509 }
510 510 }
511 511 mmu.max_page_level = lvl;
512 512
513 513 if ((lvl == 2) && (enable_1gpg == 0))
514 514 mmu.umax_page_level = 1;
515 515 else
516 516 mmu.umax_page_level = lvl;
517 517 }
518 518
519 519 /*
520 520 * Initialize hat data structures based on processor MMU information.
521 521 */
522 522 void
523 523 mmu_init(void)
524 524 {
525 525 uint_t max_htables;
526 526 uint_t pa_bits;
527 527 uint_t va_bits;
528 528 int i;
529 529
530 530 /*
531 531 * If CPU enabled the page table global bit, use it for the kernel
532 532 * This is bit 7 in CR4 (PGE - Page Global Enable).
533 533 */
534 534 if (is_x86_feature(x86_featureset, X86FSET_PGE) &&
535 535 (getcr4() & CR4_PGE) != 0)
536 536 mmu.pt_global = PT_GLOBAL;
537 537
538 538 /*
539 539 * Detect NX and PAE usage.
540 540 */
541 541 mmu.pae_hat = kbm_pae_support;
542 542 if (kbm_nx_support)
543 543 mmu.pt_nx = PT_NX;
544 544 else
545 545 mmu.pt_nx = 0;
546 546
547 547 /*
548 548 * Use CPU info to set various MMU parameters
549 549 */
550 550 cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
551 551
552 552 if (va_bits < sizeof (void *) * NBBY) {
553 553 mmu.hole_start = (1ul << (va_bits - 1));
554 554 mmu.hole_end = 0ul - mmu.hole_start - 1;
555 555 } else {
556 556 mmu.hole_end = 0;
557 557 mmu.hole_start = mmu.hole_end - 1;
558 558 }
559 559 #if defined(OPTERON_ERRATUM_121)
560 560 /*
561 561 * If erratum 121 has already been detected at this time, hole_start
562 562 * contains the value to be subtracted from mmu.hole_start.
563 563 */
564 564 ASSERT(hole_start == 0 || opteron_erratum_121 != 0);
565 565 hole_start = mmu.hole_start - hole_start;
566 566 #else
567 567 hole_start = mmu.hole_start;
568 568 #endif
569 569 hole_end = mmu.hole_end;
570 570
571 571 mmu.highest_pfn = mmu_btop((1ull << pa_bits) - 1);
572 572 if (mmu.pae_hat == 0 && pa_bits > 32)
573 573 mmu.highest_pfn = PFN_4G - 1;
574 574
575 575 if (mmu.pae_hat) {
576 576 mmu.pte_size = 8; /* 8 byte PTEs */
577 577 mmu.pte_size_shift = 3;
578 578 } else {
579 579 mmu.pte_size = 4; /* 4 byte PTEs */
580 580 mmu.pte_size_shift = 2;
581 581 }
582 582
583 583 if (mmu.pae_hat && !is_x86_feature(x86_featureset, X86FSET_PAE))
584 584 panic("Processor does not support PAE");
585 585
586 586 if (!is_x86_feature(x86_featureset, X86FSET_CX8))
587 587 panic("Processor does not support cmpxchg8b instruction");
588 588
589 589 #if defined(__amd64)
590 590
591 591 mmu.num_level = 4;
592 592 mmu.max_level = 3;
593 593 mmu.ptes_per_table = 512;
594 594 mmu.top_level_count = 512;
595 595
596 596 mmu.level_shift[0] = 12;
597 597 mmu.level_shift[1] = 21;
598 598 mmu.level_shift[2] = 30;
599 599 mmu.level_shift[3] = 39;
600 600
601 601 #elif defined(__i386)
602 602
603 603 if (mmu.pae_hat) {
604 604 mmu.num_level = 3;
605 605 mmu.max_level = 2;
606 606 mmu.ptes_per_table = 512;
607 607 mmu.top_level_count = 4;
608 608
609 609 mmu.level_shift[0] = 12;
610 610 mmu.level_shift[1] = 21;
611 611 mmu.level_shift[2] = 30;
612 612
613 613 } else {
614 614 mmu.num_level = 2;
615 615 mmu.max_level = 1;
616 616 mmu.ptes_per_table = 1024;
617 617 mmu.top_level_count = 1024;
618 618
619 619 mmu.level_shift[0] = 12;
620 620 mmu.level_shift[1] = 22;
621 621 }
622 622
623 623 #endif /* __i386 */
624 624
625 625 for (i = 0; i < mmu.num_level; ++i) {
626 626 mmu.level_size[i] = 1UL << mmu.level_shift[i];
627 627 mmu.level_offset[i] = mmu.level_size[i] - 1;
628 628 mmu.level_mask[i] = ~mmu.level_offset[i];
629 629 }
630 630
631 631 set_max_page_level();
632 632
633 633 mmu_page_sizes = mmu.max_page_level + 1;
634 634 mmu_exported_page_sizes = mmu.umax_page_level + 1;
635 635
636 636 /* restrict legacy applications from using pagesizes 1g and above */
637 637 mmu_legacy_page_sizes =
638 638 (mmu_exported_page_sizes > 2) ? 2 : mmu_exported_page_sizes;
639 639
640 640
641 641 for (i = 0; i <= mmu.max_page_level; ++i) {
642 642 mmu.pte_bits[i] = PT_VALID | pt_kern;
643 643 if (i > 0)
644 644 mmu.pte_bits[i] |= PT_PAGESIZE;
645 645 }
646 646
647 647 /*
648 648 * NOTE Legacy 32 bit PAE mode only has the P_VALID bit at top level.
649 649 */
650 650 for (i = 1; i < mmu.num_level; ++i)
651 651 mmu.ptp_bits[i] = PT_PTPBITS;
652 652
653 653 #if defined(__i386)
654 654 mmu.ptp_bits[2] = PT_VALID;
655 655 #endif
656 656
657 657 /*
658 658 * Compute how many hash table entries to have per process for htables.
659 659 * We start with 1 page's worth of entries.
660 660 *
661 661 * If physical memory is small, reduce the amount need to cover it.
662 662 */
663 663 max_htables = physmax / mmu.ptes_per_table;
664 664 mmu.hash_cnt = MMU_PAGESIZE / sizeof (htable_t *);
665 665 while (mmu.hash_cnt > 16 && mmu.hash_cnt >= max_htables)
666 666 mmu.hash_cnt >>= 1;
667 667 mmu.vlp_hash_cnt = mmu.hash_cnt;
668 668
669 669 #if defined(__amd64)
670 670 /*
671 671 * If running in 64 bits and physical memory is large,
672 672 * increase the size of the cache to cover all of memory for
673 673 * a 64 bit process.
674 674 */
675 675 #define HASH_MAX_LENGTH 4
676 676 while (mmu.hash_cnt * HASH_MAX_LENGTH < max_htables)
677 677 mmu.hash_cnt <<= 1;
678 678 #endif
679 679 }
680 680
681 681
682 682 /*
683 683 * initialize hat data structures
684 684 */
685 685 void
686 686 hat_init()
687 687 {
688 688 #if defined(__i386)
689 689 /*
690 690 * _userlimit must be aligned correctly
691 691 */
692 692 if ((_userlimit & LEVEL_MASK(1)) != _userlimit) {
693 693 prom_printf("hat_init(): _userlimit=%p, not aligned at %p\n",
694 694 (void *)_userlimit, (void *)LEVEL_SIZE(1));
695 695 halt("hat_init(): Unable to continue");
696 696 }
697 697 #endif
698 698
699 699 cv_init(&hat_list_cv, NULL, CV_DEFAULT, NULL);
700 700
701 701 /*
702 702 * initialize kmem caches
703 703 */
704 704 htable_init();
705 705 hment_init();
706 706
707 707 hat_cache = kmem_cache_create("hat_t",
708 708 sizeof (hat_t), 0, hati_constructor, NULL, NULL,
709 709 NULL, 0, 0);
710 710
711 711 hat_hash_cache = kmem_cache_create("HatHash",
712 712 mmu.hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
713 713 NULL, 0, 0);
714 714
715 715 /*
716 716 * VLP hats can use a smaller hash table size on large memroy machines
717 717 */
718 718 if (mmu.hash_cnt == mmu.vlp_hash_cnt) {
719 719 vlp_hash_cache = hat_hash_cache;
720 720 } else {
721 721 vlp_hash_cache = kmem_cache_create("HatVlpHash",
722 722 mmu.vlp_hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
723 723 NULL, 0, 0);
724 724 }
725 725
726 726 /*
727 727 * Set up the kernel's hat
728 728 */
729 729 AS_LOCK_ENTER(&kas, RW_WRITER);
730 730 kas.a_hat = kmem_cache_alloc(hat_cache, KM_NOSLEEP);
731 731 mutex_init(&kas.a_hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
732 732 kas.a_hat->hat_as = &kas;
733 733 kas.a_hat->hat_flags = 0;
734 734 AS_LOCK_EXIT(&kas);
735 735
736 736 CPUSET_ZERO(khat_cpuset);
737 737 CPUSET_ADD(khat_cpuset, CPU->cpu_id);
738 738
739 739 /*
740 740 * The kernel hat's next pointer serves as the head of the hat list .
741 741 * The kernel hat's prev pointer tracks the last hat on the list for
742 742 * htable_steal() to use.
743 743 */
744 744 kas.a_hat->hat_next = NULL;
745 745 kas.a_hat->hat_prev = NULL;
746 746
747 747 /*
748 748 * Allocate an htable hash bucket for the kernel
749 749 * XX64 - tune for 64 bit procs
750 750 */
751 751 kas.a_hat->hat_num_hash = mmu.hash_cnt;
752 752 kas.a_hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_NOSLEEP);
753 753 bzero(kas.a_hat->hat_ht_hash, mmu.hash_cnt * sizeof (htable_t *));
754 754
755 755 /*
756 756 * zero out the top level and cached htable pointers
757 757 */
758 758 kas.a_hat->hat_ht_cached = NULL;
759 759 kas.a_hat->hat_htable = NULL;
760 760
761 761 /*
762 762 * Pre-allocate hrm_hashtab before enabling the collection of
763 763 * refmod statistics. Allocating on the fly would mean us
764 764 * running the risk of suffering recursive mutex enters or
765 765 * deadlocks.
766 766 */
767 767 hrm_hashtab = kmem_zalloc(HRM_HASHSIZE * sizeof (struct hrmstat *),
768 768 KM_SLEEP);
769 769 }
770 770
771 771 /*
772 772 * Prepare CPU specific pagetables for VLP processes on 64 bit kernels.
773 773 *
774 774 * Each CPU has a set of 2 pagetables that are reused for any 32 bit
775 775 * process it runs. They are the top level pagetable, hci_vlp_l3ptes, and
776 776 * the next to top level table for the bottom 512 Gig, hci_vlp_l2ptes.
777 777 */
778 778 /*ARGSUSED*/
779 779 static void
780 780 hat_vlp_setup(struct cpu *cpu)
781 781 {
782 782 #if defined(__amd64) && !defined(__xpv)
783 783 struct hat_cpu_info *hci = cpu->cpu_hat_info;
784 784 pfn_t pfn;
785 785
786 786 /*
787 787 * allocate the level==2 page table for the bottom most
788 788 * 512Gig of address space (this is where 32 bit apps live)
789 789 */
790 790 ASSERT(hci != NULL);
791 791 hci->hci_vlp_l2ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP);
792 792
793 793 /*
794 794 * Allocate a top level pagetable and copy the kernel's
795 795 * entries into it. Then link in hci_vlp_l2ptes in the 1st entry.
796 796 */
797 797 hci->hci_vlp_l3ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP);
798 798 hci->hci_vlp_pfn =
799 799 hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l3ptes);
800 800 ASSERT(hci->hci_vlp_pfn != PFN_INVALID);
801 801 bcopy(vlp_page, hci->hci_vlp_l3ptes, MMU_PAGESIZE);
802 802
803 803 pfn = hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l2ptes);
804 804 ASSERT(pfn != PFN_INVALID);
805 805 hci->hci_vlp_l3ptes[0] = MAKEPTP(pfn, 2);
806 806 #endif /* __amd64 && !__xpv */
807 807 }
808 808
809 809 /*ARGSUSED*/
810 810 static void
811 811 hat_vlp_teardown(cpu_t *cpu)
812 812 {
813 813 #if defined(__amd64) && !defined(__xpv)
814 814 struct hat_cpu_info *hci;
815 815
816 816 if ((hci = cpu->cpu_hat_info) == NULL)
817 817 return;
818 818 if (hci->hci_vlp_l2ptes)
819 819 kmem_free(hci->hci_vlp_l2ptes, MMU_PAGESIZE);
820 820 if (hci->hci_vlp_l3ptes)
821 821 kmem_free(hci->hci_vlp_l3ptes, MMU_PAGESIZE);
822 822 #endif
823 823 }
824 824
825 825 #define NEXT_HKR(r, l, s, e) { \
826 826 kernel_ranges[r].hkr_level = l; \
827 827 kernel_ranges[r].hkr_start_va = s; \
828 828 kernel_ranges[r].hkr_end_va = e; \
829 829 ++r; \
830 830 }
831 831
832 832 /*
833 833 * Finish filling in the kernel hat.
834 834 * Pre fill in all top level kernel page table entries for the kernel's
835 835 * part of the address range. From this point on we can't use any new
836 836 * kernel large pages if they need PTE's at max_level
837 837 *
838 838 * create the kmap mappings.
839 839 */
840 840 void
841 841 hat_init_finish(void)
842 842 {
843 843 size_t size;
844 844 uint_t r = 0;
845 845 uintptr_t va;
846 846 hat_kernel_range_t *rp;
847 847
848 848
849 849 /*
850 850 * We are now effectively running on the kernel hat.
851 851 * Clearing use_boot_reserve shuts off using the pre-allocated boot
852 852 * reserve for all HAT allocations. From here on, the reserves are
853 853 * only used when avoiding recursion in kmem_alloc().
854 854 */
855 855 use_boot_reserve = 0;
856 856 htable_adjust_reserve();
857 857
858 858 /*
859 859 * User HATs are initialized with copies of all kernel mappings in
860 860 * higher level page tables. Ensure that those entries exist.
861 861 */
862 862 #if defined(__amd64)
863 863
864 864 NEXT_HKR(r, 3, kernelbase, 0);
865 865 #if defined(__xpv)
866 866 NEXT_HKR(r, 3, HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END);
867 867 #endif
868 868
869 869 #elif defined(__i386)
870 870
871 871 #if !defined(__xpv)
872 872 if (mmu.pae_hat) {
873 873 va = kernelbase;
874 874 if ((va & LEVEL_MASK(2)) != va) {
875 875 va = P2ROUNDUP(va, LEVEL_SIZE(2));
876 876 NEXT_HKR(r, 1, kernelbase, va);
877 877 }
878 878 if (va != 0)
879 879 NEXT_HKR(r, 2, va, 0);
880 880 } else
881 881 #endif /* __xpv */
882 882 NEXT_HKR(r, 1, kernelbase, 0);
883 883
884 884 #endif /* __i386 */
885 885
886 886 num_kernel_ranges = r;
887 887
888 888 /*
889 889 * Create all the kernel pagetables that will have entries
890 890 * shared to user HATs.
891 891 */
892 892 for (r = 0; r < num_kernel_ranges; ++r) {
893 893 rp = &kernel_ranges[r];
894 894 for (va = rp->hkr_start_va; va != rp->hkr_end_va;
895 895 va += LEVEL_SIZE(rp->hkr_level)) {
896 896 htable_t *ht;
897 897
898 898 if (IN_HYPERVISOR_VA(va))
899 899 continue;
900 900
901 901 /* can/must skip if a page mapping already exists */
902 902 if (rp->hkr_level <= mmu.max_page_level &&
903 903 (ht = htable_getpage(kas.a_hat, va, NULL)) !=
904 904 NULL) {
905 905 htable_release(ht);
906 906 continue;
907 907 }
908 908
909 909 (void) htable_create(kas.a_hat, va, rp->hkr_level - 1,
910 910 NULL);
911 911 }
912 912 }
913 913
914 914 /*
915 915 * 32 bit PAE metal kernels use only 4 of the 512 entries in the
916 916 * page holding the top level pagetable. We use the remainder for
917 917 * the "per CPU" page tables for VLP processes.
918 918 * Map the top level kernel pagetable into the kernel to make
919 919 * it easy to use bcopy access these tables.
920 920 */
921 921 if (mmu.pae_hat) {
922 922 vlp_page = vmem_alloc(heap_arena, MMU_PAGESIZE, VM_SLEEP);
923 923 hat_devload(kas.a_hat, (caddr_t)vlp_page, MMU_PAGESIZE,
924 924 kas.a_hat->hat_htable->ht_pfn,
925 925 #if !defined(__xpv)
926 926 PROT_WRITE |
927 927 #endif
928 928 PROT_READ | HAT_NOSYNC | HAT_UNORDERED_OK,
929 929 HAT_LOAD | HAT_LOAD_NOCONSIST);
930 930 }
931 931 hat_vlp_setup(CPU);
932 932
933 933 /*
934 934 * Create kmap (cached mappings of kernel PTEs)
935 935 * for 32 bit we map from segmap_start .. ekernelheap
936 936 * for 64 bit we map from segmap_start .. segmap_start + segmapsize;
937 937 */
938 938 #if defined(__i386)
939 939 size = (uintptr_t)ekernelheap - segmap_start;
940 940 #elif defined(__amd64)
941 941 size = segmapsize;
942 942 #endif
943 943 hat_kmap_init((uintptr_t)segmap_start, size);
944 944 }
945 945
946 946 /*
947 947 * On 32 bit PAE mode, PTE's are 64 bits, but ordinary atomic memory references
948 948 * are 32 bit, so for safety we must use atomic_cas_64() to install these.
949 949 */
950 950 #ifdef __i386
951 951 static void
952 952 reload_pae32(hat_t *hat, cpu_t *cpu)
953 953 {
954 954 x86pte_t *src;
955 955 x86pte_t *dest;
956 956 x86pte_t pte;
957 957 int i;
958 958
959 959 /*
960 960 * Load the 4 entries of the level 2 page table into this
961 961 * cpu's range of the vlp_page and point cr3 at them.
962 962 */
963 963 ASSERT(mmu.pae_hat);
964 964 src = hat->hat_vlp_ptes;
965 965 dest = vlp_page + (cpu->cpu_id + 1) * VLP_NUM_PTES;
966 966 for (i = 0; i < VLP_NUM_PTES; ++i) {
967 967 for (;;) {
968 968 pte = dest[i];
969 969 if (pte == src[i])
970 970 break;
971 971 if (atomic_cas_64(dest + i, pte, src[i]) != src[i])
972 972 break;
973 973 }
974 974 }
975 975 }
976 976 #endif
977 977
978 978 /*
979 979 * Switch to a new active hat, maintaining bit masks to track active CPUs.
980 980 *
981 981 * On the 32-bit PAE hypervisor, %cr3 is a 64-bit value, on metal it
982 982 * remains a 32-bit value.
983 983 */
984 984 void
985 985 hat_switch(hat_t *hat)
986 986 {
987 987 uint64_t newcr3;
988 988 cpu_t *cpu = CPU;
989 989 hat_t *old = cpu->cpu_current_hat;
990 990
991 991 /*
992 992 * set up this information first, so we don't miss any cross calls
993 993 */
994 994 if (old != NULL) {
995 995 if (old == hat)
996 996 return;
997 997 if (old != kas.a_hat)
998 998 CPUSET_ATOMIC_DEL(old->hat_cpus, cpu->cpu_id);
999 999 }
1000 1000
1001 1001 /*
1002 1002 * Add this CPU to the active set for this HAT.
1003 1003 */
1004 1004 if (hat != kas.a_hat) {
1005 1005 CPUSET_ATOMIC_ADD(hat->hat_cpus, cpu->cpu_id);
1006 1006 }
1007 1007 cpu->cpu_current_hat = hat;
1008 1008
1009 1009 /*
1010 1010 * now go ahead and load cr3
1011 1011 */
1012 1012 if (hat->hat_flags & HAT_VLP) {
1013 1013 #if defined(__amd64)
1014 1014 x86pte_t *vlpptep = cpu->cpu_hat_info->hci_vlp_l2ptes;
1015 1015
1016 1016 VLP_COPY(hat->hat_vlp_ptes, vlpptep);
1017 1017 newcr3 = MAKECR3(cpu->cpu_hat_info->hci_vlp_pfn);
1018 1018 #elif defined(__i386)
1019 1019 reload_pae32(hat, cpu);
1020 1020 newcr3 = MAKECR3(kas.a_hat->hat_htable->ht_pfn) +
1021 1021 (cpu->cpu_id + 1) * VLP_SIZE;
1022 1022 #endif
1023 1023 } else {
1024 1024 newcr3 = MAKECR3((uint64_t)hat->hat_htable->ht_pfn);
1025 1025 }
1026 1026 #ifdef __xpv
1027 1027 {
1028 1028 struct mmuext_op t[2];
1029 1029 uint_t retcnt;
1030 1030 uint_t opcnt = 1;
1031 1031
1032 1032 t[0].cmd = MMUEXT_NEW_BASEPTR;
1033 1033 t[0].arg1.mfn = mmu_btop(pa_to_ma(newcr3));
1034 1034 #if defined(__amd64)
1035 1035 /*
1036 1036 * There's an interesting problem here, as to what to
1037 1037 * actually specify when switching to the kernel hat.
1038 1038 * For now we'll reuse the kernel hat again.
1039 1039 */
1040 1040 t[1].cmd = MMUEXT_NEW_USER_BASEPTR;
1041 1041 if (hat == kas.a_hat)
1042 1042 t[1].arg1.mfn = mmu_btop(pa_to_ma(newcr3));
1043 1043 else
1044 1044 t[1].arg1.mfn = pfn_to_mfn(hat->hat_user_ptable);
1045 1045 ++opcnt;
1046 1046 #endif /* __amd64 */
1047 1047 if (HYPERVISOR_mmuext_op(t, opcnt, &retcnt, DOMID_SELF) < 0)
1048 1048 panic("HYPERVISOR_mmu_update() failed");
1049 1049 ASSERT(retcnt == opcnt);
1050 1050
1051 1051 }
1052 1052 #else
1053 1053 setcr3(newcr3);
1054 1054 #endif
1055 1055 ASSERT(cpu == CPU);
1056 1056 }
1057 1057
1058 1058 /*
1059 1059 * Utility to return a valid x86pte_t from protections, pfn, and level number
1060 1060 */
1061 1061 static x86pte_t
1062 1062 hati_mkpte(pfn_t pfn, uint_t attr, level_t level, uint_t flags)
1063 1063 {
1064 1064 x86pte_t pte;
1065 1065 uint_t cache_attr = attr & HAT_ORDER_MASK;
1066 1066
1067 1067 pte = MAKEPTE(pfn, level);
1068 1068
1069 1069 if (attr & PROT_WRITE)
1070 1070 PTE_SET(pte, PT_WRITABLE);
1071 1071
1072 1072 if (attr & PROT_USER)
1073 1073 PTE_SET(pte, PT_USER);
1074 1074
1075 1075 if (!(attr & PROT_EXEC))
1076 1076 PTE_SET(pte, mmu.pt_nx);
1077 1077
1078 1078 /*
1079 1079 * Set the software bits used track ref/mod sync's and hments.
1080 1080 * If not using REF/MOD, set them to avoid h/w rewriting PTEs.
1081 1081 */
1082 1082 if (flags & HAT_LOAD_NOCONSIST)
1083 1083 PTE_SET(pte, PT_NOCONSIST | PT_REF | PT_MOD);
1084 1084 else if (attr & HAT_NOSYNC)
1085 1085 PTE_SET(pte, PT_NOSYNC | PT_REF | PT_MOD);
1086 1086
1087 1087 /*
1088 1088 * Set the caching attributes in the PTE. The combination
1089 1089 * of attributes are poorly defined, so we pay attention
1090 1090 * to them in the given order.
1091 1091 *
1092 1092 * The test for HAT_STRICTORDER is different because it's defined
1093 1093 * as "0" - which was a stupid thing to do, but is too late to change!
1094 1094 */
1095 1095 if (cache_attr == HAT_STRICTORDER) {
1096 1096 PTE_SET(pte, PT_NOCACHE);
1097 1097 /*LINTED [Lint hates empty ifs, but it's the obvious way to do this] */
1098 1098 } else if (cache_attr & (HAT_UNORDERED_OK | HAT_STORECACHING_OK)) {
1099 1099 /* nothing to set */;
1100 1100 } else if (cache_attr & (HAT_MERGING_OK | HAT_LOADCACHING_OK)) {
1101 1101 PTE_SET(pte, PT_NOCACHE);
1102 1102 if (is_x86_feature(x86_featureset, X86FSET_PAT))
1103 1103 PTE_SET(pte, (level == 0) ? PT_PAT_4K : PT_PAT_LARGE);
1104 1104 else
1105 1105 PTE_SET(pte, PT_WRITETHRU);
1106 1106 } else {
1107 1107 panic("hati_mkpte(): bad caching attributes: %x\n", cache_attr);
1108 1108 }
1109 1109
1110 1110 return (pte);
1111 1111 }
1112 1112
1113 1113 /*
1114 1114 * Duplicate address translations of the parent to the child.
1115 1115 * This function really isn't used anymore.
1116 1116 */
1117 1117 /*ARGSUSED*/
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1117 lines elided |
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1118 1118 int
1119 1119 hat_dup(hat_t *old, hat_t *new, caddr_t addr, size_t len, uint_t flag)
1120 1120 {
1121 1121 ASSERT((uintptr_t)addr < kernelbase);
1122 1122 ASSERT(new != kas.a_hat);
1123 1123 ASSERT(old != kas.a_hat);
1124 1124 return (0);
1125 1125 }
1126 1126
1127 1127 /*
1128 - * Allocate any hat resources required for a process being swapped in.
1129 - */
1130 -/*ARGSUSED*/
1131 -void
1132 -hat_swapin(hat_t *hat)
1133 -{
1134 - /* do nothing - we let everything fault back in */
1135 -}
1136 -
1137 -/*
1138 - * Unload all translations associated with an address space of a process
1139 - * that is being swapped out.
1140 - */
1141 -void
1142 -hat_swapout(hat_t *hat)
1143 -{
1144 - uintptr_t vaddr = (uintptr_t)0;
1145 - uintptr_t eaddr = _userlimit;
1146 - htable_t *ht = NULL;
1147 - level_t l;
1148 -
1149 - XPV_DISALLOW_MIGRATE();
1150 - /*
1151 - * We can't just call hat_unload(hat, 0, _userlimit...) here, because
1152 - * seg_spt and shared pagetables can't be swapped out.
1153 - * Take a look at segspt_shmswapout() - it's a big no-op.
1154 - *
1155 - * Instead we'll walk through all the address space and unload
1156 - * any mappings which we are sure are not shared, not locked.
1157 - */
1158 - ASSERT(IS_PAGEALIGNED(vaddr));
1159 - ASSERT(IS_PAGEALIGNED(eaddr));
1160 - ASSERT(AS_LOCK_HELD(hat->hat_as));
1161 - if ((uintptr_t)hat->hat_as->a_userlimit < eaddr)
1162 - eaddr = (uintptr_t)hat->hat_as->a_userlimit;
1163 -
1164 - while (vaddr < eaddr) {
1165 - (void) htable_walk(hat, &ht, &vaddr, eaddr);
1166 - if (ht == NULL)
1167 - break;
1168 -
1169 - ASSERT(!IN_VA_HOLE(vaddr));
1170 -
1171 - /*
1172 - * If the page table is shared skip its entire range.
1173 - */
1174 - l = ht->ht_level;
1175 - if (ht->ht_flags & HTABLE_SHARED_PFN) {
1176 - vaddr = ht->ht_vaddr + LEVEL_SIZE(l + 1);
1177 - htable_release(ht);
1178 - ht = NULL;
1179 - continue;
1180 - }
1181 -
1182 - /*
1183 - * If the page table has no locked entries, unload this one.
1184 - */
1185 - if (ht->ht_lock_cnt == 0)
1186 - hat_unload(hat, (caddr_t)vaddr, LEVEL_SIZE(l),
1187 - HAT_UNLOAD_UNMAP);
1188 -
1189 - /*
1190 - * If we have a level 0 page table with locked entries,
1191 - * skip the entire page table, otherwise skip just one entry.
1192 - */
1193 - if (ht->ht_lock_cnt > 0 && l == 0)
1194 - vaddr = ht->ht_vaddr + LEVEL_SIZE(1);
1195 - else
1196 - vaddr += LEVEL_SIZE(l);
1197 - }
1198 - if (ht)
1199 - htable_release(ht);
1200 -
1201 - /*
1202 - * We're in swapout because the system is low on memory, so
1203 - * go back and flush all the htables off the cached list.
1204 - */
1205 - htable_purge_hat(hat);
1206 - XPV_ALLOW_MIGRATE();
1207 -}
1208 -
1209 -/*
1210 1128 * returns number of bytes that have valid mappings in hat.
1211 1129 */
1212 1130 size_t
1213 1131 hat_get_mapped_size(hat_t *hat)
1214 1132 {
1215 1133 size_t total = 0;
1216 1134 int l;
1217 1135
1218 1136 for (l = 0; l <= mmu.max_page_level; l++)
1219 1137 total += (hat->hat_pages_mapped[l] << LEVEL_SHIFT(l));
1220 1138 total += hat->hat_ism_pgcnt;
1221 1139
1222 1140 return (total);
1223 1141 }
1224 1142
1225 1143 /*
1226 1144 * enable/disable collection of stats for hat.
1227 1145 */
1228 1146 int
1229 1147 hat_stats_enable(hat_t *hat)
1230 1148 {
1231 1149 atomic_inc_32(&hat->hat_stats);
1232 1150 return (1);
1233 1151 }
1234 1152
1235 1153 void
1236 1154 hat_stats_disable(hat_t *hat)
1237 1155 {
1238 1156 atomic_dec_32(&hat->hat_stats);
1239 1157 }
1240 1158
1241 1159 /*
1242 1160 * Utility to sync the ref/mod bits from a page table entry to the page_t
1243 1161 * We must be holding the mapping list lock when this is called.
1244 1162 */
1245 1163 static void
1246 1164 hati_sync_pte_to_page(page_t *pp, x86pte_t pte, level_t level)
1247 1165 {
1248 1166 uint_t rm = 0;
1249 1167 pgcnt_t pgcnt;
1250 1168
1251 1169 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC)
1252 1170 return;
1253 1171
1254 1172 if (PTE_GET(pte, PT_REF))
1255 1173 rm |= P_REF;
1256 1174
1257 1175 if (PTE_GET(pte, PT_MOD))
1258 1176 rm |= P_MOD;
1259 1177
1260 1178 if (rm == 0)
1261 1179 return;
1262 1180
1263 1181 /*
1264 1182 * sync to all constituent pages of a large page
1265 1183 */
1266 1184 ASSERT(x86_hm_held(pp));
1267 1185 pgcnt = page_get_pagecnt(level);
1268 1186 ASSERT(IS_P2ALIGNED(pp->p_pagenum, pgcnt));
1269 1187 for (; pgcnt > 0; --pgcnt) {
1270 1188 /*
1271 1189 * hat_page_demote() can't decrease
1272 1190 * pszc below this mapping size
1273 1191 * since this large mapping existed after we
1274 1192 * took mlist lock.
1275 1193 */
1276 1194 ASSERT(pp->p_szc >= level);
1277 1195 hat_page_setattr(pp, rm);
1278 1196 ++pp;
1279 1197 }
1280 1198 }
1281 1199
1282 1200 /*
1283 1201 * This the set of PTE bits for PFN, permissions and caching
1284 1202 * that are allowed to change on a HAT_LOAD_REMAP
1285 1203 */
1286 1204 #define PT_REMAP_BITS \
1287 1205 (PT_PADDR | PT_NX | PT_WRITABLE | PT_WRITETHRU | \
1288 1206 PT_NOCACHE | PT_PAT_4K | PT_PAT_LARGE | PT_IGNORE | PT_REF | PT_MOD)
1289 1207
1290 1208 #define REMAPASSERT(EX) if (!(EX)) panic("hati_pte_map: " #EX)
1291 1209 /*
1292 1210 * Do the low-level work to get a mapping entered into a HAT's pagetables
1293 1211 * and in the mapping list of the associated page_t.
1294 1212 */
1295 1213 static int
1296 1214 hati_pte_map(
1297 1215 htable_t *ht,
1298 1216 uint_t entry,
1299 1217 page_t *pp,
1300 1218 x86pte_t pte,
1301 1219 int flags,
1302 1220 void *pte_ptr)
1303 1221 {
1304 1222 hat_t *hat = ht->ht_hat;
1305 1223 x86pte_t old_pte;
1306 1224 level_t l = ht->ht_level;
1307 1225 hment_t *hm;
1308 1226 uint_t is_consist;
1309 1227 uint_t is_locked;
1310 1228 int rv = 0;
1311 1229
1312 1230 /*
1313 1231 * Is this a consistent (ie. need mapping list lock) mapping?
1314 1232 */
1315 1233 is_consist = (pp != NULL && (flags & HAT_LOAD_NOCONSIST) == 0);
1316 1234
1317 1235 /*
1318 1236 * Track locked mapping count in the htable. Do this first,
1319 1237 * as we track locking even if there already is a mapping present.
1320 1238 */
1321 1239 is_locked = (flags & HAT_LOAD_LOCK) != 0 && hat != kas.a_hat;
1322 1240 if (is_locked)
1323 1241 HTABLE_LOCK_INC(ht);
1324 1242
1325 1243 /*
1326 1244 * Acquire the page's mapping list lock and get an hment to use.
1327 1245 * Note that hment_prepare() might return NULL.
1328 1246 */
1329 1247 if (is_consist) {
1330 1248 x86_hm_enter(pp);
1331 1249 hm = hment_prepare(ht, entry, pp);
1332 1250 }
1333 1251
1334 1252 /*
1335 1253 * Set the new pte, retrieving the old one at the same time.
1336 1254 */
1337 1255 old_pte = x86pte_set(ht, entry, pte, pte_ptr);
1338 1256
1339 1257 /*
1340 1258 * Did we get a large page / page table collision?
1341 1259 */
1342 1260 if (old_pte == LPAGE_ERROR) {
1343 1261 if (is_locked)
1344 1262 HTABLE_LOCK_DEC(ht);
1345 1263 rv = -1;
1346 1264 goto done;
1347 1265 }
1348 1266
1349 1267 /*
1350 1268 * If the mapping didn't change there is nothing more to do.
1351 1269 */
1352 1270 if (PTE_EQUIV(pte, old_pte))
1353 1271 goto done;
1354 1272
1355 1273 /*
1356 1274 * Install a new mapping in the page's mapping list
1357 1275 */
1358 1276 if (!PTE_ISVALID(old_pte)) {
1359 1277 if (is_consist) {
1360 1278 hment_assign(ht, entry, pp, hm);
1361 1279 x86_hm_exit(pp);
1362 1280 } else {
1363 1281 ASSERT(flags & HAT_LOAD_NOCONSIST);
1364 1282 }
1365 1283 #if defined(__amd64)
1366 1284 if (ht->ht_flags & HTABLE_VLP) {
1367 1285 cpu_t *cpu = CPU;
1368 1286 x86pte_t *vlpptep = cpu->cpu_hat_info->hci_vlp_l2ptes;
1369 1287 VLP_COPY(hat->hat_vlp_ptes, vlpptep);
1370 1288 }
1371 1289 #endif
1372 1290 HTABLE_INC(ht->ht_valid_cnt);
1373 1291 PGCNT_INC(hat, l);
1374 1292 return (rv);
1375 1293 }
1376 1294
1377 1295 /*
1378 1296 * Remap's are more complicated:
1379 1297 * - HAT_LOAD_REMAP must be specified if changing the pfn.
1380 1298 * We also require that NOCONSIST be specified.
1381 1299 * - Otherwise only permission or caching bits may change.
1382 1300 */
1383 1301 if (!PTE_ISPAGE(old_pte, l))
1384 1302 panic("non-null/page mapping pte=" FMT_PTE, old_pte);
1385 1303
1386 1304 if (PTE2PFN(old_pte, l) != PTE2PFN(pte, l)) {
1387 1305 REMAPASSERT(flags & HAT_LOAD_REMAP);
1388 1306 REMAPASSERT(flags & HAT_LOAD_NOCONSIST);
1389 1307 REMAPASSERT(PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST);
1390 1308 REMAPASSERT(pf_is_memory(PTE2PFN(old_pte, l)) ==
1391 1309 pf_is_memory(PTE2PFN(pte, l)));
1392 1310 REMAPASSERT(!is_consist);
1393 1311 }
1394 1312
1395 1313 /*
1396 1314 * We only let remaps change the certain bits in the PTE.
1397 1315 */
1398 1316 if (PTE_GET(old_pte, ~PT_REMAP_BITS) != PTE_GET(pte, ~PT_REMAP_BITS))
1399 1317 panic("remap bits changed: old_pte="FMT_PTE", pte="FMT_PTE"\n",
1400 1318 old_pte, pte);
1401 1319
1402 1320 /*
1403 1321 * We don't create any mapping list entries on a remap, so release
1404 1322 * any allocated hment after we drop the mapping list lock.
1405 1323 */
1406 1324 done:
1407 1325 if (is_consist) {
1408 1326 x86_hm_exit(pp);
1409 1327 if (hm != NULL)
1410 1328 hment_free(hm);
1411 1329 }
1412 1330 return (rv);
1413 1331 }
1414 1332
1415 1333 /*
1416 1334 * Internal routine to load a single page table entry. This only fails if
1417 1335 * we attempt to overwrite a page table link with a large page.
1418 1336 */
1419 1337 static int
1420 1338 hati_load_common(
1421 1339 hat_t *hat,
1422 1340 uintptr_t va,
1423 1341 page_t *pp,
1424 1342 uint_t attr,
1425 1343 uint_t flags,
1426 1344 level_t level,
1427 1345 pfn_t pfn)
1428 1346 {
1429 1347 htable_t *ht;
1430 1348 uint_t entry;
1431 1349 x86pte_t pte;
1432 1350 int rv = 0;
1433 1351
1434 1352 /*
1435 1353 * The number 16 is arbitrary and here to catch a recursion problem
1436 1354 * early before we blow out the kernel stack.
1437 1355 */
1438 1356 ++curthread->t_hatdepth;
1439 1357 ASSERT(curthread->t_hatdepth < 16);
1440 1358
1441 1359 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1442 1360
1443 1361 if (flags & HAT_LOAD_SHARE)
1444 1362 hat->hat_flags |= HAT_SHARED;
1445 1363
1446 1364 /*
1447 1365 * Find the page table that maps this page if it already exists.
1448 1366 */
1449 1367 ht = htable_lookup(hat, va, level);
1450 1368
1451 1369 /*
1452 1370 * We must have HAT_LOAD_NOCONSIST if page_t is NULL.
1453 1371 */
1454 1372 if (pp == NULL)
1455 1373 flags |= HAT_LOAD_NOCONSIST;
1456 1374
1457 1375 if (ht == NULL) {
1458 1376 ht = htable_create(hat, va, level, NULL);
1459 1377 ASSERT(ht != NULL);
1460 1378 }
1461 1379 entry = htable_va2entry(va, ht);
1462 1380
1463 1381 /*
1464 1382 * a bunch of paranoid error checking
1465 1383 */
1466 1384 ASSERT(ht->ht_busy > 0);
1467 1385 if (ht->ht_vaddr > va || va > HTABLE_LAST_PAGE(ht))
1468 1386 panic("hati_load_common: bad htable %p, va %p",
1469 1387 (void *)ht, (void *)va);
1470 1388 ASSERT(ht->ht_level == level);
1471 1389
1472 1390 /*
1473 1391 * construct the new PTE
1474 1392 */
1475 1393 if (hat == kas.a_hat)
1476 1394 attr &= ~PROT_USER;
1477 1395 pte = hati_mkpte(pfn, attr, level, flags);
1478 1396 if (hat == kas.a_hat && va >= kernelbase)
1479 1397 PTE_SET(pte, mmu.pt_global);
1480 1398
1481 1399 /*
1482 1400 * establish the mapping
1483 1401 */
1484 1402 rv = hati_pte_map(ht, entry, pp, pte, flags, NULL);
1485 1403
1486 1404 /*
1487 1405 * release the htable and any reserves
1488 1406 */
1489 1407 htable_release(ht);
1490 1408 --curthread->t_hatdepth;
1491 1409 return (rv);
1492 1410 }
1493 1411
1494 1412 /*
1495 1413 * special case of hat_memload to deal with some kernel addrs for performance
1496 1414 */
1497 1415 static void
1498 1416 hat_kmap_load(
1499 1417 caddr_t addr,
1500 1418 page_t *pp,
1501 1419 uint_t attr,
1502 1420 uint_t flags)
1503 1421 {
1504 1422 uintptr_t va = (uintptr_t)addr;
1505 1423 x86pte_t pte;
1506 1424 pfn_t pfn = page_pptonum(pp);
1507 1425 pgcnt_t pg_off = mmu_btop(va - mmu.kmap_addr);
1508 1426 htable_t *ht;
1509 1427 uint_t entry;
1510 1428 void *pte_ptr;
1511 1429
1512 1430 /*
1513 1431 * construct the requested PTE
1514 1432 */
1515 1433 attr &= ~PROT_USER;
1516 1434 attr |= HAT_STORECACHING_OK;
1517 1435 pte = hati_mkpte(pfn, attr, 0, flags);
1518 1436 PTE_SET(pte, mmu.pt_global);
1519 1437
1520 1438 /*
1521 1439 * Figure out the pte_ptr and htable and use common code to finish up
1522 1440 */
1523 1441 if (mmu.pae_hat)
1524 1442 pte_ptr = mmu.kmap_ptes + pg_off;
1525 1443 else
1526 1444 pte_ptr = (x86pte32_t *)mmu.kmap_ptes + pg_off;
1527 1445 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr) >>
1528 1446 LEVEL_SHIFT(1)];
1529 1447 entry = htable_va2entry(va, ht);
1530 1448 ++curthread->t_hatdepth;
1531 1449 ASSERT(curthread->t_hatdepth < 16);
1532 1450 (void) hati_pte_map(ht, entry, pp, pte, flags, pte_ptr);
1533 1451 --curthread->t_hatdepth;
1534 1452 }
1535 1453
1536 1454 /*
1537 1455 * hat_memload() - load a translation to the given page struct
1538 1456 *
1539 1457 * Flags for hat_memload/hat_devload/hat_*attr.
1540 1458 *
1541 1459 * HAT_LOAD Default flags to load a translation to the page.
1542 1460 *
1543 1461 * HAT_LOAD_LOCK Lock down mapping resources; hat_map(), hat_memload(),
1544 1462 * and hat_devload().
1545 1463 *
1546 1464 * HAT_LOAD_NOCONSIST Do not add mapping to page_t mapping list.
1547 1465 * sets PT_NOCONSIST
1548 1466 *
1549 1467 * HAT_LOAD_SHARE A flag to hat_memload() to indicate h/w page tables
1550 1468 * that map some user pages (not kas) is shared by more
1551 1469 * than one process (eg. ISM).
1552 1470 *
1553 1471 * HAT_LOAD_REMAP Reload a valid pte with a different page frame.
1554 1472 *
1555 1473 * HAT_NO_KALLOC Do not kmem_alloc while creating the mapping; at this
1556 1474 * point, it's setting up mapping to allocate internal
1557 1475 * hat layer data structures. This flag forces hat layer
1558 1476 * to tap its reserves in order to prevent infinite
1559 1477 * recursion.
1560 1478 *
1561 1479 * The following is a protection attribute (like PROT_READ, etc.)
1562 1480 *
1563 1481 * HAT_NOSYNC set PT_NOSYNC - this mapping's ref/mod bits
1564 1482 * are never cleared.
1565 1483 *
1566 1484 * Installing new valid PTE's and creation of the mapping list
1567 1485 * entry are controlled under the same lock. It's derived from the
1568 1486 * page_t being mapped.
1569 1487 */
1570 1488 static uint_t supported_memload_flags =
1571 1489 HAT_LOAD | HAT_LOAD_LOCK | HAT_LOAD_ADV | HAT_LOAD_NOCONSIST |
1572 1490 HAT_LOAD_SHARE | HAT_NO_KALLOC | HAT_LOAD_REMAP | HAT_LOAD_TEXT;
1573 1491
1574 1492 void
1575 1493 hat_memload(
1576 1494 hat_t *hat,
1577 1495 caddr_t addr,
1578 1496 page_t *pp,
1579 1497 uint_t attr,
1580 1498 uint_t flags)
1581 1499 {
1582 1500 uintptr_t va = (uintptr_t)addr;
1583 1501 level_t level = 0;
1584 1502 pfn_t pfn = page_pptonum(pp);
1585 1503
1586 1504 XPV_DISALLOW_MIGRATE();
1587 1505 ASSERT(IS_PAGEALIGNED(va));
1588 1506 ASSERT(hat == kas.a_hat || va < _userlimit);
1589 1507 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1590 1508 ASSERT((flags & supported_memload_flags) == flags);
1591 1509
1592 1510 ASSERT(!IN_VA_HOLE(va));
1593 1511 ASSERT(!PP_ISFREE(pp));
1594 1512
1595 1513 /*
1596 1514 * kernel address special case for performance.
1597 1515 */
1598 1516 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) {
1599 1517 ASSERT(hat == kas.a_hat);
1600 1518 hat_kmap_load(addr, pp, attr, flags);
1601 1519 XPV_ALLOW_MIGRATE();
1602 1520 return;
1603 1521 }
1604 1522
1605 1523 /*
1606 1524 * This is used for memory with normal caching enabled, so
1607 1525 * always set HAT_STORECACHING_OK.
1608 1526 */
1609 1527 attr |= HAT_STORECACHING_OK;
1610 1528 if (hati_load_common(hat, va, pp, attr, flags, level, pfn) != 0)
1611 1529 panic("unexpected hati_load_common() failure");
1612 1530 XPV_ALLOW_MIGRATE();
1613 1531 }
1614 1532
1615 1533 /* ARGSUSED */
1616 1534 void
1617 1535 hat_memload_region(struct hat *hat, caddr_t addr, struct page *pp,
1618 1536 uint_t attr, uint_t flags, hat_region_cookie_t rcookie)
1619 1537 {
1620 1538 hat_memload(hat, addr, pp, attr, flags);
1621 1539 }
1622 1540
1623 1541 /*
1624 1542 * Load the given array of page structs using large pages when possible
1625 1543 */
1626 1544 void
1627 1545 hat_memload_array(
1628 1546 hat_t *hat,
1629 1547 caddr_t addr,
1630 1548 size_t len,
1631 1549 page_t **pages,
1632 1550 uint_t attr,
1633 1551 uint_t flags)
1634 1552 {
1635 1553 uintptr_t va = (uintptr_t)addr;
1636 1554 uintptr_t eaddr = va + len;
1637 1555 level_t level;
1638 1556 size_t pgsize;
1639 1557 pgcnt_t pgindx = 0;
1640 1558 pfn_t pfn;
1641 1559 pgcnt_t i;
1642 1560
1643 1561 XPV_DISALLOW_MIGRATE();
1644 1562 ASSERT(IS_PAGEALIGNED(va));
1645 1563 ASSERT(hat == kas.a_hat || va + len <= _userlimit);
1646 1564 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1647 1565 ASSERT((flags & supported_memload_flags) == flags);
1648 1566
1649 1567 /*
1650 1568 * memload is used for memory with full caching enabled, so
1651 1569 * set HAT_STORECACHING_OK.
1652 1570 */
1653 1571 attr |= HAT_STORECACHING_OK;
1654 1572
1655 1573 /*
1656 1574 * handle all pages using largest possible pagesize
1657 1575 */
1658 1576 while (va < eaddr) {
1659 1577 /*
1660 1578 * decide what level mapping to use (ie. pagesize)
1661 1579 */
1662 1580 pfn = page_pptonum(pages[pgindx]);
1663 1581 for (level = mmu.max_page_level; ; --level) {
1664 1582 pgsize = LEVEL_SIZE(level);
1665 1583 if (level == 0)
1666 1584 break;
1667 1585
1668 1586 if (!IS_P2ALIGNED(va, pgsize) ||
1669 1587 (eaddr - va) < pgsize ||
1670 1588 !IS_P2ALIGNED(pfn_to_pa(pfn), pgsize))
1671 1589 continue;
1672 1590
1673 1591 /*
1674 1592 * To use a large mapping of this size, all the
1675 1593 * pages we are passed must be sequential subpages
1676 1594 * of the large page.
1677 1595 * hat_page_demote() can't change p_szc because
1678 1596 * all pages are locked.
1679 1597 */
1680 1598 if (pages[pgindx]->p_szc >= level) {
1681 1599 for (i = 0; i < mmu_btop(pgsize); ++i) {
1682 1600 if (pfn + i !=
1683 1601 page_pptonum(pages[pgindx + i]))
1684 1602 break;
1685 1603 ASSERT(pages[pgindx + i]->p_szc >=
1686 1604 level);
1687 1605 ASSERT(pages[pgindx] + i ==
1688 1606 pages[pgindx + i]);
1689 1607 }
1690 1608 if (i == mmu_btop(pgsize)) {
1691 1609 #ifdef DEBUG
1692 1610 if (level == 2)
1693 1611 map1gcnt++;
1694 1612 #endif
1695 1613 break;
1696 1614 }
1697 1615 }
1698 1616 }
1699 1617
1700 1618 /*
1701 1619 * Load this page mapping. If the load fails, try a smaller
1702 1620 * pagesize.
1703 1621 */
1704 1622 ASSERT(!IN_VA_HOLE(va));
1705 1623 while (hati_load_common(hat, va, pages[pgindx], attr,
1706 1624 flags, level, pfn) != 0) {
1707 1625 if (level == 0)
1708 1626 panic("unexpected hati_load_common() failure");
1709 1627 --level;
1710 1628 pgsize = LEVEL_SIZE(level);
1711 1629 }
1712 1630
1713 1631 /*
1714 1632 * move to next page
1715 1633 */
1716 1634 va += pgsize;
1717 1635 pgindx += mmu_btop(pgsize);
1718 1636 }
1719 1637 XPV_ALLOW_MIGRATE();
1720 1638 }
1721 1639
1722 1640 /* ARGSUSED */
1723 1641 void
1724 1642 hat_memload_array_region(struct hat *hat, caddr_t addr, size_t len,
1725 1643 struct page **pps, uint_t attr, uint_t flags,
1726 1644 hat_region_cookie_t rcookie)
1727 1645 {
1728 1646 hat_memload_array(hat, addr, len, pps, attr, flags);
1729 1647 }
1730 1648
1731 1649 /*
1732 1650 * void hat_devload(hat, addr, len, pf, attr, flags)
1733 1651 * load/lock the given page frame number
1734 1652 *
1735 1653 * Advisory ordering attributes. Apply only to device mappings.
1736 1654 *
1737 1655 * HAT_STRICTORDER: the CPU must issue the references in order, as the
1738 1656 * programmer specified. This is the default.
1739 1657 * HAT_UNORDERED_OK: the CPU may reorder the references (this is all kinds
1740 1658 * of reordering; store or load with store or load).
1741 1659 * HAT_MERGING_OK: merging and batching: the CPU may merge individual stores
1742 1660 * to consecutive locations (for example, turn two consecutive byte
1743 1661 * stores into one halfword store), and it may batch individual loads
1744 1662 * (for example, turn two consecutive byte loads into one halfword load).
1745 1663 * This also implies re-ordering.
1746 1664 * HAT_LOADCACHING_OK: the CPU may cache the data it fetches and reuse it
1747 1665 * until another store occurs. The default is to fetch new data
1748 1666 * on every load. This also implies merging.
1749 1667 * HAT_STORECACHING_OK: the CPU may keep the data in the cache and push it to
1750 1668 * the device (perhaps with other data) at a later time. The default is
1751 1669 * to push the data right away. This also implies load caching.
1752 1670 *
1753 1671 * Equivalent of hat_memload(), but can be used for device memory where
1754 1672 * there are no page_t's and we support additional flags (write merging, etc).
1755 1673 * Note that we can have large page mappings with this interface.
1756 1674 */
1757 1675 int supported_devload_flags = HAT_LOAD | HAT_LOAD_LOCK |
1758 1676 HAT_LOAD_NOCONSIST | HAT_STRICTORDER | HAT_UNORDERED_OK |
1759 1677 HAT_MERGING_OK | HAT_LOADCACHING_OK | HAT_STORECACHING_OK;
1760 1678
1761 1679 void
1762 1680 hat_devload(
1763 1681 hat_t *hat,
1764 1682 caddr_t addr,
1765 1683 size_t len,
1766 1684 pfn_t pfn,
1767 1685 uint_t attr,
1768 1686 int flags)
1769 1687 {
1770 1688 uintptr_t va = ALIGN2PAGE(addr);
1771 1689 uintptr_t eva = va + len;
1772 1690 level_t level;
1773 1691 size_t pgsize;
1774 1692 page_t *pp;
1775 1693 int f; /* per PTE copy of flags - maybe modified */
1776 1694 uint_t a; /* per PTE copy of attr */
1777 1695
1778 1696 XPV_DISALLOW_MIGRATE();
1779 1697 ASSERT(IS_PAGEALIGNED(va));
1780 1698 ASSERT(hat == kas.a_hat || eva <= _userlimit);
1781 1699 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1782 1700 ASSERT((flags & supported_devload_flags) == flags);
1783 1701
1784 1702 /*
1785 1703 * handle all pages
1786 1704 */
1787 1705 while (va < eva) {
1788 1706
1789 1707 /*
1790 1708 * decide what level mapping to use (ie. pagesize)
1791 1709 */
1792 1710 for (level = mmu.max_page_level; ; --level) {
1793 1711 pgsize = LEVEL_SIZE(level);
1794 1712 if (level == 0)
1795 1713 break;
1796 1714 if (IS_P2ALIGNED(va, pgsize) &&
1797 1715 (eva - va) >= pgsize &&
1798 1716 IS_P2ALIGNED(pfn, mmu_btop(pgsize))) {
1799 1717 #ifdef DEBUG
1800 1718 if (level == 2)
1801 1719 map1gcnt++;
1802 1720 #endif
1803 1721 break;
1804 1722 }
1805 1723 }
1806 1724
1807 1725 /*
1808 1726 * If this is just memory then allow caching (this happens
1809 1727 * for the nucleus pages) - though HAT_PLAT_NOCACHE can be used
1810 1728 * to override that. If we don't have a page_t then make sure
1811 1729 * NOCONSIST is set.
1812 1730 */
1813 1731 a = attr;
1814 1732 f = flags;
1815 1733 if (!pf_is_memory(pfn))
1816 1734 f |= HAT_LOAD_NOCONSIST;
1817 1735 else if (!(a & HAT_PLAT_NOCACHE))
1818 1736 a |= HAT_STORECACHING_OK;
1819 1737
1820 1738 if (f & HAT_LOAD_NOCONSIST)
1821 1739 pp = NULL;
1822 1740 else
1823 1741 pp = page_numtopp_nolock(pfn);
1824 1742
1825 1743 /*
1826 1744 * Check to make sure we are really trying to map a valid
1827 1745 * memory page. The caller wishing to intentionally map
1828 1746 * free memory pages will have passed the HAT_LOAD_NOCONSIST
1829 1747 * flag, then pp will be NULL.
1830 1748 */
1831 1749 if (pp != NULL) {
1832 1750 if (PP_ISFREE(pp)) {
1833 1751 panic("hat_devload: loading "
1834 1752 "a mapping to free page %p", (void *)pp);
1835 1753 }
1836 1754
1837 1755 if (!PAGE_LOCKED(pp) && !PP_ISNORELOC(pp)) {
1838 1756 panic("hat_devload: loading a mapping "
1839 1757 "to an unlocked page %p",
1840 1758 (void *)pp);
1841 1759 }
1842 1760 }
1843 1761
1844 1762 /*
1845 1763 * load this page mapping
1846 1764 */
1847 1765 ASSERT(!IN_VA_HOLE(va));
1848 1766 while (hati_load_common(hat, va, pp, a, f, level, pfn) != 0) {
1849 1767 if (level == 0)
1850 1768 panic("unexpected hati_load_common() failure");
1851 1769 --level;
1852 1770 pgsize = LEVEL_SIZE(level);
1853 1771 }
1854 1772
1855 1773 /*
1856 1774 * move to next page
1857 1775 */
1858 1776 va += pgsize;
1859 1777 pfn += mmu_btop(pgsize);
1860 1778 }
1861 1779 XPV_ALLOW_MIGRATE();
1862 1780 }
1863 1781
1864 1782 /*
1865 1783 * void hat_unlock(hat, addr, len)
1866 1784 * unlock the mappings to a given range of addresses
1867 1785 *
1868 1786 * Locks are tracked by ht_lock_cnt in the htable.
1869 1787 */
1870 1788 void
1871 1789 hat_unlock(hat_t *hat, caddr_t addr, size_t len)
1872 1790 {
1873 1791 uintptr_t vaddr = (uintptr_t)addr;
1874 1792 uintptr_t eaddr = vaddr + len;
1875 1793 htable_t *ht = NULL;
1876 1794
1877 1795 /*
1878 1796 * kernel entries are always locked, we don't track lock counts
1879 1797 */
1880 1798 ASSERT(hat == kas.a_hat || eaddr <= _userlimit);
1881 1799 ASSERT(IS_PAGEALIGNED(vaddr));
1882 1800 ASSERT(IS_PAGEALIGNED(eaddr));
1883 1801 if (hat == kas.a_hat)
1884 1802 return;
1885 1803 if (eaddr > _userlimit)
1886 1804 panic("hat_unlock() address out of range - above _userlimit");
1887 1805
1888 1806 XPV_DISALLOW_MIGRATE();
1889 1807 ASSERT(AS_LOCK_HELD(hat->hat_as));
1890 1808 while (vaddr < eaddr) {
1891 1809 (void) htable_walk(hat, &ht, &vaddr, eaddr);
1892 1810 if (ht == NULL)
1893 1811 break;
1894 1812
1895 1813 ASSERT(!IN_VA_HOLE(vaddr));
1896 1814
1897 1815 if (ht->ht_lock_cnt < 1)
1898 1816 panic("hat_unlock(): lock_cnt < 1, "
1899 1817 "htable=%p, vaddr=%p\n", (void *)ht, (void *)vaddr);
1900 1818 HTABLE_LOCK_DEC(ht);
1901 1819
1902 1820 vaddr += LEVEL_SIZE(ht->ht_level);
1903 1821 }
1904 1822 if (ht)
1905 1823 htable_release(ht);
1906 1824 XPV_ALLOW_MIGRATE();
1907 1825 }
1908 1826
1909 1827 /* ARGSUSED */
1910 1828 void
1911 1829 hat_unlock_region(struct hat *hat, caddr_t addr, size_t len,
1912 1830 hat_region_cookie_t rcookie)
1913 1831 {
1914 1832 panic("No shared region support on x86");
1915 1833 }
1916 1834
1917 1835 #if !defined(__xpv)
1918 1836 /*
1919 1837 * Cross call service routine to demap a virtual page on
1920 1838 * the current CPU or flush all mappings in TLB.
1921 1839 */
1922 1840 /*ARGSUSED*/
1923 1841 static int
1924 1842 hati_demap_func(xc_arg_t a1, xc_arg_t a2, xc_arg_t a3)
1925 1843 {
1926 1844 hat_t *hat = (hat_t *)a1;
1927 1845 caddr_t addr = (caddr_t)a2;
1928 1846 size_t len = (size_t)a3;
1929 1847
1930 1848 /*
1931 1849 * If the target hat isn't the kernel and this CPU isn't operating
1932 1850 * in the target hat, we can ignore the cross call.
1933 1851 */
1934 1852 if (hat != kas.a_hat && hat != CPU->cpu_current_hat)
1935 1853 return (0);
1936 1854
1937 1855 /*
1938 1856 * For a normal address, we flush a range of contiguous mappings
1939 1857 */
1940 1858 if ((uintptr_t)addr != DEMAP_ALL_ADDR) {
1941 1859 for (size_t i = 0; i < len; i += MMU_PAGESIZE)
1942 1860 mmu_tlbflush_entry(addr + i);
1943 1861 return (0);
1944 1862 }
1945 1863
1946 1864 /*
1947 1865 * Otherwise we reload cr3 to effect a complete TLB flush.
1948 1866 *
1949 1867 * A reload of cr3 on a VLP process also means we must also recopy in
1950 1868 * the pte values from the struct hat
1951 1869 */
1952 1870 if (hat->hat_flags & HAT_VLP) {
1953 1871 #if defined(__amd64)
1954 1872 x86pte_t *vlpptep = CPU->cpu_hat_info->hci_vlp_l2ptes;
1955 1873
1956 1874 VLP_COPY(hat->hat_vlp_ptes, vlpptep);
1957 1875 #elif defined(__i386)
1958 1876 reload_pae32(hat, CPU);
1959 1877 #endif
1960 1878 }
1961 1879 reload_cr3();
1962 1880 return (0);
1963 1881 }
1964 1882
1965 1883 /*
1966 1884 * Flush all TLB entries, including global (ie. kernel) ones.
1967 1885 */
1968 1886 static void
1969 1887 flush_all_tlb_entries(void)
1970 1888 {
1971 1889 ulong_t cr4 = getcr4();
1972 1890
1973 1891 if (cr4 & CR4_PGE) {
1974 1892 setcr4(cr4 & ~(ulong_t)CR4_PGE);
1975 1893 setcr4(cr4);
1976 1894
1977 1895 /*
1978 1896 * 32 bit PAE also needs to always reload_cr3()
1979 1897 */
1980 1898 if (mmu.max_level == 2)
1981 1899 reload_cr3();
1982 1900 } else {
1983 1901 reload_cr3();
1984 1902 }
1985 1903 }
1986 1904
1987 1905 #define TLB_CPU_HALTED (01ul)
1988 1906 #define TLB_INVAL_ALL (02ul)
1989 1907 #define CAS_TLB_INFO(cpu, old, new) \
1990 1908 atomic_cas_ulong((ulong_t *)&(cpu)->cpu_m.mcpu_tlb_info, (old), (new))
1991 1909
1992 1910 /*
1993 1911 * Record that a CPU is going idle
1994 1912 */
1995 1913 void
1996 1914 tlb_going_idle(void)
1997 1915 {
1998 1916 atomic_or_ulong((ulong_t *)&CPU->cpu_m.mcpu_tlb_info, TLB_CPU_HALTED);
1999 1917 }
2000 1918
2001 1919 /*
2002 1920 * Service a delayed TLB flush if coming out of being idle.
2003 1921 * It will be called from cpu idle notification with interrupt disabled.
2004 1922 */
2005 1923 void
2006 1924 tlb_service(void)
2007 1925 {
2008 1926 ulong_t tlb_info;
2009 1927 ulong_t found;
2010 1928
2011 1929 /*
2012 1930 * We only have to do something if coming out of being idle.
2013 1931 */
2014 1932 tlb_info = CPU->cpu_m.mcpu_tlb_info;
2015 1933 if (tlb_info & TLB_CPU_HALTED) {
2016 1934 ASSERT(CPU->cpu_current_hat == kas.a_hat);
2017 1935
2018 1936 /*
2019 1937 * Atomic clear and fetch of old state.
2020 1938 */
2021 1939 while ((found = CAS_TLB_INFO(CPU, tlb_info, 0)) != tlb_info) {
2022 1940 ASSERT(found & TLB_CPU_HALTED);
2023 1941 tlb_info = found;
2024 1942 SMT_PAUSE();
2025 1943 }
2026 1944 if (tlb_info & TLB_INVAL_ALL)
2027 1945 flush_all_tlb_entries();
2028 1946 }
2029 1947 }
2030 1948 #endif /* !__xpv */
2031 1949
2032 1950 /*
2033 1951 * Internal routine to do cross calls to invalidate a range of pages on
2034 1952 * all CPUs using a given hat.
2035 1953 */
2036 1954 void
2037 1955 hat_tlb_inval_range(hat_t *hat, uintptr_t va, size_t len)
2038 1956 {
2039 1957 extern int flushes_require_xcalls; /* from mp_startup.c */
2040 1958 cpuset_t justme;
2041 1959 cpuset_t cpus_to_shootdown;
2042 1960 #ifndef __xpv
2043 1961 cpuset_t check_cpus;
2044 1962 cpu_t *cpup;
2045 1963 int c;
2046 1964 #endif
2047 1965
2048 1966 /*
2049 1967 * If the hat is being destroyed, there are no more users, so
2050 1968 * demap need not do anything.
2051 1969 */
2052 1970 if (hat->hat_flags & HAT_FREEING)
2053 1971 return;
2054 1972
2055 1973 /*
2056 1974 * If demapping from a shared pagetable, we best demap the
2057 1975 * entire set of user TLBs, since we don't know what addresses
2058 1976 * these were shared at.
2059 1977 */
2060 1978 if (hat->hat_flags & HAT_SHARED) {
2061 1979 hat = kas.a_hat;
2062 1980 va = DEMAP_ALL_ADDR;
2063 1981 }
2064 1982
2065 1983 /*
2066 1984 * if not running with multiple CPUs, don't use cross calls
2067 1985 */
2068 1986 if (panicstr || !flushes_require_xcalls) {
2069 1987 #ifdef __xpv
2070 1988 if (va == DEMAP_ALL_ADDR) {
2071 1989 xen_flush_tlb();
2072 1990 } else {
2073 1991 for (size_t i = 0; i < len; i += MMU_PAGESIZE)
2074 1992 xen_flush_va((caddr_t)(va + i));
2075 1993 }
2076 1994 #else
2077 1995 (void) hati_demap_func((xc_arg_t)hat,
2078 1996 (xc_arg_t)va, (xc_arg_t)len);
2079 1997 #endif
2080 1998 return;
2081 1999 }
2082 2000
2083 2001
2084 2002 /*
2085 2003 * Determine CPUs to shootdown. Kernel changes always do all CPUs.
2086 2004 * Otherwise it's just CPUs currently executing in this hat.
2087 2005 */
2088 2006 kpreempt_disable();
2089 2007 CPUSET_ONLY(justme, CPU->cpu_id);
2090 2008 if (hat == kas.a_hat)
2091 2009 cpus_to_shootdown = khat_cpuset;
2092 2010 else
2093 2011 cpus_to_shootdown = hat->hat_cpus;
2094 2012
2095 2013 #ifndef __xpv
2096 2014 /*
2097 2015 * If any CPUs in the set are idle, just request a delayed flush
2098 2016 * and avoid waking them up.
2099 2017 */
2100 2018 check_cpus = cpus_to_shootdown;
2101 2019 for (c = 0; c < NCPU && !CPUSET_ISNULL(check_cpus); ++c) {
2102 2020 ulong_t tlb_info;
2103 2021
2104 2022 if (!CPU_IN_SET(check_cpus, c))
2105 2023 continue;
2106 2024 CPUSET_DEL(check_cpus, c);
2107 2025 cpup = cpu[c];
2108 2026 if (cpup == NULL)
2109 2027 continue;
2110 2028
2111 2029 tlb_info = cpup->cpu_m.mcpu_tlb_info;
2112 2030 while (tlb_info == TLB_CPU_HALTED) {
2113 2031 (void) CAS_TLB_INFO(cpup, TLB_CPU_HALTED,
2114 2032 TLB_CPU_HALTED | TLB_INVAL_ALL);
2115 2033 SMT_PAUSE();
2116 2034 tlb_info = cpup->cpu_m.mcpu_tlb_info;
2117 2035 }
2118 2036 if (tlb_info == (TLB_CPU_HALTED | TLB_INVAL_ALL)) {
2119 2037 HATSTAT_INC(hs_tlb_inval_delayed);
2120 2038 CPUSET_DEL(cpus_to_shootdown, c);
2121 2039 }
2122 2040 }
2123 2041 #endif
2124 2042
2125 2043 if (CPUSET_ISNULL(cpus_to_shootdown) ||
2126 2044 CPUSET_ISEQUAL(cpus_to_shootdown, justme)) {
2127 2045
2128 2046 #ifdef __xpv
2129 2047 if (va == DEMAP_ALL_ADDR) {
2130 2048 xen_flush_tlb();
2131 2049 } else {
2132 2050 for (size_t i = 0; i < len; i += MMU_PAGESIZE)
2133 2051 xen_flush_va((caddr_t)(va + i));
2134 2052 }
2135 2053 #else
2136 2054 (void) hati_demap_func((xc_arg_t)hat,
2137 2055 (xc_arg_t)va, (xc_arg_t)len);
2138 2056 #endif
2139 2057
2140 2058 } else {
2141 2059
2142 2060 CPUSET_ADD(cpus_to_shootdown, CPU->cpu_id);
2143 2061 #ifdef __xpv
2144 2062 if (va == DEMAP_ALL_ADDR) {
2145 2063 xen_gflush_tlb(cpus_to_shootdown);
2146 2064 } else {
2147 2065 for (size_t i = 0; i < len; i += MMU_PAGESIZE) {
2148 2066 xen_gflush_va((caddr_t)(va + i),
2149 2067 cpus_to_shootdown);
2150 2068 }
2151 2069 }
2152 2070 #else
2153 2071 xc_call((xc_arg_t)hat, (xc_arg_t)va, (xc_arg_t)len,
2154 2072 CPUSET2BV(cpus_to_shootdown), hati_demap_func);
2155 2073 #endif
2156 2074
2157 2075 }
2158 2076 kpreempt_enable();
2159 2077 }
2160 2078
2161 2079 void
2162 2080 hat_tlb_inval(hat_t *hat, uintptr_t va)
2163 2081 {
2164 2082 hat_tlb_inval_range(hat, va, MMU_PAGESIZE);
2165 2083 }
2166 2084
2167 2085 /*
2168 2086 * Interior routine for HAT_UNLOADs from hat_unload_callback(),
2169 2087 * hat_kmap_unload() OR from hat_steal() code. This routine doesn't
2170 2088 * handle releasing of the htables.
2171 2089 */
2172 2090 void
2173 2091 hat_pte_unmap(
2174 2092 htable_t *ht,
2175 2093 uint_t entry,
2176 2094 uint_t flags,
2177 2095 x86pte_t old_pte,
2178 2096 void *pte_ptr,
2179 2097 boolean_t tlb)
2180 2098 {
2181 2099 hat_t *hat = ht->ht_hat;
2182 2100 hment_t *hm = NULL;
2183 2101 page_t *pp = NULL;
2184 2102 level_t l = ht->ht_level;
2185 2103 pfn_t pfn;
2186 2104
2187 2105 /*
2188 2106 * We always track the locking counts, even if nothing is unmapped
2189 2107 */
2190 2108 if ((flags & HAT_UNLOAD_UNLOCK) != 0 && hat != kas.a_hat) {
2191 2109 ASSERT(ht->ht_lock_cnt > 0);
2192 2110 HTABLE_LOCK_DEC(ht);
2193 2111 }
2194 2112
2195 2113 /*
2196 2114 * Figure out which page's mapping list lock to acquire using the PFN
2197 2115 * passed in "old" PTE. We then attempt to invalidate the PTE.
2198 2116 * If another thread, probably a hat_pageunload, has asynchronously
2199 2117 * unmapped/remapped this address we'll loop here.
2200 2118 */
2201 2119 ASSERT(ht->ht_busy > 0);
2202 2120 while (PTE_ISVALID(old_pte)) {
2203 2121 pfn = PTE2PFN(old_pte, l);
2204 2122 if (PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST) {
2205 2123 pp = NULL;
2206 2124 } else {
2207 2125 #ifdef __xpv
2208 2126 if (pfn == PFN_INVALID)
2209 2127 panic("Invalid PFN, but not PT_NOCONSIST");
2210 2128 #endif
2211 2129 pp = page_numtopp_nolock(pfn);
2212 2130 if (pp == NULL) {
2213 2131 panic("no page_t, not NOCONSIST: old_pte="
2214 2132 FMT_PTE " ht=%lx entry=0x%x pte_ptr=%lx",
2215 2133 old_pte, (uintptr_t)ht, entry,
2216 2134 (uintptr_t)pte_ptr);
2217 2135 }
2218 2136 x86_hm_enter(pp);
2219 2137 }
2220 2138
2221 2139 old_pte = x86pte_inval(ht, entry, old_pte, pte_ptr, tlb);
2222 2140
2223 2141 /*
2224 2142 * If the page hadn't changed we've unmapped it and can proceed
2225 2143 */
2226 2144 if (PTE_ISVALID(old_pte) && PTE2PFN(old_pte, l) == pfn)
2227 2145 break;
2228 2146
2229 2147 /*
2230 2148 * Otherwise, we'll have to retry with the current old_pte.
2231 2149 * Drop the hment lock, since the pfn may have changed.
2232 2150 */
2233 2151 if (pp != NULL) {
2234 2152 x86_hm_exit(pp);
2235 2153 pp = NULL;
2236 2154 } else {
2237 2155 ASSERT(PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST);
2238 2156 }
2239 2157 }
2240 2158
2241 2159 /*
2242 2160 * If the old mapping wasn't valid, there's nothing more to do
2243 2161 */
2244 2162 if (!PTE_ISVALID(old_pte)) {
2245 2163 if (pp != NULL)
2246 2164 x86_hm_exit(pp);
2247 2165 return;
2248 2166 }
2249 2167
2250 2168 /*
2251 2169 * Take care of syncing any MOD/REF bits and removing the hment.
2252 2170 */
2253 2171 if (pp != NULL) {
2254 2172 if (!(flags & HAT_UNLOAD_NOSYNC))
2255 2173 hati_sync_pte_to_page(pp, old_pte, l);
2256 2174 hm = hment_remove(pp, ht, entry);
2257 2175 x86_hm_exit(pp);
2258 2176 if (hm != NULL)
2259 2177 hment_free(hm);
2260 2178 }
2261 2179
2262 2180 /*
2263 2181 * Handle book keeping in the htable and hat
2264 2182 */
2265 2183 ASSERT(ht->ht_valid_cnt > 0);
2266 2184 HTABLE_DEC(ht->ht_valid_cnt);
2267 2185 PGCNT_DEC(hat, l);
2268 2186 }
2269 2187
2270 2188 /*
2271 2189 * very cheap unload implementation to special case some kernel addresses
2272 2190 */
2273 2191 static void
2274 2192 hat_kmap_unload(caddr_t addr, size_t len, uint_t flags)
2275 2193 {
2276 2194 uintptr_t va = (uintptr_t)addr;
2277 2195 uintptr_t eva = va + len;
2278 2196 pgcnt_t pg_index;
2279 2197 htable_t *ht;
2280 2198 uint_t entry;
2281 2199 x86pte_t *pte_ptr;
2282 2200 x86pte_t old_pte;
2283 2201
2284 2202 for (; va < eva; va += MMU_PAGESIZE) {
2285 2203 /*
2286 2204 * Get the PTE
2287 2205 */
2288 2206 pg_index = mmu_btop(va - mmu.kmap_addr);
2289 2207 pte_ptr = PT_INDEX_PTR(mmu.kmap_ptes, pg_index);
2290 2208 old_pte = GET_PTE(pte_ptr);
2291 2209
2292 2210 /*
2293 2211 * get the htable / entry
2294 2212 */
2295 2213 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr)
2296 2214 >> LEVEL_SHIFT(1)];
2297 2215 entry = htable_va2entry(va, ht);
2298 2216
2299 2217 /*
2300 2218 * use mostly common code to unmap it.
2301 2219 */
2302 2220 hat_pte_unmap(ht, entry, flags, old_pte, pte_ptr, B_TRUE);
2303 2221 }
2304 2222 }
2305 2223
2306 2224
2307 2225 /*
2308 2226 * unload a range of virtual address space (no callback)
2309 2227 */
2310 2228 void
2311 2229 hat_unload(hat_t *hat, caddr_t addr, size_t len, uint_t flags)
2312 2230 {
2313 2231 uintptr_t va = (uintptr_t)addr;
2314 2232
2315 2233 XPV_DISALLOW_MIGRATE();
2316 2234 ASSERT(hat == kas.a_hat || va + len <= _userlimit);
2317 2235
2318 2236 /*
2319 2237 * special case for performance.
2320 2238 */
2321 2239 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) {
2322 2240 ASSERT(hat == kas.a_hat);
2323 2241 hat_kmap_unload(addr, len, flags);
2324 2242 } else {
2325 2243 hat_unload_callback(hat, addr, len, flags, NULL);
2326 2244 }
2327 2245 XPV_ALLOW_MIGRATE();
2328 2246 }
2329 2247
2330 2248 /*
2331 2249 * Do the callbacks for ranges being unloaded.
2332 2250 */
2333 2251 typedef struct range_info {
2334 2252 uintptr_t rng_va;
2335 2253 ulong_t rng_cnt;
2336 2254 level_t rng_level;
2337 2255 } range_info_t;
2338 2256
2339 2257 /*
2340 2258 * Invalidate the TLB, and perform the callback to the upper level VM system,
2341 2259 * for the specified ranges of contiguous pages.
2342 2260 */
2343 2261 static void
2344 2262 handle_ranges(hat_t *hat, hat_callback_t *cb, uint_t cnt, range_info_t *range)
2345 2263 {
2346 2264 while (cnt > 0) {
2347 2265 size_t len;
2348 2266
2349 2267 --cnt;
2350 2268 len = range[cnt].rng_cnt << LEVEL_SHIFT(range[cnt].rng_level);
2351 2269 hat_tlb_inval_range(hat, (uintptr_t)range[cnt].rng_va, len);
2352 2270
2353 2271 if (cb != NULL) {
2354 2272 cb->hcb_start_addr = (caddr_t)range[cnt].rng_va;
2355 2273 cb->hcb_end_addr = cb->hcb_start_addr;
2356 2274 cb->hcb_end_addr += len;
2357 2275 cb->hcb_function(cb);
2358 2276 }
2359 2277 }
2360 2278 }
2361 2279
2362 2280 /*
2363 2281 * Unload a given range of addresses (has optional callback)
2364 2282 *
2365 2283 * Flags:
2366 2284 * define HAT_UNLOAD 0x00
2367 2285 * define HAT_UNLOAD_NOSYNC 0x02
2368 2286 * define HAT_UNLOAD_UNLOCK 0x04
2369 2287 * define HAT_UNLOAD_OTHER 0x08 - not used
2370 2288 * define HAT_UNLOAD_UNMAP 0x10 - same as HAT_UNLOAD
2371 2289 */
2372 2290 #define MAX_UNLOAD_CNT (8)
2373 2291 void
2374 2292 hat_unload_callback(
2375 2293 hat_t *hat,
2376 2294 caddr_t addr,
2377 2295 size_t len,
2378 2296 uint_t flags,
2379 2297 hat_callback_t *cb)
2380 2298 {
2381 2299 uintptr_t vaddr = (uintptr_t)addr;
2382 2300 uintptr_t eaddr = vaddr + len;
2383 2301 htable_t *ht = NULL;
2384 2302 uint_t entry;
2385 2303 uintptr_t contig_va = (uintptr_t)-1L;
2386 2304 range_info_t r[MAX_UNLOAD_CNT];
2387 2305 uint_t r_cnt = 0;
2388 2306 x86pte_t old_pte;
2389 2307
2390 2308 XPV_DISALLOW_MIGRATE();
2391 2309 ASSERT(hat == kas.a_hat || eaddr <= _userlimit);
2392 2310 ASSERT(IS_PAGEALIGNED(vaddr));
2393 2311 ASSERT(IS_PAGEALIGNED(eaddr));
2394 2312
2395 2313 /*
2396 2314 * Special case a single page being unloaded for speed. This happens
2397 2315 * quite frequently, COW faults after a fork() for example.
2398 2316 */
2399 2317 if (cb == NULL && len == MMU_PAGESIZE) {
2400 2318 ht = htable_getpte(hat, vaddr, &entry, &old_pte, 0);
2401 2319 if (ht != NULL) {
2402 2320 if (PTE_ISVALID(old_pte)) {
2403 2321 hat_pte_unmap(ht, entry, flags, old_pte,
2404 2322 NULL, B_TRUE);
2405 2323 }
2406 2324 htable_release(ht);
2407 2325 }
2408 2326 XPV_ALLOW_MIGRATE();
2409 2327 return;
2410 2328 }
2411 2329
2412 2330 while (vaddr < eaddr) {
2413 2331 old_pte = htable_walk(hat, &ht, &vaddr, eaddr);
2414 2332 if (ht == NULL)
2415 2333 break;
2416 2334
2417 2335 ASSERT(!IN_VA_HOLE(vaddr));
2418 2336
2419 2337 if (vaddr < (uintptr_t)addr)
2420 2338 panic("hat_unload_callback(): unmap inside large page");
2421 2339
2422 2340 /*
2423 2341 * We'll do the call backs for contiguous ranges
2424 2342 */
2425 2343 if (vaddr != contig_va ||
2426 2344 (r_cnt > 0 && r[r_cnt - 1].rng_level != ht->ht_level)) {
2427 2345 if (r_cnt == MAX_UNLOAD_CNT) {
2428 2346 handle_ranges(hat, cb, r_cnt, r);
2429 2347 r_cnt = 0;
2430 2348 }
2431 2349 r[r_cnt].rng_va = vaddr;
2432 2350 r[r_cnt].rng_cnt = 0;
2433 2351 r[r_cnt].rng_level = ht->ht_level;
2434 2352 ++r_cnt;
2435 2353 }
2436 2354
2437 2355 /*
2438 2356 * Unload one mapping (for a single page) from the page tables.
2439 2357 * Note that we do not remove the mapping from the TLB yet,
2440 2358 * as indicated by the tlb=FALSE argument to hat_pte_unmap().
2441 2359 * handle_ranges() will clear the TLB entries with one call to
2442 2360 * hat_tlb_inval_range() per contiguous range. This is
2443 2361 * safe because the page can not be reused until the
2444 2362 * callback is made (or we return).
2445 2363 */
2446 2364 entry = htable_va2entry(vaddr, ht);
2447 2365 hat_pte_unmap(ht, entry, flags, old_pte, NULL, B_FALSE);
2448 2366 ASSERT(ht->ht_level <= mmu.max_page_level);
2449 2367 vaddr += LEVEL_SIZE(ht->ht_level);
2450 2368 contig_va = vaddr;
2451 2369 ++r[r_cnt - 1].rng_cnt;
2452 2370 }
2453 2371 if (ht)
2454 2372 htable_release(ht);
2455 2373
2456 2374 /*
2457 2375 * handle last range for callbacks
2458 2376 */
2459 2377 if (r_cnt > 0)
2460 2378 handle_ranges(hat, cb, r_cnt, r);
2461 2379 XPV_ALLOW_MIGRATE();
2462 2380 }
2463 2381
2464 2382 /*
2465 2383 * Invalidate a virtual address translation on a slave CPU during
2466 2384 * panic() dumps.
2467 2385 */
2468 2386 void
2469 2387 hat_flush_range(hat_t *hat, caddr_t va, size_t size)
2470 2388 {
2471 2389 ssize_t sz;
2472 2390 caddr_t endva = va + size;
2473 2391
2474 2392 while (va < endva) {
2475 2393 sz = hat_getpagesize(hat, va);
2476 2394 if (sz < 0) {
2477 2395 #ifdef __xpv
2478 2396 xen_flush_tlb();
2479 2397 #else
2480 2398 flush_all_tlb_entries();
2481 2399 #endif
2482 2400 break;
2483 2401 }
2484 2402 #ifdef __xpv
2485 2403 xen_flush_va(va);
2486 2404 #else
2487 2405 mmu_tlbflush_entry(va);
2488 2406 #endif
2489 2407 va += sz;
2490 2408 }
2491 2409 }
2492 2410
2493 2411 /*
2494 2412 * synchronize mapping with software data structures
2495 2413 *
2496 2414 * This interface is currently only used by the working set monitor
2497 2415 * driver.
2498 2416 */
2499 2417 /*ARGSUSED*/
2500 2418 void
2501 2419 hat_sync(hat_t *hat, caddr_t addr, size_t len, uint_t flags)
2502 2420 {
2503 2421 uintptr_t vaddr = (uintptr_t)addr;
2504 2422 uintptr_t eaddr = vaddr + len;
2505 2423 htable_t *ht = NULL;
2506 2424 uint_t entry;
2507 2425 x86pte_t pte;
2508 2426 x86pte_t save_pte;
2509 2427 x86pte_t new;
2510 2428 page_t *pp;
2511 2429
2512 2430 ASSERT(!IN_VA_HOLE(vaddr));
2513 2431 ASSERT(IS_PAGEALIGNED(vaddr));
2514 2432 ASSERT(IS_PAGEALIGNED(eaddr));
2515 2433 ASSERT(hat == kas.a_hat || eaddr <= _userlimit);
2516 2434
2517 2435 XPV_DISALLOW_MIGRATE();
2518 2436 for (; vaddr < eaddr; vaddr += LEVEL_SIZE(ht->ht_level)) {
2519 2437 try_again:
2520 2438 pte = htable_walk(hat, &ht, &vaddr, eaddr);
2521 2439 if (ht == NULL)
2522 2440 break;
2523 2441 entry = htable_va2entry(vaddr, ht);
2524 2442
2525 2443 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC ||
2526 2444 PTE_GET(pte, PT_REF | PT_MOD) == 0)
2527 2445 continue;
2528 2446
2529 2447 /*
2530 2448 * We need to acquire the mapping list lock to protect
2531 2449 * against hat_pageunload(), hat_unload(), etc.
2532 2450 */
2533 2451 pp = page_numtopp_nolock(PTE2PFN(pte, ht->ht_level));
2534 2452 if (pp == NULL)
2535 2453 break;
2536 2454 x86_hm_enter(pp);
2537 2455 save_pte = pte;
2538 2456 pte = x86pte_get(ht, entry);
2539 2457 if (pte != save_pte) {
2540 2458 x86_hm_exit(pp);
2541 2459 goto try_again;
2542 2460 }
2543 2461 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC ||
2544 2462 PTE_GET(pte, PT_REF | PT_MOD) == 0) {
2545 2463 x86_hm_exit(pp);
2546 2464 continue;
2547 2465 }
2548 2466
2549 2467 /*
2550 2468 * Need to clear ref or mod bits. We may compete with
2551 2469 * hardware updating the R/M bits and have to try again.
2552 2470 */
2553 2471 if (flags == HAT_SYNC_ZERORM) {
2554 2472 new = pte;
2555 2473 PTE_CLR(new, PT_REF | PT_MOD);
2556 2474 pte = hati_update_pte(ht, entry, pte, new);
2557 2475 if (pte != 0) {
2558 2476 x86_hm_exit(pp);
2559 2477 goto try_again;
2560 2478 }
2561 2479 } else {
2562 2480 /*
2563 2481 * sync the PTE to the page_t
2564 2482 */
2565 2483 hati_sync_pte_to_page(pp, save_pte, ht->ht_level);
2566 2484 }
2567 2485 x86_hm_exit(pp);
2568 2486 }
2569 2487 if (ht)
2570 2488 htable_release(ht);
2571 2489 XPV_ALLOW_MIGRATE();
2572 2490 }
2573 2491
2574 2492 /*
2575 2493 * void hat_map(hat, addr, len, flags)
2576 2494 */
2577 2495 /*ARGSUSED*/
2578 2496 void
2579 2497 hat_map(hat_t *hat, caddr_t addr, size_t len, uint_t flags)
2580 2498 {
2581 2499 /* does nothing */
2582 2500 }
2583 2501
2584 2502 /*
2585 2503 * uint_t hat_getattr(hat, addr, *attr)
2586 2504 * returns attr for <hat,addr> in *attr. returns 0 if there was a
2587 2505 * mapping and *attr is valid, nonzero if there was no mapping and
2588 2506 * *attr is not valid.
2589 2507 */
2590 2508 uint_t
2591 2509 hat_getattr(hat_t *hat, caddr_t addr, uint_t *attr)
2592 2510 {
2593 2511 uintptr_t vaddr = ALIGN2PAGE(addr);
2594 2512 htable_t *ht = NULL;
2595 2513 x86pte_t pte;
2596 2514
2597 2515 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2598 2516
2599 2517 if (IN_VA_HOLE(vaddr))
2600 2518 return ((uint_t)-1);
2601 2519
2602 2520 ht = htable_getpte(hat, vaddr, NULL, &pte, mmu.max_page_level);
2603 2521 if (ht == NULL)
2604 2522 return ((uint_t)-1);
2605 2523
2606 2524 if (!PTE_ISVALID(pte) || !PTE_ISPAGE(pte, ht->ht_level)) {
2607 2525 htable_release(ht);
2608 2526 return ((uint_t)-1);
2609 2527 }
2610 2528
2611 2529 *attr = PROT_READ;
2612 2530 if (PTE_GET(pte, PT_WRITABLE))
2613 2531 *attr |= PROT_WRITE;
2614 2532 if (PTE_GET(pte, PT_USER))
2615 2533 *attr |= PROT_USER;
2616 2534 if (!PTE_GET(pte, mmu.pt_nx))
2617 2535 *attr |= PROT_EXEC;
2618 2536 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC)
2619 2537 *attr |= HAT_NOSYNC;
2620 2538 htable_release(ht);
2621 2539 return (0);
2622 2540 }
2623 2541
2624 2542 /*
2625 2543 * hat_updateattr() applies the given attribute change to an existing mapping
2626 2544 */
2627 2545 #define HAT_LOAD_ATTR 1
2628 2546 #define HAT_SET_ATTR 2
2629 2547 #define HAT_CLR_ATTR 3
2630 2548
2631 2549 static void
2632 2550 hat_updateattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr, int what)
2633 2551 {
2634 2552 uintptr_t vaddr = (uintptr_t)addr;
2635 2553 uintptr_t eaddr = (uintptr_t)addr + len;
2636 2554 htable_t *ht = NULL;
2637 2555 uint_t entry;
2638 2556 x86pte_t oldpte, newpte;
2639 2557 page_t *pp;
2640 2558
2641 2559 XPV_DISALLOW_MIGRATE();
2642 2560 ASSERT(IS_PAGEALIGNED(vaddr));
2643 2561 ASSERT(IS_PAGEALIGNED(eaddr));
2644 2562 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
2645 2563 for (; vaddr < eaddr; vaddr += LEVEL_SIZE(ht->ht_level)) {
2646 2564 try_again:
2647 2565 oldpte = htable_walk(hat, &ht, &vaddr, eaddr);
2648 2566 if (ht == NULL)
2649 2567 break;
2650 2568 if (PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOCONSIST)
2651 2569 continue;
2652 2570
2653 2571 pp = page_numtopp_nolock(PTE2PFN(oldpte, ht->ht_level));
2654 2572 if (pp == NULL)
2655 2573 continue;
2656 2574 x86_hm_enter(pp);
2657 2575
2658 2576 newpte = oldpte;
2659 2577 /*
2660 2578 * We found a page table entry in the desired range,
2661 2579 * figure out the new attributes.
2662 2580 */
2663 2581 if (what == HAT_SET_ATTR || what == HAT_LOAD_ATTR) {
2664 2582 if ((attr & PROT_WRITE) &&
2665 2583 !PTE_GET(oldpte, PT_WRITABLE))
2666 2584 newpte |= PT_WRITABLE;
2667 2585
2668 2586 if ((attr & HAT_NOSYNC) &&
2669 2587 PTE_GET(oldpte, PT_SOFTWARE) < PT_NOSYNC)
2670 2588 newpte |= PT_NOSYNC;
2671 2589
2672 2590 if ((attr & PROT_EXEC) && PTE_GET(oldpte, mmu.pt_nx))
2673 2591 newpte &= ~mmu.pt_nx;
2674 2592 }
2675 2593
2676 2594 if (what == HAT_LOAD_ATTR) {
2677 2595 if (!(attr & PROT_WRITE) &&
2678 2596 PTE_GET(oldpte, PT_WRITABLE))
2679 2597 newpte &= ~PT_WRITABLE;
2680 2598
2681 2599 if (!(attr & HAT_NOSYNC) &&
2682 2600 PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOSYNC)
2683 2601 newpte &= ~PT_SOFTWARE;
2684 2602
2685 2603 if (!(attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx))
2686 2604 newpte |= mmu.pt_nx;
2687 2605 }
2688 2606
2689 2607 if (what == HAT_CLR_ATTR) {
2690 2608 if ((attr & PROT_WRITE) && PTE_GET(oldpte, PT_WRITABLE))
2691 2609 newpte &= ~PT_WRITABLE;
2692 2610
2693 2611 if ((attr & HAT_NOSYNC) &&
2694 2612 PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOSYNC)
2695 2613 newpte &= ~PT_SOFTWARE;
2696 2614
2697 2615 if ((attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx))
2698 2616 newpte |= mmu.pt_nx;
2699 2617 }
2700 2618
2701 2619 /*
2702 2620 * Ensure NOSYNC/NOCONSIST mappings have REF and MOD set.
2703 2621 * x86pte_set() depends on this.
2704 2622 */
2705 2623 if (PTE_GET(newpte, PT_SOFTWARE) >= PT_NOSYNC)
2706 2624 newpte |= PT_REF | PT_MOD;
2707 2625
2708 2626 /*
2709 2627 * what about PROT_READ or others? this code only handles:
2710 2628 * EXEC, WRITE, NOSYNC
2711 2629 */
2712 2630
2713 2631 /*
2714 2632 * If new PTE really changed, update the table.
2715 2633 */
2716 2634 if (newpte != oldpte) {
2717 2635 entry = htable_va2entry(vaddr, ht);
2718 2636 oldpte = hati_update_pte(ht, entry, oldpte, newpte);
2719 2637 if (oldpte != 0) {
2720 2638 x86_hm_exit(pp);
2721 2639 goto try_again;
2722 2640 }
2723 2641 }
2724 2642 x86_hm_exit(pp);
2725 2643 }
2726 2644 if (ht)
2727 2645 htable_release(ht);
2728 2646 XPV_ALLOW_MIGRATE();
2729 2647 }
2730 2648
2731 2649 /*
2732 2650 * Various wrappers for hat_updateattr()
2733 2651 */
2734 2652 void
2735 2653 hat_setattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr)
2736 2654 {
2737 2655 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2738 2656 hat_updateattr(hat, addr, len, attr, HAT_SET_ATTR);
2739 2657 }
2740 2658
2741 2659 void
2742 2660 hat_clrattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr)
2743 2661 {
2744 2662 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2745 2663 hat_updateattr(hat, addr, len, attr, HAT_CLR_ATTR);
2746 2664 }
2747 2665
2748 2666 void
2749 2667 hat_chgattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr)
2750 2668 {
2751 2669 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2752 2670 hat_updateattr(hat, addr, len, attr, HAT_LOAD_ATTR);
2753 2671 }
2754 2672
2755 2673 void
2756 2674 hat_chgprot(hat_t *hat, caddr_t addr, size_t len, uint_t vprot)
2757 2675 {
2758 2676 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2759 2677 hat_updateattr(hat, addr, len, vprot & HAT_PROT_MASK, HAT_LOAD_ATTR);
2760 2678 }
2761 2679
2762 2680 /*
2763 2681 * size_t hat_getpagesize(hat, addr)
2764 2682 * returns pagesize in bytes for <hat, addr>. returns -1 of there is
2765 2683 * no mapping. This is an advisory call.
2766 2684 */
2767 2685 ssize_t
2768 2686 hat_getpagesize(hat_t *hat, caddr_t addr)
2769 2687 {
2770 2688 uintptr_t vaddr = ALIGN2PAGE(addr);
2771 2689 htable_t *ht;
2772 2690 size_t pagesize;
2773 2691
2774 2692 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2775 2693 if (IN_VA_HOLE(vaddr))
2776 2694 return (-1);
2777 2695 ht = htable_getpage(hat, vaddr, NULL);
2778 2696 if (ht == NULL)
2779 2697 return (-1);
2780 2698 pagesize = LEVEL_SIZE(ht->ht_level);
2781 2699 htable_release(ht);
2782 2700 return (pagesize);
2783 2701 }
2784 2702
2785 2703
2786 2704
2787 2705 /*
2788 2706 * pfn_t hat_getpfnum(hat, addr)
2789 2707 * returns pfn for <hat, addr> or PFN_INVALID if mapping is invalid.
2790 2708 */
2791 2709 pfn_t
2792 2710 hat_getpfnum(hat_t *hat, caddr_t addr)
2793 2711 {
2794 2712 uintptr_t vaddr = ALIGN2PAGE(addr);
2795 2713 htable_t *ht;
2796 2714 uint_t entry;
2797 2715 pfn_t pfn = PFN_INVALID;
2798 2716
2799 2717 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2800 2718 if (khat_running == 0)
2801 2719 return (PFN_INVALID);
2802 2720
2803 2721 if (IN_VA_HOLE(vaddr))
2804 2722 return (PFN_INVALID);
2805 2723
2806 2724 XPV_DISALLOW_MIGRATE();
2807 2725 /*
2808 2726 * A very common use of hat_getpfnum() is from the DDI for kernel pages.
2809 2727 * Use the kmap_ptes (which also covers the 32 bit heap) to speed
2810 2728 * this up.
2811 2729 */
2812 2730 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) {
2813 2731 x86pte_t pte;
2814 2732 pgcnt_t pg_index;
2815 2733
2816 2734 pg_index = mmu_btop(vaddr - mmu.kmap_addr);
2817 2735 pte = GET_PTE(PT_INDEX_PTR(mmu.kmap_ptes, pg_index));
2818 2736 if (PTE_ISVALID(pte))
2819 2737 /*LINTED [use of constant 0 causes a lint warning] */
2820 2738 pfn = PTE2PFN(pte, 0);
2821 2739 XPV_ALLOW_MIGRATE();
2822 2740 return (pfn);
2823 2741 }
2824 2742
2825 2743 ht = htable_getpage(hat, vaddr, &entry);
2826 2744 if (ht == NULL) {
2827 2745 XPV_ALLOW_MIGRATE();
2828 2746 return (PFN_INVALID);
2829 2747 }
2830 2748 ASSERT(vaddr >= ht->ht_vaddr);
2831 2749 ASSERT(vaddr <= HTABLE_LAST_PAGE(ht));
2832 2750 pfn = PTE2PFN(x86pte_get(ht, entry), ht->ht_level);
2833 2751 if (ht->ht_level > 0)
2834 2752 pfn += mmu_btop(vaddr & LEVEL_OFFSET(ht->ht_level));
2835 2753 htable_release(ht);
2836 2754 XPV_ALLOW_MIGRATE();
2837 2755 return (pfn);
2838 2756 }
2839 2757
2840 2758 /*
2841 2759 * int hat_probe(hat, addr)
2842 2760 * return 0 if no valid mapping is present. Faster version
2843 2761 * of hat_getattr in certain architectures.
2844 2762 */
2845 2763 int
2846 2764 hat_probe(hat_t *hat, caddr_t addr)
2847 2765 {
2848 2766 uintptr_t vaddr = ALIGN2PAGE(addr);
2849 2767 uint_t entry;
2850 2768 htable_t *ht;
2851 2769 pgcnt_t pg_off;
2852 2770
2853 2771 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2854 2772 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
2855 2773 if (IN_VA_HOLE(vaddr))
2856 2774 return (0);
2857 2775
2858 2776 /*
2859 2777 * Most common use of hat_probe is from segmap. We special case it
2860 2778 * for performance.
2861 2779 */
2862 2780 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) {
2863 2781 pg_off = mmu_btop(vaddr - mmu.kmap_addr);
2864 2782 if (mmu.pae_hat)
2865 2783 return (PTE_ISVALID(mmu.kmap_ptes[pg_off]));
2866 2784 else
2867 2785 return (PTE_ISVALID(
2868 2786 ((x86pte32_t *)mmu.kmap_ptes)[pg_off]));
2869 2787 }
2870 2788
2871 2789 ht = htable_getpage(hat, vaddr, &entry);
2872 2790 htable_release(ht);
2873 2791 return (ht != NULL);
2874 2792 }
2875 2793
2876 2794 /*
2877 2795 * Find out if the segment for hat_share()/hat_unshare() is DISM or locked ISM.
2878 2796 */
2879 2797 static int
2880 2798 is_it_dism(hat_t *hat, caddr_t va)
2881 2799 {
2882 2800 struct seg *seg;
2883 2801 struct shm_data *shmd;
2884 2802 struct spt_data *sptd;
2885 2803
2886 2804 seg = as_findseg(hat->hat_as, va, 0);
2887 2805 ASSERT(seg != NULL);
2888 2806 ASSERT(seg->s_base <= va);
2889 2807 shmd = (struct shm_data *)seg->s_data;
2890 2808 ASSERT(shmd != NULL);
2891 2809 sptd = (struct spt_data *)shmd->shm_sptseg->s_data;
2892 2810 ASSERT(sptd != NULL);
2893 2811 if (sptd->spt_flags & SHM_PAGEABLE)
2894 2812 return (1);
2895 2813 return (0);
2896 2814 }
2897 2815
2898 2816 /*
2899 2817 * Simple implementation of ISM. hat_share() is similar to hat_memload_array(),
2900 2818 * except that we use the ism_hat's existing mappings to determine the pages
2901 2819 * and protections to use for this hat. If we find a full properly aligned
2902 2820 * and sized pagetable, we will attempt to share the pagetable itself.
2903 2821 */
2904 2822 /*ARGSUSED*/
2905 2823 int
2906 2824 hat_share(
2907 2825 hat_t *hat,
2908 2826 caddr_t addr,
2909 2827 hat_t *ism_hat,
2910 2828 caddr_t src_addr,
2911 2829 size_t len, /* almost useless value, see below.. */
2912 2830 uint_t ismszc)
2913 2831 {
2914 2832 uintptr_t vaddr_start = (uintptr_t)addr;
2915 2833 uintptr_t vaddr;
2916 2834 uintptr_t eaddr = vaddr_start + len;
2917 2835 uintptr_t ism_addr_start = (uintptr_t)src_addr;
2918 2836 uintptr_t ism_addr = ism_addr_start;
2919 2837 uintptr_t e_ism_addr = ism_addr + len;
2920 2838 htable_t *ism_ht = NULL;
2921 2839 htable_t *ht;
2922 2840 x86pte_t pte;
2923 2841 page_t *pp;
2924 2842 pfn_t pfn;
2925 2843 level_t l;
2926 2844 pgcnt_t pgcnt;
2927 2845 uint_t prot;
2928 2846 int is_dism;
2929 2847 int flags;
2930 2848
2931 2849 /*
2932 2850 * We might be asked to share an empty DISM hat by as_dup()
2933 2851 */
2934 2852 ASSERT(hat != kas.a_hat);
2935 2853 ASSERT(eaddr <= _userlimit);
2936 2854 if (!(ism_hat->hat_flags & HAT_SHARED)) {
2937 2855 ASSERT(hat_get_mapped_size(ism_hat) == 0);
2938 2856 return (0);
2939 2857 }
2940 2858 XPV_DISALLOW_MIGRATE();
2941 2859
2942 2860 /*
2943 2861 * The SPT segment driver often passes us a size larger than there are
2944 2862 * valid mappings. That's because it rounds the segment size up to a
2945 2863 * large pagesize, even if the actual memory mapped by ism_hat is less.
2946 2864 */
2947 2865 ASSERT(IS_PAGEALIGNED(vaddr_start));
2948 2866 ASSERT(IS_PAGEALIGNED(ism_addr_start));
2949 2867 ASSERT(ism_hat->hat_flags & HAT_SHARED);
2950 2868 is_dism = is_it_dism(hat, addr);
2951 2869 while (ism_addr < e_ism_addr) {
2952 2870 /*
2953 2871 * use htable_walk to get the next valid ISM mapping
2954 2872 */
2955 2873 pte = htable_walk(ism_hat, &ism_ht, &ism_addr, e_ism_addr);
2956 2874 if (ism_ht == NULL)
2957 2875 break;
2958 2876
2959 2877 /*
2960 2878 * First check to see if we already share the page table.
2961 2879 */
2962 2880 l = ism_ht->ht_level;
2963 2881 vaddr = vaddr_start + (ism_addr - ism_addr_start);
2964 2882 ht = htable_lookup(hat, vaddr, l);
2965 2883 if (ht != NULL) {
2966 2884 if (ht->ht_flags & HTABLE_SHARED_PFN)
2967 2885 goto shared;
2968 2886 htable_release(ht);
2969 2887 goto not_shared;
2970 2888 }
2971 2889
2972 2890 /*
2973 2891 * Can't ever share top table.
2974 2892 */
2975 2893 if (l == mmu.max_level)
2976 2894 goto not_shared;
2977 2895
2978 2896 /*
2979 2897 * Avoid level mismatches later due to DISM faults.
2980 2898 */
2981 2899 if (is_dism && l > 0)
2982 2900 goto not_shared;
2983 2901
2984 2902 /*
2985 2903 * addresses and lengths must align
2986 2904 * table must be fully populated
2987 2905 * no lower level page tables
2988 2906 */
2989 2907 if (ism_addr != ism_ht->ht_vaddr ||
2990 2908 (vaddr & LEVEL_OFFSET(l + 1)) != 0)
2991 2909 goto not_shared;
2992 2910
2993 2911 /*
2994 2912 * The range of address space must cover a full table.
2995 2913 */
2996 2914 if (e_ism_addr - ism_addr < LEVEL_SIZE(l + 1))
2997 2915 goto not_shared;
2998 2916
2999 2917 /*
3000 2918 * All entries in the ISM page table must be leaf PTEs.
3001 2919 */
3002 2920 if (l > 0) {
3003 2921 int e;
3004 2922
3005 2923 /*
3006 2924 * We know the 0th is from htable_walk() above.
3007 2925 */
3008 2926 for (e = 1; e < HTABLE_NUM_PTES(ism_ht); ++e) {
3009 2927 x86pte_t pte;
3010 2928 pte = x86pte_get(ism_ht, e);
3011 2929 if (!PTE_ISPAGE(pte, l))
3012 2930 goto not_shared;
3013 2931 }
3014 2932 }
3015 2933
3016 2934 /*
3017 2935 * share the page table
3018 2936 */
3019 2937 ht = htable_create(hat, vaddr, l, ism_ht);
3020 2938 shared:
3021 2939 ASSERT(ht->ht_flags & HTABLE_SHARED_PFN);
3022 2940 ASSERT(ht->ht_shares == ism_ht);
3023 2941 hat->hat_ism_pgcnt +=
3024 2942 (ism_ht->ht_valid_cnt - ht->ht_valid_cnt) <<
3025 2943 (LEVEL_SHIFT(ht->ht_level) - MMU_PAGESHIFT);
3026 2944 ht->ht_valid_cnt = ism_ht->ht_valid_cnt;
3027 2945 htable_release(ht);
3028 2946 ism_addr = ism_ht->ht_vaddr + LEVEL_SIZE(l + 1);
3029 2947 htable_release(ism_ht);
3030 2948 ism_ht = NULL;
3031 2949 continue;
3032 2950
3033 2951 not_shared:
3034 2952 /*
3035 2953 * Unable to share the page table. Instead we will
3036 2954 * create new mappings from the values in the ISM mappings.
3037 2955 * Figure out what level size mappings to use;
3038 2956 */
3039 2957 for (l = ism_ht->ht_level; l > 0; --l) {
3040 2958 if (LEVEL_SIZE(l) <= eaddr - vaddr &&
3041 2959 (vaddr & LEVEL_OFFSET(l)) == 0)
3042 2960 break;
3043 2961 }
3044 2962
3045 2963 /*
3046 2964 * The ISM mapping might be larger than the share area,
3047 2965 * be careful to truncate it if needed.
3048 2966 */
3049 2967 if (eaddr - vaddr >= LEVEL_SIZE(ism_ht->ht_level)) {
3050 2968 pgcnt = mmu_btop(LEVEL_SIZE(ism_ht->ht_level));
3051 2969 } else {
3052 2970 pgcnt = mmu_btop(eaddr - vaddr);
3053 2971 l = 0;
3054 2972 }
3055 2973
3056 2974 pfn = PTE2PFN(pte, ism_ht->ht_level);
3057 2975 ASSERT(pfn != PFN_INVALID);
3058 2976 while (pgcnt > 0) {
3059 2977 /*
3060 2978 * Make a new pte for the PFN for this level.
3061 2979 * Copy protections for the pte from the ISM pte.
3062 2980 */
3063 2981 pp = page_numtopp_nolock(pfn);
3064 2982 ASSERT(pp != NULL);
3065 2983
3066 2984 prot = PROT_USER | PROT_READ | HAT_UNORDERED_OK;
3067 2985 if (PTE_GET(pte, PT_WRITABLE))
3068 2986 prot |= PROT_WRITE;
3069 2987 if (!PTE_GET(pte, PT_NX))
3070 2988 prot |= PROT_EXEC;
3071 2989
3072 2990 flags = HAT_LOAD;
3073 2991 if (!is_dism)
3074 2992 flags |= HAT_LOAD_LOCK | HAT_LOAD_NOCONSIST;
3075 2993 while (hati_load_common(hat, vaddr, pp, prot, flags,
3076 2994 l, pfn) != 0) {
3077 2995 if (l == 0)
3078 2996 panic("hati_load_common() failure");
3079 2997 --l;
3080 2998 }
3081 2999
3082 3000 vaddr += LEVEL_SIZE(l);
3083 3001 ism_addr += LEVEL_SIZE(l);
3084 3002 pfn += mmu_btop(LEVEL_SIZE(l));
3085 3003 pgcnt -= mmu_btop(LEVEL_SIZE(l));
3086 3004 }
3087 3005 }
3088 3006 if (ism_ht != NULL)
3089 3007 htable_release(ism_ht);
3090 3008 XPV_ALLOW_MIGRATE();
3091 3009 return (0);
3092 3010 }
3093 3011
3094 3012
3095 3013 /*
3096 3014 * hat_unshare() is similar to hat_unload_callback(), but
3097 3015 * we have to look for empty shared pagetables. Note that
3098 3016 * hat_unshare() is always invoked against an entire segment.
3099 3017 */
3100 3018 /*ARGSUSED*/
3101 3019 void
3102 3020 hat_unshare(hat_t *hat, caddr_t addr, size_t len, uint_t ismszc)
3103 3021 {
3104 3022 uint64_t vaddr = (uintptr_t)addr;
3105 3023 uintptr_t eaddr = vaddr + len;
3106 3024 htable_t *ht = NULL;
3107 3025 uint_t need_demaps = 0;
3108 3026 int flags = HAT_UNLOAD_UNMAP;
3109 3027 level_t l;
3110 3028
3111 3029 ASSERT(hat != kas.a_hat);
3112 3030 ASSERT(eaddr <= _userlimit);
3113 3031 ASSERT(IS_PAGEALIGNED(vaddr));
3114 3032 ASSERT(IS_PAGEALIGNED(eaddr));
3115 3033 XPV_DISALLOW_MIGRATE();
3116 3034
3117 3035 /*
3118 3036 * First go through and remove any shared pagetables.
3119 3037 *
3120 3038 * Note that it's ok to delay the TLB shootdown till the entire range is
3121 3039 * finished, because if hat_pageunload() were to unload a shared
3122 3040 * pagetable page, its hat_tlb_inval() will do a global TLB invalidate.
3123 3041 */
3124 3042 l = mmu.max_page_level;
3125 3043 if (l == mmu.max_level)
3126 3044 --l;
3127 3045 for (; l >= 0; --l) {
3128 3046 for (vaddr = (uintptr_t)addr; vaddr < eaddr;
3129 3047 vaddr = (vaddr & LEVEL_MASK(l + 1)) + LEVEL_SIZE(l + 1)) {
3130 3048 ASSERT(!IN_VA_HOLE(vaddr));
3131 3049 /*
3132 3050 * find a pagetable that maps the current address
3133 3051 */
3134 3052 ht = htable_lookup(hat, vaddr, l);
3135 3053 if (ht == NULL)
3136 3054 continue;
3137 3055 if (ht->ht_flags & HTABLE_SHARED_PFN) {
3138 3056 /*
3139 3057 * clear page count, set valid_cnt to 0,
3140 3058 * let htable_release() finish the job
3141 3059 */
3142 3060 hat->hat_ism_pgcnt -= ht->ht_valid_cnt <<
3143 3061 (LEVEL_SHIFT(ht->ht_level) - MMU_PAGESHIFT);
3144 3062 ht->ht_valid_cnt = 0;
3145 3063 need_demaps = 1;
3146 3064 }
3147 3065 htable_release(ht);
3148 3066 }
3149 3067 }
3150 3068
3151 3069 /*
3152 3070 * flush the TLBs - since we're probably dealing with MANY mappings
3153 3071 * we do just one CR3 reload.
3154 3072 */
3155 3073 if (!(hat->hat_flags & HAT_FREEING) && need_demaps)
3156 3074 hat_tlb_inval(hat, DEMAP_ALL_ADDR);
3157 3075
3158 3076 /*
3159 3077 * Now go back and clean up any unaligned mappings that
3160 3078 * couldn't share pagetables.
3161 3079 */
3162 3080 if (!is_it_dism(hat, addr))
3163 3081 flags |= HAT_UNLOAD_UNLOCK;
3164 3082 hat_unload(hat, addr, len, flags);
3165 3083 XPV_ALLOW_MIGRATE();
3166 3084 }
3167 3085
3168 3086
3169 3087 /*
3170 3088 * hat_reserve() does nothing
3171 3089 */
3172 3090 /*ARGSUSED*/
3173 3091 void
3174 3092 hat_reserve(struct as *as, caddr_t addr, size_t len)
3175 3093 {
3176 3094 }
3177 3095
3178 3096
3179 3097 /*
3180 3098 * Called when all mappings to a page should have write permission removed.
3181 3099 * Mostly stolen from hat_pagesync()
3182 3100 */
3183 3101 static void
3184 3102 hati_page_clrwrt(struct page *pp)
3185 3103 {
3186 3104 hment_t *hm = NULL;
3187 3105 htable_t *ht;
3188 3106 uint_t entry;
3189 3107 x86pte_t old;
3190 3108 x86pte_t new;
3191 3109 uint_t pszc = 0;
3192 3110
3193 3111 XPV_DISALLOW_MIGRATE();
3194 3112 next_size:
3195 3113 /*
3196 3114 * walk thru the mapping list clearing write permission
3197 3115 */
3198 3116 x86_hm_enter(pp);
3199 3117 while ((hm = hment_walk(pp, &ht, &entry, hm)) != NULL) {
3200 3118 if (ht->ht_level < pszc)
3201 3119 continue;
3202 3120 old = x86pte_get(ht, entry);
3203 3121
3204 3122 for (;;) {
3205 3123 /*
3206 3124 * Is this mapping of interest?
3207 3125 */
3208 3126 if (PTE2PFN(old, ht->ht_level) != pp->p_pagenum ||
3209 3127 PTE_GET(old, PT_WRITABLE) == 0)
3210 3128 break;
3211 3129
3212 3130 /*
3213 3131 * Clear ref/mod writable bits. This requires cross
3214 3132 * calls to ensure any executing TLBs see cleared bits.
3215 3133 */
3216 3134 new = old;
3217 3135 PTE_CLR(new, PT_REF | PT_MOD | PT_WRITABLE);
3218 3136 old = hati_update_pte(ht, entry, old, new);
3219 3137 if (old != 0)
3220 3138 continue;
3221 3139
3222 3140 break;
3223 3141 }
3224 3142 }
3225 3143 x86_hm_exit(pp);
3226 3144 while (pszc < pp->p_szc) {
3227 3145 page_t *tpp;
3228 3146 pszc++;
3229 3147 tpp = PP_GROUPLEADER(pp, pszc);
3230 3148 if (pp != tpp) {
3231 3149 pp = tpp;
3232 3150 goto next_size;
3233 3151 }
3234 3152 }
3235 3153 XPV_ALLOW_MIGRATE();
3236 3154 }
3237 3155
3238 3156 /*
3239 3157 * void hat_page_setattr(pp, flag)
3240 3158 * void hat_page_clrattr(pp, flag)
3241 3159 * used to set/clr ref/mod bits.
3242 3160 */
3243 3161 void
3244 3162 hat_page_setattr(struct page *pp, uint_t flag)
3245 3163 {
3246 3164 vnode_t *vp = pp->p_vnode;
3247 3165 kmutex_t *vphm = NULL;
3248 3166 page_t **listp;
3249 3167 int noshuffle;
3250 3168
3251 3169 noshuffle = flag & P_NSH;
3252 3170 flag &= ~P_NSH;
3253 3171
3254 3172 if (PP_GETRM(pp, flag) == flag)
3255 3173 return;
3256 3174
3257 3175 if ((flag & P_MOD) != 0 && vp != NULL && IS_VMODSORT(vp) &&
3258 3176 !noshuffle) {
3259 3177 vphm = page_vnode_mutex(vp);
3260 3178 mutex_enter(vphm);
3261 3179 }
3262 3180
3263 3181 PP_SETRM(pp, flag);
3264 3182
3265 3183 if (vphm != NULL) {
3266 3184
3267 3185 /*
3268 3186 * Some File Systems examine v_pages for NULL w/o
3269 3187 * grabbing the vphm mutex. Must not let it become NULL when
3270 3188 * pp is the only page on the list.
3271 3189 */
3272 3190 if (pp->p_vpnext != pp) {
3273 3191 page_vpsub(&vp->v_pages, pp);
3274 3192 if (vp->v_pages != NULL)
3275 3193 listp = &vp->v_pages->p_vpprev->p_vpnext;
3276 3194 else
3277 3195 listp = &vp->v_pages;
3278 3196 page_vpadd(listp, pp);
3279 3197 }
3280 3198 mutex_exit(vphm);
3281 3199 }
3282 3200 }
3283 3201
3284 3202 void
3285 3203 hat_page_clrattr(struct page *pp, uint_t flag)
3286 3204 {
3287 3205 vnode_t *vp = pp->p_vnode;
3288 3206 ASSERT(!(flag & ~(P_MOD | P_REF | P_RO)));
3289 3207
3290 3208 /*
3291 3209 * Caller is expected to hold page's io lock for VMODSORT to work
3292 3210 * correctly with pvn_vplist_dirty() and pvn_getdirty() when mod
3293 3211 * bit is cleared.
3294 3212 * We don't have assert to avoid tripping some existing third party
3295 3213 * code. The dirty page is moved back to top of the v_page list
3296 3214 * after IO is done in pvn_write_done().
3297 3215 */
3298 3216 PP_CLRRM(pp, flag);
3299 3217
3300 3218 if ((flag & P_MOD) != 0 && vp != NULL && IS_VMODSORT(vp)) {
3301 3219
3302 3220 /*
3303 3221 * VMODSORT works by removing write permissions and getting
3304 3222 * a fault when a page is made dirty. At this point
3305 3223 * we need to remove write permission from all mappings
3306 3224 * to this page.
3307 3225 */
3308 3226 hati_page_clrwrt(pp);
3309 3227 }
3310 3228 }
3311 3229
3312 3230 /*
3313 3231 * If flag is specified, returns 0 if attribute is disabled
3314 3232 * and non zero if enabled. If flag specifes multiple attributes
3315 3233 * then returns 0 if ALL attributes are disabled. This is an advisory
3316 3234 * call.
3317 3235 */
3318 3236 uint_t
3319 3237 hat_page_getattr(struct page *pp, uint_t flag)
3320 3238 {
3321 3239 return (PP_GETRM(pp, flag));
3322 3240 }
3323 3241
3324 3242
3325 3243 /*
3326 3244 * common code used by hat_pageunload() and hment_steal()
3327 3245 */
3328 3246 hment_t *
3329 3247 hati_page_unmap(page_t *pp, htable_t *ht, uint_t entry)
3330 3248 {
3331 3249 x86pte_t old_pte;
3332 3250 pfn_t pfn = pp->p_pagenum;
3333 3251 hment_t *hm;
3334 3252
3335 3253 /*
3336 3254 * We need to acquire a hold on the htable in order to
3337 3255 * do the invalidate. We know the htable must exist, since
3338 3256 * unmap's don't release the htable until after removing any
3339 3257 * hment. Having x86_hm_enter() keeps that from proceeding.
3340 3258 */
3341 3259 htable_acquire(ht);
3342 3260
3343 3261 /*
3344 3262 * Invalidate the PTE and remove the hment.
3345 3263 */
3346 3264 old_pte = x86pte_inval(ht, entry, 0, NULL, B_TRUE);
3347 3265 if (PTE2PFN(old_pte, ht->ht_level) != pfn) {
3348 3266 panic("x86pte_inval() failure found PTE = " FMT_PTE
3349 3267 " pfn being unmapped is %lx ht=0x%lx entry=0x%x",
3350 3268 old_pte, pfn, (uintptr_t)ht, entry);
3351 3269 }
3352 3270
3353 3271 /*
3354 3272 * Clean up all the htable information for this mapping
3355 3273 */
3356 3274 ASSERT(ht->ht_valid_cnt > 0);
3357 3275 HTABLE_DEC(ht->ht_valid_cnt);
3358 3276 PGCNT_DEC(ht->ht_hat, ht->ht_level);
3359 3277
3360 3278 /*
3361 3279 * sync ref/mod bits to the page_t
3362 3280 */
3363 3281 if (PTE_GET(old_pte, PT_SOFTWARE) < PT_NOSYNC)
3364 3282 hati_sync_pte_to_page(pp, old_pte, ht->ht_level);
3365 3283
3366 3284 /*
3367 3285 * Remove the mapping list entry for this page.
3368 3286 */
3369 3287 hm = hment_remove(pp, ht, entry);
3370 3288
3371 3289 /*
3372 3290 * drop the mapping list lock so that we might free the
3373 3291 * hment and htable.
3374 3292 */
3375 3293 x86_hm_exit(pp);
3376 3294 htable_release(ht);
3377 3295 return (hm);
3378 3296 }
3379 3297
3380 3298 extern int vpm_enable;
3381 3299 /*
3382 3300 * Unload all translations to a page. If the page is a subpage of a large
3383 3301 * page, the large page mappings are also removed.
3384 3302 *
3385 3303 * The forceflags are unused.
3386 3304 */
3387 3305
3388 3306 /*ARGSUSED*/
3389 3307 static int
3390 3308 hati_pageunload(struct page *pp, uint_t pg_szcd, uint_t forceflag)
3391 3309 {
3392 3310 page_t *cur_pp = pp;
3393 3311 hment_t *hm;
3394 3312 hment_t *prev;
3395 3313 htable_t *ht;
3396 3314 uint_t entry;
3397 3315 level_t level;
3398 3316
3399 3317 XPV_DISALLOW_MIGRATE();
3400 3318
3401 3319 /*
3402 3320 * prevent recursion due to kmem_free()
3403 3321 */
3404 3322 ++curthread->t_hatdepth;
3405 3323 ASSERT(curthread->t_hatdepth < 16);
3406 3324
3407 3325 #if defined(__amd64)
3408 3326 /*
3409 3327 * clear the vpm ref.
3410 3328 */
3411 3329 if (vpm_enable) {
3412 3330 pp->p_vpmref = 0;
3413 3331 }
3414 3332 #endif
3415 3333 /*
3416 3334 * The loop with next_size handles pages with multiple pagesize mappings
3417 3335 */
3418 3336 next_size:
3419 3337 for (;;) {
3420 3338
3421 3339 /*
3422 3340 * Get a mapping list entry
3423 3341 */
3424 3342 x86_hm_enter(cur_pp);
3425 3343 for (prev = NULL; ; prev = hm) {
3426 3344 hm = hment_walk(cur_pp, &ht, &entry, prev);
3427 3345 if (hm == NULL) {
3428 3346 x86_hm_exit(cur_pp);
3429 3347
3430 3348 /*
3431 3349 * If not part of a larger page, we're done.
3432 3350 */
3433 3351 if (cur_pp->p_szc <= pg_szcd) {
3434 3352 ASSERT(curthread->t_hatdepth > 0);
3435 3353 --curthread->t_hatdepth;
3436 3354 XPV_ALLOW_MIGRATE();
3437 3355 return (0);
3438 3356 }
3439 3357
3440 3358 /*
3441 3359 * Else check the next larger page size.
3442 3360 * hat_page_demote() may decrease p_szc
3443 3361 * but that's ok we'll just take an extra
3444 3362 * trip discover there're no larger mappings
3445 3363 * and return.
3446 3364 */
3447 3365 ++pg_szcd;
3448 3366 cur_pp = PP_GROUPLEADER(cur_pp, pg_szcd);
3449 3367 goto next_size;
3450 3368 }
3451 3369
3452 3370 /*
3453 3371 * If this mapping size matches, remove it.
3454 3372 */
3455 3373 level = ht->ht_level;
3456 3374 if (level == pg_szcd)
3457 3375 break;
3458 3376 }
3459 3377
3460 3378 /*
3461 3379 * Remove the mapping list entry for this page.
3462 3380 * Note this does the x86_hm_exit() for us.
3463 3381 */
3464 3382 hm = hati_page_unmap(cur_pp, ht, entry);
3465 3383 if (hm != NULL)
3466 3384 hment_free(hm);
3467 3385 }
3468 3386 }
3469 3387
3470 3388 int
3471 3389 hat_pageunload(struct page *pp, uint_t forceflag)
3472 3390 {
3473 3391 ASSERT(PAGE_EXCL(pp));
3474 3392 return (hati_pageunload(pp, 0, forceflag));
3475 3393 }
3476 3394
3477 3395 /*
3478 3396 * Unload all large mappings to pp and reduce by 1 p_szc field of every large
3479 3397 * page level that included pp.
3480 3398 *
3481 3399 * pp must be locked EXCL. Even though no other constituent pages are locked
3482 3400 * it's legal to unload large mappings to pp because all constituent pages of
3483 3401 * large locked mappings have to be locked SHARED. therefore if we have EXCL
3484 3402 * lock on one of constituent pages none of the large mappings to pp are
3485 3403 * locked.
3486 3404 *
3487 3405 * Change (always decrease) p_szc field starting from the last constituent
3488 3406 * page and ending with root constituent page so that root's pszc always shows
3489 3407 * the area where hat_page_demote() may be active.
3490 3408 *
3491 3409 * This mechanism is only used for file system pages where it's not always
3492 3410 * possible to get EXCL locks on all constituent pages to demote the size code
3493 3411 * (as is done for anonymous or kernel large pages).
3494 3412 */
3495 3413 void
3496 3414 hat_page_demote(page_t *pp)
3497 3415 {
3498 3416 uint_t pszc;
3499 3417 uint_t rszc;
3500 3418 uint_t szc;
3501 3419 page_t *rootpp;
3502 3420 page_t *firstpp;
3503 3421 page_t *lastpp;
3504 3422 pgcnt_t pgcnt;
3505 3423
3506 3424 ASSERT(PAGE_EXCL(pp));
3507 3425 ASSERT(!PP_ISFREE(pp));
3508 3426 ASSERT(page_szc_lock_assert(pp));
3509 3427
3510 3428 if (pp->p_szc == 0)
3511 3429 return;
3512 3430
3513 3431 rootpp = PP_GROUPLEADER(pp, 1);
3514 3432 (void) hati_pageunload(rootpp, 1, HAT_FORCE_PGUNLOAD);
3515 3433
3516 3434 /*
3517 3435 * all large mappings to pp are gone
3518 3436 * and no new can be setup since pp is locked exclusively.
3519 3437 *
3520 3438 * Lock the root to make sure there's only one hat_page_demote()
3521 3439 * outstanding within the area of this root's pszc.
3522 3440 *
3523 3441 * Second potential hat_page_demote() is already eliminated by upper
3524 3442 * VM layer via page_szc_lock() but we don't rely on it and use our
3525 3443 * own locking (so that upper layer locking can be changed without
3526 3444 * assumptions that hat depends on upper layer VM to prevent multiple
3527 3445 * hat_page_demote() to be issued simultaneously to the same large
3528 3446 * page).
3529 3447 */
3530 3448 again:
3531 3449 pszc = pp->p_szc;
3532 3450 if (pszc == 0)
3533 3451 return;
3534 3452 rootpp = PP_GROUPLEADER(pp, pszc);
3535 3453 x86_hm_enter(rootpp);
3536 3454 /*
3537 3455 * If root's p_szc is different from pszc we raced with another
3538 3456 * hat_page_demote(). Drop the lock and try to find the root again.
3539 3457 * If root's p_szc is greater than pszc previous hat_page_demote() is
3540 3458 * not done yet. Take and release mlist lock of root's root to wait
3541 3459 * for previous hat_page_demote() to complete.
3542 3460 */
3543 3461 if ((rszc = rootpp->p_szc) != pszc) {
3544 3462 x86_hm_exit(rootpp);
3545 3463 if (rszc > pszc) {
3546 3464 /* p_szc of a locked non free page can't increase */
3547 3465 ASSERT(pp != rootpp);
3548 3466
3549 3467 rootpp = PP_GROUPLEADER(rootpp, rszc);
3550 3468 x86_hm_enter(rootpp);
3551 3469 x86_hm_exit(rootpp);
3552 3470 }
3553 3471 goto again;
3554 3472 }
3555 3473 ASSERT(pp->p_szc == pszc);
3556 3474
3557 3475 /*
3558 3476 * Decrement by 1 p_szc of every constituent page of a region that
3559 3477 * covered pp. For example if original szc is 3 it gets changed to 2
3560 3478 * everywhere except in region 2 that covered pp. Region 2 that
3561 3479 * covered pp gets demoted to 1 everywhere except in region 1 that
3562 3480 * covered pp. The region 1 that covered pp is demoted to region
3563 3481 * 0. It's done this way because from region 3 we removed level 3
3564 3482 * mappings, from region 2 that covered pp we removed level 2 mappings
3565 3483 * and from region 1 that covered pp we removed level 1 mappings. All
3566 3484 * changes are done from from high pfn's to low pfn's so that roots
3567 3485 * are changed last allowing one to know the largest region where
3568 3486 * hat_page_demote() is stil active by only looking at the root page.
3569 3487 *
3570 3488 * This algorithm is implemented in 2 while loops. First loop changes
3571 3489 * p_szc of pages to the right of pp's level 1 region and second
3572 3490 * loop changes p_szc of pages of level 1 region that covers pp
3573 3491 * and all pages to the left of level 1 region that covers pp.
3574 3492 * In the first loop p_szc keeps dropping with every iteration
3575 3493 * and in the second loop it keeps increasing with every iteration.
3576 3494 *
3577 3495 * First loop description: Demote pages to the right of pp outside of
3578 3496 * level 1 region that covers pp. In every iteration of the while
3579 3497 * loop below find the last page of szc region and the first page of
3580 3498 * (szc - 1) region that is immediately to the right of (szc - 1)
3581 3499 * region that covers pp. From last such page to first such page
3582 3500 * change every page's szc to szc - 1. Decrement szc and continue
3583 3501 * looping until szc is 1. If pp belongs to the last (szc - 1) region
3584 3502 * of szc region skip to the next iteration.
3585 3503 */
3586 3504 szc = pszc;
3587 3505 while (szc > 1) {
3588 3506 lastpp = PP_GROUPLEADER(pp, szc);
3589 3507 pgcnt = page_get_pagecnt(szc);
3590 3508 lastpp += pgcnt - 1;
3591 3509 firstpp = PP_GROUPLEADER(pp, (szc - 1));
3592 3510 pgcnt = page_get_pagecnt(szc - 1);
3593 3511 if (lastpp - firstpp < pgcnt) {
3594 3512 szc--;
3595 3513 continue;
3596 3514 }
3597 3515 firstpp += pgcnt;
3598 3516 while (lastpp != firstpp) {
3599 3517 ASSERT(lastpp->p_szc == pszc);
3600 3518 lastpp->p_szc = szc - 1;
3601 3519 lastpp--;
3602 3520 }
3603 3521 firstpp->p_szc = szc - 1;
3604 3522 szc--;
3605 3523 }
3606 3524
3607 3525 /*
3608 3526 * Second loop description:
3609 3527 * First iteration changes p_szc to 0 of every
3610 3528 * page of level 1 region that covers pp.
3611 3529 * Subsequent iterations find last page of szc region
3612 3530 * immediately to the left of szc region that covered pp
3613 3531 * and first page of (szc + 1) region that covers pp.
3614 3532 * From last to first page change p_szc of every page to szc.
3615 3533 * Increment szc and continue looping until szc is pszc.
3616 3534 * If pp belongs to the fist szc region of (szc + 1) region
3617 3535 * skip to the next iteration.
3618 3536 *
3619 3537 */
3620 3538 szc = 0;
3621 3539 while (szc < pszc) {
3622 3540 firstpp = PP_GROUPLEADER(pp, (szc + 1));
3623 3541 if (szc == 0) {
3624 3542 pgcnt = page_get_pagecnt(1);
3625 3543 lastpp = firstpp + (pgcnt - 1);
3626 3544 } else {
3627 3545 lastpp = PP_GROUPLEADER(pp, szc);
3628 3546 if (firstpp == lastpp) {
3629 3547 szc++;
3630 3548 continue;
3631 3549 }
3632 3550 lastpp--;
3633 3551 pgcnt = page_get_pagecnt(szc);
3634 3552 }
3635 3553 while (lastpp != firstpp) {
3636 3554 ASSERT(lastpp->p_szc == pszc);
3637 3555 lastpp->p_szc = szc;
3638 3556 lastpp--;
3639 3557 }
3640 3558 firstpp->p_szc = szc;
3641 3559 if (firstpp == rootpp)
3642 3560 break;
3643 3561 szc++;
3644 3562 }
3645 3563 x86_hm_exit(rootpp);
3646 3564 }
3647 3565
3648 3566 /*
3649 3567 * get hw stats from hardware into page struct and reset hw stats
3650 3568 * returns attributes of page
3651 3569 * Flags for hat_pagesync, hat_getstat, hat_sync
3652 3570 *
3653 3571 * define HAT_SYNC_ZERORM 0x01
3654 3572 *
3655 3573 * Additional flags for hat_pagesync
3656 3574 *
3657 3575 * define HAT_SYNC_STOPON_REF 0x02
3658 3576 * define HAT_SYNC_STOPON_MOD 0x04
3659 3577 * define HAT_SYNC_STOPON_RM 0x06
3660 3578 * define HAT_SYNC_STOPON_SHARED 0x08
3661 3579 */
3662 3580 uint_t
3663 3581 hat_pagesync(struct page *pp, uint_t flags)
3664 3582 {
3665 3583 hment_t *hm = NULL;
3666 3584 htable_t *ht;
3667 3585 uint_t entry;
3668 3586 x86pte_t old, save_old;
3669 3587 x86pte_t new;
3670 3588 uchar_t nrmbits = P_REF|P_MOD|P_RO;
3671 3589 extern ulong_t po_share;
3672 3590 page_t *save_pp = pp;
3673 3591 uint_t pszc = 0;
3674 3592
3675 3593 ASSERT(PAGE_LOCKED(pp) || panicstr);
3676 3594
3677 3595 if (PP_ISRO(pp) && (flags & HAT_SYNC_STOPON_MOD))
3678 3596 return (pp->p_nrm & nrmbits);
3679 3597
3680 3598 if ((flags & HAT_SYNC_ZERORM) == 0) {
3681 3599
3682 3600 if ((flags & HAT_SYNC_STOPON_REF) != 0 && PP_ISREF(pp))
3683 3601 return (pp->p_nrm & nrmbits);
3684 3602
3685 3603 if ((flags & HAT_SYNC_STOPON_MOD) != 0 && PP_ISMOD(pp))
3686 3604 return (pp->p_nrm & nrmbits);
3687 3605
3688 3606 if ((flags & HAT_SYNC_STOPON_SHARED) != 0 &&
3689 3607 hat_page_getshare(pp) > po_share) {
3690 3608 if (PP_ISRO(pp))
3691 3609 PP_SETREF(pp);
3692 3610 return (pp->p_nrm & nrmbits);
3693 3611 }
3694 3612 }
3695 3613
3696 3614 XPV_DISALLOW_MIGRATE();
3697 3615 next_size:
3698 3616 /*
3699 3617 * walk thru the mapping list syncing (and clearing) ref/mod bits.
3700 3618 */
3701 3619 x86_hm_enter(pp);
3702 3620 while ((hm = hment_walk(pp, &ht, &entry, hm)) != NULL) {
3703 3621 if (ht->ht_level < pszc)
3704 3622 continue;
3705 3623 old = x86pte_get(ht, entry);
3706 3624 try_again:
3707 3625
3708 3626 ASSERT(PTE2PFN(old, ht->ht_level) == pp->p_pagenum);
3709 3627
3710 3628 if (PTE_GET(old, PT_REF | PT_MOD) == 0)
3711 3629 continue;
3712 3630
3713 3631 save_old = old;
3714 3632 if ((flags & HAT_SYNC_ZERORM) != 0) {
3715 3633
3716 3634 /*
3717 3635 * Need to clear ref or mod bits. Need to demap
3718 3636 * to make sure any executing TLBs see cleared bits.
3719 3637 */
3720 3638 new = old;
3721 3639 PTE_CLR(new, PT_REF | PT_MOD);
3722 3640 old = hati_update_pte(ht, entry, old, new);
3723 3641 if (old != 0)
3724 3642 goto try_again;
3725 3643
3726 3644 old = save_old;
3727 3645 }
3728 3646
3729 3647 /*
3730 3648 * Sync the PTE
3731 3649 */
3732 3650 if (!(flags & HAT_SYNC_ZERORM) &&
3733 3651 PTE_GET(old, PT_SOFTWARE) <= PT_NOSYNC)
3734 3652 hati_sync_pte_to_page(pp, old, ht->ht_level);
3735 3653
3736 3654 /*
3737 3655 * can stop short if we found a ref'd or mod'd page
3738 3656 */
3739 3657 if ((flags & HAT_SYNC_STOPON_MOD) && PP_ISMOD(save_pp) ||
3740 3658 (flags & HAT_SYNC_STOPON_REF) && PP_ISREF(save_pp)) {
3741 3659 x86_hm_exit(pp);
3742 3660 goto done;
3743 3661 }
3744 3662 }
3745 3663 x86_hm_exit(pp);
3746 3664 while (pszc < pp->p_szc) {
3747 3665 page_t *tpp;
3748 3666 pszc++;
3749 3667 tpp = PP_GROUPLEADER(pp, pszc);
3750 3668 if (pp != tpp) {
3751 3669 pp = tpp;
3752 3670 goto next_size;
3753 3671 }
3754 3672 }
3755 3673 done:
3756 3674 XPV_ALLOW_MIGRATE();
3757 3675 return (save_pp->p_nrm & nrmbits);
3758 3676 }
3759 3677
3760 3678 /*
3761 3679 * returns approx number of mappings to this pp. A return of 0 implies
3762 3680 * there are no mappings to the page.
3763 3681 */
3764 3682 ulong_t
3765 3683 hat_page_getshare(page_t *pp)
3766 3684 {
3767 3685 uint_t cnt;
3768 3686 cnt = hment_mapcnt(pp);
3769 3687 #if defined(__amd64)
3770 3688 if (vpm_enable && pp->p_vpmref) {
3771 3689 cnt += 1;
3772 3690 }
3773 3691 #endif
3774 3692 return (cnt);
3775 3693 }
3776 3694
3777 3695 /*
3778 3696 * Return 1 the number of mappings exceeds sh_thresh. Return 0
3779 3697 * otherwise.
3780 3698 */
3781 3699 int
3782 3700 hat_page_checkshare(page_t *pp, ulong_t sh_thresh)
3783 3701 {
3784 3702 return (hat_page_getshare(pp) > sh_thresh);
3785 3703 }
3786 3704
3787 3705 /*
3788 3706 * hat_softlock isn't supported anymore
3789 3707 */
3790 3708 /*ARGSUSED*/
3791 3709 faultcode_t
3792 3710 hat_softlock(
3793 3711 hat_t *hat,
3794 3712 caddr_t addr,
3795 3713 size_t *len,
3796 3714 struct page **page_array,
3797 3715 uint_t flags)
3798 3716 {
3799 3717 return (FC_NOSUPPORT);
3800 3718 }
3801 3719
3802 3720
3803 3721
3804 3722 /*
3805 3723 * Routine to expose supported HAT features to platform independent code.
3806 3724 */
3807 3725 /*ARGSUSED*/
3808 3726 int
3809 3727 hat_supported(enum hat_features feature, void *arg)
3810 3728 {
3811 3729 switch (feature) {
3812 3730
3813 3731 case HAT_SHARED_PT: /* this is really ISM */
3814 3732 return (1);
3815 3733
3816 3734 case HAT_DYNAMIC_ISM_UNMAP:
3817 3735 return (0);
3818 3736
3819 3737 case HAT_VMODSORT:
3820 3738 return (1);
3821 3739
3822 3740 case HAT_SHARED_REGIONS:
3823 3741 return (0);
3824 3742
3825 3743 default:
3826 3744 panic("hat_supported() - unknown feature");
3827 3745 }
3828 3746 return (0);
3829 3747 }
3830 3748
3831 3749 /*
3832 3750 * Called when a thread is exiting and has been switched to the kernel AS
3833 3751 */
3834 3752 void
3835 3753 hat_thread_exit(kthread_t *thd)
3836 3754 {
3837 3755 ASSERT(thd->t_procp->p_as == &kas);
3838 3756 XPV_DISALLOW_MIGRATE();
3839 3757 hat_switch(thd->t_procp->p_as->a_hat);
3840 3758 XPV_ALLOW_MIGRATE();
3841 3759 }
3842 3760
3843 3761 /*
3844 3762 * Setup the given brand new hat structure as the new HAT on this cpu's mmu.
3845 3763 */
3846 3764 /*ARGSUSED*/
3847 3765 void
3848 3766 hat_setup(hat_t *hat, int flags)
3849 3767 {
3850 3768 XPV_DISALLOW_MIGRATE();
3851 3769 kpreempt_disable();
3852 3770
3853 3771 hat_switch(hat);
3854 3772
3855 3773 kpreempt_enable();
3856 3774 XPV_ALLOW_MIGRATE();
3857 3775 }
3858 3776
3859 3777 /*
3860 3778 * Prepare for a CPU private mapping for the given address.
3861 3779 *
3862 3780 * The address can only be used from a single CPU and can be remapped
3863 3781 * using hat_mempte_remap(). Return the address of the PTE.
3864 3782 *
3865 3783 * We do the htable_create() if necessary and increment the valid count so
3866 3784 * the htable can't disappear. We also hat_devload() the page table into
3867 3785 * kernel so that the PTE is quickly accessed.
3868 3786 */
3869 3787 hat_mempte_t
3870 3788 hat_mempte_setup(caddr_t addr)
3871 3789 {
3872 3790 uintptr_t va = (uintptr_t)addr;
3873 3791 htable_t *ht;
3874 3792 uint_t entry;
3875 3793 x86pte_t oldpte;
3876 3794 hat_mempte_t p;
3877 3795
3878 3796 ASSERT(IS_PAGEALIGNED(va));
3879 3797 ASSERT(!IN_VA_HOLE(va));
3880 3798 ++curthread->t_hatdepth;
3881 3799 XPV_DISALLOW_MIGRATE();
3882 3800 ht = htable_getpte(kas.a_hat, va, &entry, &oldpte, 0);
3883 3801 if (ht == NULL) {
3884 3802 ht = htable_create(kas.a_hat, va, 0, NULL);
3885 3803 entry = htable_va2entry(va, ht);
3886 3804 ASSERT(ht->ht_level == 0);
3887 3805 oldpte = x86pte_get(ht, entry);
3888 3806 }
3889 3807 if (PTE_ISVALID(oldpte))
3890 3808 panic("hat_mempte_setup(): address already mapped"
3891 3809 "ht=%p, entry=%d, pte=" FMT_PTE, (void *)ht, entry, oldpte);
3892 3810
3893 3811 /*
3894 3812 * increment ht_valid_cnt so that the pagetable can't disappear
3895 3813 */
3896 3814 HTABLE_INC(ht->ht_valid_cnt);
3897 3815
3898 3816 /*
3899 3817 * return the PTE physical address to the caller.
3900 3818 */
3901 3819 htable_release(ht);
3902 3820 XPV_ALLOW_MIGRATE();
3903 3821 p = PT_INDEX_PHYSADDR(pfn_to_pa(ht->ht_pfn), entry);
3904 3822 --curthread->t_hatdepth;
3905 3823 return (p);
3906 3824 }
3907 3825
3908 3826 /*
3909 3827 * Release a CPU private mapping for the given address.
3910 3828 * We decrement the htable valid count so it might be destroyed.
3911 3829 */
3912 3830 /*ARGSUSED1*/
3913 3831 void
3914 3832 hat_mempte_release(caddr_t addr, hat_mempte_t pte_pa)
3915 3833 {
3916 3834 htable_t *ht;
3917 3835
3918 3836 XPV_DISALLOW_MIGRATE();
3919 3837 /*
3920 3838 * invalidate any left over mapping and decrement the htable valid count
3921 3839 */
3922 3840 #ifdef __xpv
3923 3841 if (HYPERVISOR_update_va_mapping((uintptr_t)addr, 0,
3924 3842 UVMF_INVLPG | UVMF_LOCAL))
3925 3843 panic("HYPERVISOR_update_va_mapping() failed");
3926 3844 #else
3927 3845 {
3928 3846 x86pte_t *pteptr;
3929 3847
3930 3848 pteptr = x86pte_mapin(mmu_btop(pte_pa),
3931 3849 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL);
3932 3850 if (mmu.pae_hat)
3933 3851 *pteptr = 0;
3934 3852 else
3935 3853 *(x86pte32_t *)pteptr = 0;
3936 3854 mmu_tlbflush_entry(addr);
3937 3855 x86pte_mapout();
3938 3856 }
3939 3857 #endif
3940 3858
3941 3859 ht = htable_getpte(kas.a_hat, ALIGN2PAGE(addr), NULL, NULL, 0);
3942 3860 if (ht == NULL)
3943 3861 panic("hat_mempte_release(): invalid address");
3944 3862 ASSERT(ht->ht_level == 0);
3945 3863 HTABLE_DEC(ht->ht_valid_cnt);
3946 3864 htable_release(ht);
3947 3865 XPV_ALLOW_MIGRATE();
3948 3866 }
3949 3867
3950 3868 /*
3951 3869 * Apply a temporary CPU private mapping to a page. We flush the TLB only
3952 3870 * on this CPU, so this ought to have been called with preemption disabled.
3953 3871 */
3954 3872 void
3955 3873 hat_mempte_remap(
3956 3874 pfn_t pfn,
3957 3875 caddr_t addr,
3958 3876 hat_mempte_t pte_pa,
3959 3877 uint_t attr,
3960 3878 uint_t flags)
3961 3879 {
3962 3880 uintptr_t va = (uintptr_t)addr;
3963 3881 x86pte_t pte;
3964 3882
3965 3883 /*
3966 3884 * Remap the given PTE to the new page's PFN. Invalidate only
3967 3885 * on this CPU.
3968 3886 */
3969 3887 #ifdef DEBUG
3970 3888 htable_t *ht;
3971 3889 uint_t entry;
3972 3890
3973 3891 ASSERT(IS_PAGEALIGNED(va));
3974 3892 ASSERT(!IN_VA_HOLE(va));
3975 3893 ht = htable_getpte(kas.a_hat, va, &entry, NULL, 0);
3976 3894 ASSERT(ht != NULL);
3977 3895 ASSERT(ht->ht_level == 0);
3978 3896 ASSERT(ht->ht_valid_cnt > 0);
3979 3897 ASSERT(ht->ht_pfn == mmu_btop(pte_pa));
3980 3898 htable_release(ht);
3981 3899 #endif
3982 3900 XPV_DISALLOW_MIGRATE();
3983 3901 pte = hati_mkpte(pfn, attr, 0, flags);
3984 3902 #ifdef __xpv
3985 3903 if (HYPERVISOR_update_va_mapping(va, pte, UVMF_INVLPG | UVMF_LOCAL))
3986 3904 panic("HYPERVISOR_update_va_mapping() failed");
3987 3905 #else
3988 3906 {
3989 3907 x86pte_t *pteptr;
3990 3908
3991 3909 pteptr = x86pte_mapin(mmu_btop(pte_pa),
3992 3910 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL);
3993 3911 if (mmu.pae_hat)
3994 3912 *(x86pte_t *)pteptr = pte;
3995 3913 else
3996 3914 *(x86pte32_t *)pteptr = (x86pte32_t)pte;
3997 3915 mmu_tlbflush_entry(addr);
3998 3916 x86pte_mapout();
3999 3917 }
4000 3918 #endif
4001 3919 XPV_ALLOW_MIGRATE();
4002 3920 }
4003 3921
4004 3922
4005 3923
4006 3924 /*
4007 3925 * Hat locking functions
4008 3926 * XXX - these two functions are currently being used by hatstats
4009 3927 * they can be removed by using a per-as mutex for hatstats.
4010 3928 */
4011 3929 void
4012 3930 hat_enter(hat_t *hat)
4013 3931 {
4014 3932 mutex_enter(&hat->hat_mutex);
4015 3933 }
4016 3934
4017 3935 void
4018 3936 hat_exit(hat_t *hat)
4019 3937 {
4020 3938 mutex_exit(&hat->hat_mutex);
4021 3939 }
4022 3940
4023 3941 /*
4024 3942 * HAT part of cpu initialization.
4025 3943 */
4026 3944 void
4027 3945 hat_cpu_online(struct cpu *cpup)
4028 3946 {
4029 3947 if (cpup != CPU) {
4030 3948 x86pte_cpu_init(cpup);
4031 3949 hat_vlp_setup(cpup);
4032 3950 }
4033 3951 CPUSET_ATOMIC_ADD(khat_cpuset, cpup->cpu_id);
4034 3952 }
4035 3953
4036 3954 /*
4037 3955 * HAT part of cpu deletion.
4038 3956 * (currently, we only call this after the cpu is safely passivated.)
4039 3957 */
4040 3958 void
4041 3959 hat_cpu_offline(struct cpu *cpup)
4042 3960 {
4043 3961 ASSERT(cpup != CPU);
4044 3962
4045 3963 CPUSET_ATOMIC_DEL(khat_cpuset, cpup->cpu_id);
4046 3964 hat_vlp_teardown(cpup);
4047 3965 x86pte_cpu_fini(cpup);
4048 3966 }
4049 3967
4050 3968 /*
4051 3969 * Function called after all CPUs are brought online.
4052 3970 * Used to remove low address boot mappings.
4053 3971 */
4054 3972 void
4055 3973 clear_boot_mappings(uintptr_t low, uintptr_t high)
4056 3974 {
4057 3975 uintptr_t vaddr = low;
4058 3976 htable_t *ht = NULL;
4059 3977 level_t level;
4060 3978 uint_t entry;
4061 3979 x86pte_t pte;
4062 3980
4063 3981 /*
4064 3982 * On 1st CPU we can unload the prom mappings, basically we blow away
4065 3983 * all virtual mappings under _userlimit.
4066 3984 */
4067 3985 while (vaddr < high) {
4068 3986 pte = htable_walk(kas.a_hat, &ht, &vaddr, high);
4069 3987 if (ht == NULL)
4070 3988 break;
4071 3989
4072 3990 level = ht->ht_level;
4073 3991 entry = htable_va2entry(vaddr, ht);
4074 3992 ASSERT(level <= mmu.max_page_level);
4075 3993 ASSERT(PTE_ISPAGE(pte, level));
4076 3994
4077 3995 /*
4078 3996 * Unload the mapping from the page tables.
4079 3997 */
4080 3998 (void) x86pte_inval(ht, entry, 0, NULL, B_TRUE);
4081 3999 ASSERT(ht->ht_valid_cnt > 0);
4082 4000 HTABLE_DEC(ht->ht_valid_cnt);
4083 4001 PGCNT_DEC(ht->ht_hat, ht->ht_level);
4084 4002
4085 4003 vaddr += LEVEL_SIZE(ht->ht_level);
4086 4004 }
4087 4005 if (ht)
4088 4006 htable_release(ht);
4089 4007 }
4090 4008
4091 4009 /*
4092 4010 * Atomically update a new translation for a single page. If the
4093 4011 * currently installed PTE doesn't match the value we expect to find,
4094 4012 * it's not updated and we return the PTE we found.
4095 4013 *
4096 4014 * If activating nosync or NOWRITE and the page was modified we need to sync
4097 4015 * with the page_t. Also sync with page_t if clearing ref/mod bits.
4098 4016 */
4099 4017 static x86pte_t
4100 4018 hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected, x86pte_t new)
4101 4019 {
4102 4020 page_t *pp;
4103 4021 uint_t rm = 0;
4104 4022 x86pte_t replaced;
4105 4023
4106 4024 if (PTE_GET(expected, PT_SOFTWARE) < PT_NOSYNC &&
4107 4025 PTE_GET(expected, PT_MOD | PT_REF) &&
4108 4026 (PTE_GET(new, PT_NOSYNC) || !PTE_GET(new, PT_WRITABLE) ||
4109 4027 !PTE_GET(new, PT_MOD | PT_REF))) {
4110 4028
4111 4029 ASSERT(!pfn_is_foreign(PTE2PFN(expected, ht->ht_level)));
4112 4030 pp = page_numtopp_nolock(PTE2PFN(expected, ht->ht_level));
4113 4031 ASSERT(pp != NULL);
4114 4032 if (PTE_GET(expected, PT_MOD))
4115 4033 rm |= P_MOD;
4116 4034 if (PTE_GET(expected, PT_REF))
4117 4035 rm |= P_REF;
4118 4036 PTE_CLR(new, PT_MOD | PT_REF);
4119 4037 }
4120 4038
4121 4039 replaced = x86pte_update(ht, entry, expected, new);
4122 4040 if (replaced != expected)
4123 4041 return (replaced);
4124 4042
4125 4043 if (rm) {
4126 4044 /*
4127 4045 * sync to all constituent pages of a large page
4128 4046 */
4129 4047 pgcnt_t pgcnt = page_get_pagecnt(ht->ht_level);
4130 4048 ASSERT(IS_P2ALIGNED(pp->p_pagenum, pgcnt));
4131 4049 while (pgcnt-- > 0) {
4132 4050 /*
4133 4051 * hat_page_demote() can't decrease
4134 4052 * pszc below this mapping size
4135 4053 * since large mapping existed after we
4136 4054 * took mlist lock.
4137 4055 */
4138 4056 ASSERT(pp->p_szc >= ht->ht_level);
4139 4057 hat_page_setattr(pp, rm);
4140 4058 ++pp;
4141 4059 }
4142 4060 }
4143 4061
4144 4062 return (0);
4145 4063 }
4146 4064
4147 4065 /* ARGSUSED */
4148 4066 void
4149 4067 hat_join_srd(struct hat *hat, vnode_t *evp)
4150 4068 {
4151 4069 }
4152 4070
4153 4071 /* ARGSUSED */
4154 4072 hat_region_cookie_t
4155 4073 hat_join_region(struct hat *hat,
4156 4074 caddr_t r_saddr,
4157 4075 size_t r_size,
4158 4076 void *r_obj,
4159 4077 u_offset_t r_objoff,
4160 4078 uchar_t r_perm,
4161 4079 uchar_t r_pgszc,
4162 4080 hat_rgn_cb_func_t r_cb_function,
4163 4081 uint_t flags)
4164 4082 {
4165 4083 panic("No shared region support on x86");
4166 4084 return (HAT_INVALID_REGION_COOKIE);
4167 4085 }
4168 4086
4169 4087 /* ARGSUSED */
4170 4088 void
4171 4089 hat_leave_region(struct hat *hat, hat_region_cookie_t rcookie, uint_t flags)
4172 4090 {
4173 4091 panic("No shared region support on x86");
4174 4092 }
4175 4093
4176 4094 /* ARGSUSED */
4177 4095 void
4178 4096 hat_dup_region(struct hat *hat, hat_region_cookie_t rcookie)
4179 4097 {
4180 4098 panic("No shared region support on x86");
4181 4099 }
4182 4100
4183 4101
4184 4102 /*
4185 4103 * Kernel Physical Mapping (kpm) facility
4186 4104 *
4187 4105 * Most of the routines needed to support segkpm are almost no-ops on the
4188 4106 * x86 platform. We map in the entire segment when it is created and leave
4189 4107 * it mapped in, so there is no additional work required to set up and tear
4190 4108 * down individual mappings. All of these routines were created to support
4191 4109 * SPARC platforms that have to avoid aliasing in their virtually indexed
4192 4110 * caches.
4193 4111 *
4194 4112 * Most of the routines have sanity checks in them (e.g. verifying that the
4195 4113 * passed-in page is locked). We don't actually care about most of these
4196 4114 * checks on x86, but we leave them in place to identify problems in the
4197 4115 * upper levels.
4198 4116 */
4199 4117
4200 4118 /*
4201 4119 * Map in a locked page and return the vaddr.
4202 4120 */
4203 4121 /*ARGSUSED*/
4204 4122 caddr_t
4205 4123 hat_kpm_mapin(struct page *pp, struct kpme *kpme)
4206 4124 {
4207 4125 caddr_t vaddr;
4208 4126
4209 4127 #ifdef DEBUG
4210 4128 if (kpm_enable == 0) {
4211 4129 cmn_err(CE_WARN, "hat_kpm_mapin: kpm_enable not set\n");
4212 4130 return ((caddr_t)NULL);
4213 4131 }
4214 4132
4215 4133 if (pp == NULL || PAGE_LOCKED(pp) == 0) {
4216 4134 cmn_err(CE_WARN, "hat_kpm_mapin: pp zero or not locked\n");
4217 4135 return ((caddr_t)NULL);
4218 4136 }
4219 4137 #endif
4220 4138
4221 4139 vaddr = hat_kpm_page2va(pp, 1);
4222 4140
4223 4141 return (vaddr);
4224 4142 }
4225 4143
4226 4144 /*
4227 4145 * Mapout a locked page.
4228 4146 */
4229 4147 /*ARGSUSED*/
4230 4148 void
4231 4149 hat_kpm_mapout(struct page *pp, struct kpme *kpme, caddr_t vaddr)
4232 4150 {
4233 4151 #ifdef DEBUG
4234 4152 if (kpm_enable == 0) {
4235 4153 cmn_err(CE_WARN, "hat_kpm_mapout: kpm_enable not set\n");
4236 4154 return;
4237 4155 }
4238 4156
4239 4157 if (IS_KPM_ADDR(vaddr) == 0) {
4240 4158 cmn_err(CE_WARN, "hat_kpm_mapout: no kpm address\n");
4241 4159 return;
4242 4160 }
4243 4161
4244 4162 if (pp == NULL || PAGE_LOCKED(pp) == 0) {
4245 4163 cmn_err(CE_WARN, "hat_kpm_mapout: page zero or not locked\n");
4246 4164 return;
4247 4165 }
4248 4166 #endif
4249 4167 }
4250 4168
4251 4169 /*
4252 4170 * hat_kpm_mapin_pfn is used to obtain a kpm mapping for physical
4253 4171 * memory addresses that are not described by a page_t. It can
4254 4172 * also be used for normal pages that are not locked, but beware
4255 4173 * this is dangerous - no locking is performed, so the identity of
4256 4174 * the page could change. hat_kpm_mapin_pfn is not supported when
4257 4175 * vac_colors > 1, because the chosen va depends on the page identity,
4258 4176 * which could change.
4259 4177 * The caller must only pass pfn's for valid physical addresses; violation
4260 4178 * of this rule will cause panic.
4261 4179 */
4262 4180 caddr_t
4263 4181 hat_kpm_mapin_pfn(pfn_t pfn)
4264 4182 {
4265 4183 caddr_t paddr, vaddr;
4266 4184
4267 4185 if (kpm_enable == 0)
4268 4186 return ((caddr_t)NULL);
4269 4187
4270 4188 paddr = (caddr_t)ptob(pfn);
4271 4189 vaddr = (uintptr_t)kpm_vbase + paddr;
4272 4190
4273 4191 return ((caddr_t)vaddr);
4274 4192 }
4275 4193
4276 4194 /*ARGSUSED*/
4277 4195 void
4278 4196 hat_kpm_mapout_pfn(pfn_t pfn)
4279 4197 {
4280 4198 /* empty */
4281 4199 }
4282 4200
4283 4201 /*
4284 4202 * Return the kpm virtual address for a specific pfn
4285 4203 */
4286 4204 caddr_t
4287 4205 hat_kpm_pfn2va(pfn_t pfn)
4288 4206 {
4289 4207 uintptr_t vaddr = (uintptr_t)kpm_vbase + mmu_ptob(pfn);
4290 4208
4291 4209 ASSERT(!pfn_is_foreign(pfn));
4292 4210 return ((caddr_t)vaddr);
4293 4211 }
4294 4212
4295 4213 /*
4296 4214 * Return the kpm virtual address for the page at pp.
4297 4215 */
4298 4216 /*ARGSUSED*/
4299 4217 caddr_t
4300 4218 hat_kpm_page2va(struct page *pp, int checkswap)
4301 4219 {
4302 4220 return (hat_kpm_pfn2va(pp->p_pagenum));
4303 4221 }
4304 4222
4305 4223 /*
4306 4224 * Return the page frame number for the kpm virtual address vaddr.
4307 4225 */
4308 4226 pfn_t
4309 4227 hat_kpm_va2pfn(caddr_t vaddr)
4310 4228 {
4311 4229 pfn_t pfn;
4312 4230
4313 4231 ASSERT(IS_KPM_ADDR(vaddr));
4314 4232
4315 4233 pfn = (pfn_t)btop(vaddr - kpm_vbase);
4316 4234
4317 4235 return (pfn);
4318 4236 }
4319 4237
4320 4238
4321 4239 /*
4322 4240 * Return the page for the kpm virtual address vaddr.
4323 4241 */
4324 4242 page_t *
4325 4243 hat_kpm_vaddr2page(caddr_t vaddr)
4326 4244 {
4327 4245 pfn_t pfn;
4328 4246
4329 4247 ASSERT(IS_KPM_ADDR(vaddr));
4330 4248
4331 4249 pfn = hat_kpm_va2pfn(vaddr);
4332 4250
4333 4251 return (page_numtopp_nolock(pfn));
4334 4252 }
4335 4253
4336 4254 /*
4337 4255 * hat_kpm_fault is called from segkpm_fault when we take a page fault on a
4338 4256 * KPM page. This should never happen on x86
4339 4257 */
4340 4258 int
4341 4259 hat_kpm_fault(hat_t *hat, caddr_t vaddr)
4342 4260 {
4343 4261 panic("pagefault in seg_kpm. hat: 0x%p vaddr: 0x%p",
4344 4262 (void *)hat, (void *)vaddr);
4345 4263
4346 4264 return (0);
4347 4265 }
4348 4266
4349 4267 /*ARGSUSED*/
4350 4268 void
4351 4269 hat_kpm_mseghash_clear(int nentries)
4352 4270 {}
4353 4271
4354 4272 /*ARGSUSED*/
4355 4273 void
4356 4274 hat_kpm_mseghash_update(pgcnt_t inx, struct memseg *msp)
4357 4275 {}
4358 4276
4359 4277 #ifndef __xpv
4360 4278 void
4361 4279 hat_kpm_addmem_mseg_update(struct memseg *msp, pgcnt_t nkpmpgs,
4362 4280 offset_t kpm_pages_off)
4363 4281 {
4364 4282 _NOTE(ARGUNUSED(nkpmpgs, kpm_pages_off));
4365 4283 pfn_t base, end;
4366 4284
4367 4285 /*
4368 4286 * kphysm_add_memory_dynamic() does not set nkpmpgs
4369 4287 * when page_t memory is externally allocated. That
4370 4288 * code must properly calculate nkpmpgs in all cases
4371 4289 * if nkpmpgs needs to be used at some point.
4372 4290 */
4373 4291
4374 4292 /*
4375 4293 * The meta (page_t) pages for dynamically added memory are allocated
4376 4294 * either from the incoming memory itself or from existing memory.
4377 4295 * In the former case the base of the incoming pages will be different
4378 4296 * than the base of the dynamic segment so call memseg_get_start() to
4379 4297 * get the actual base of the incoming memory for each case.
4380 4298 */
4381 4299
4382 4300 base = memseg_get_start(msp);
4383 4301 end = msp->pages_end;
4384 4302
4385 4303 hat_devload(kas.a_hat, kpm_vbase + mmu_ptob(base),
4386 4304 mmu_ptob(end - base), base, PROT_READ | PROT_WRITE,
4387 4305 HAT_LOAD | HAT_LOAD_LOCK | HAT_LOAD_NOCONSIST);
4388 4306 }
4389 4307
4390 4308 void
4391 4309 hat_kpm_addmem_mseg_insert(struct memseg *msp)
4392 4310 {
4393 4311 _NOTE(ARGUNUSED(msp));
4394 4312 }
4395 4313
4396 4314 void
4397 4315 hat_kpm_addmem_memsegs_update(struct memseg *msp)
4398 4316 {
4399 4317 _NOTE(ARGUNUSED(msp));
4400 4318 }
4401 4319
4402 4320 /*
4403 4321 * Return end of metadata for an already setup memseg.
4404 4322 * X86 platforms don't need per-page meta data to support kpm.
4405 4323 */
4406 4324 caddr_t
4407 4325 hat_kpm_mseg_reuse(struct memseg *msp)
4408 4326 {
4409 4327 return ((caddr_t)msp->epages);
4410 4328 }
4411 4329
4412 4330 void
4413 4331 hat_kpm_delmem_mseg_update(struct memseg *msp, struct memseg **mspp)
4414 4332 {
4415 4333 _NOTE(ARGUNUSED(msp, mspp));
4416 4334 ASSERT(0);
4417 4335 }
4418 4336
4419 4337 void
4420 4338 hat_kpm_split_mseg_update(struct memseg *msp, struct memseg **mspp,
4421 4339 struct memseg *lo, struct memseg *mid, struct memseg *hi)
4422 4340 {
4423 4341 _NOTE(ARGUNUSED(msp, mspp, lo, mid, hi));
4424 4342 ASSERT(0);
4425 4343 }
4426 4344
4427 4345 /*
4428 4346 * Walk the memsegs chain, applying func to each memseg span.
4429 4347 */
4430 4348 void
4431 4349 hat_kpm_walk(void (*func)(void *, void *, size_t), void *arg)
4432 4350 {
4433 4351 pfn_t pbase, pend;
4434 4352 void *base;
4435 4353 size_t size;
4436 4354 struct memseg *msp;
4437 4355
4438 4356 for (msp = memsegs; msp; msp = msp->next) {
4439 4357 pbase = msp->pages_base;
4440 4358 pend = msp->pages_end;
4441 4359 base = ptob(pbase) + kpm_vbase;
4442 4360 size = ptob(pend - pbase);
4443 4361 func(arg, base, size);
4444 4362 }
4445 4363 }
4446 4364
4447 4365 #else /* __xpv */
4448 4366
4449 4367 /*
4450 4368 * There are specific Hypervisor calls to establish and remove mappings
4451 4369 * to grant table references and the privcmd driver. We have to ensure
4452 4370 * that a page table actually exists.
4453 4371 */
4454 4372 void
4455 4373 hat_prepare_mapping(hat_t *hat, caddr_t addr, uint64_t *pte_ma)
4456 4374 {
4457 4375 maddr_t base_ma;
4458 4376 htable_t *ht;
4459 4377 uint_t entry;
4460 4378
4461 4379 ASSERT(IS_P2ALIGNED((uintptr_t)addr, MMU_PAGESIZE));
4462 4380 XPV_DISALLOW_MIGRATE();
4463 4381 ht = htable_create(hat, (uintptr_t)addr, 0, NULL);
4464 4382
4465 4383 /*
4466 4384 * if an address for pte_ma is passed in, return the MA of the pte
4467 4385 * for this specific address. This address is only valid as long
4468 4386 * as the htable stays locked.
4469 4387 */
4470 4388 if (pte_ma != NULL) {
4471 4389 entry = htable_va2entry((uintptr_t)addr, ht);
4472 4390 base_ma = pa_to_ma(ptob(ht->ht_pfn));
4473 4391 *pte_ma = base_ma + (entry << mmu.pte_size_shift);
4474 4392 }
4475 4393 XPV_ALLOW_MIGRATE();
4476 4394 }
4477 4395
4478 4396 void
4479 4397 hat_release_mapping(hat_t *hat, caddr_t addr)
4480 4398 {
4481 4399 htable_t *ht;
4482 4400
4483 4401 ASSERT(IS_P2ALIGNED((uintptr_t)addr, MMU_PAGESIZE));
4484 4402 XPV_DISALLOW_MIGRATE();
4485 4403 ht = htable_lookup(hat, (uintptr_t)addr, 0);
4486 4404 ASSERT(ht != NULL);
4487 4405 ASSERT(ht->ht_busy >= 2);
4488 4406 htable_release(ht);
4489 4407 htable_release(ht);
4490 4408 XPV_ALLOW_MIGRATE();
4491 4409 }
4492 4410 #endif /* __xpv */
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