1102
1103 while (done == 0) {
1104 ql_8021_rd_32(ha, UNM_ROMUSB_GLB_STATUS, &done);
1105 done &= 2;
1106 timeout++;
1107 if (timeout >= ROM_MAX_TIMEOUT) {
1108 EL(ha, "Timeout reached waiting for rom done\n");
1109 return (-1);
1110 }
1111 }
1112
1113 return (0);
1114 }
1115
1116 static int
1117 ql_8021_wait_flash_done(ql_adapter_state_t *ha)
1118 {
1119 clock_t timer;
1120 uint32_t status;
1121
1122 for (timer = 30 * drv_usectohz(1000000); timer; timer--) {
1123 ql_8021_wr_32(ha, UNM_ROMUSB_ROM_ABYTE_CNT, 0);
1124 ql_8021_wr_32(ha, UNM_ROMUSB_ROM_INSTR_OPCODE,
1125 UNM_ROMUSB_ROM_RDSR_INSTR);
1126 if (ql_8021_wait_rom_done(ha)) {
1127 EL(ha, "Error waiting for rom done2\n");
1128 return (-1);
1129 }
1130
1131 /* Get status. */
1132 ql_8021_rd_32(ha, UNM_ROMUSB_ROM_RDATA, &status);
1133 if (!(status & BIT_0)) {
1134 return (0);
1135 }
1136 delay(1);
1137 }
1138
1139 EL(ha, "timeout status=%x\n", status);
1140 return (-1);
1141 }
1142
1591 dp = (uint8_t *)&data;
1592 for (i = 0; i < size; i++) {
1593 for (n = 0; n < 8; n++) {
1594 dp[n] = *bp++;
1595 }
1596 LITTLE_ENDIAN_64(&data);
1597 (void) ql_8021_pci_mem_write_2M(ha, flashaddr, &data, 8);
1598 flashaddr += 8;
1599 }
1600
1601 return (0);
1602 }
1603
1604 static int
1605 ql_8021_init_p3p(ql_adapter_state_t *ha)
1606 {
1607 uint32_t data;
1608
1609 /* ??? */
1610 ql_8021_wr_32(ha, UNM_PORT_MODE_ADDR, UNM_PORT_MODE_AUTO_NEG);
1611 delay(drv_usectohz(1000000));
1612
1613 /* CAM RAM Cold Boot Register */
1614 ql_8021_rd_32(ha, UNM_RAM_COLD_BOOT, &data);
1615 if (data == 0x55555555) {
1616 ql_8021_rd_32(ha, UNM_ROMUSB_GLB_SW_RESET, &data);
1617 if (data != 0x80000f) {
1618 EL(ha, "CRB_UNM_GLB_SW_RST=%x exit\n", data);
1619 return (-1);
1620 }
1621 ql_8021_wr_32(ha, UNM_RAM_COLD_BOOT, 0);
1622 }
1623 ql_8021_rd_32(ha, UNM_ROMUSB_GLB_PEGTUNE_DONE, &data);
1624 data |= 1;
1625 ql_8021_wr_32(ha, UNM_ROMUSB_GLB_PEGTUNE_DONE, data);
1626
1627 /*
1628 * ???
1629 * data = ha->pci_bus_addr | BIT_31;
1630 * ql_8021_wr_32(ha, UNM_BUS_DEV_NO, data);
1631 */
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1102
1103 while (done == 0) {
1104 ql_8021_rd_32(ha, UNM_ROMUSB_GLB_STATUS, &done);
1105 done &= 2;
1106 timeout++;
1107 if (timeout >= ROM_MAX_TIMEOUT) {
1108 EL(ha, "Timeout reached waiting for rom done\n");
1109 return (-1);
1110 }
1111 }
1112
1113 return (0);
1114 }
1115
1116 static int
1117 ql_8021_wait_flash_done(ql_adapter_state_t *ha)
1118 {
1119 clock_t timer;
1120 uint32_t status;
1121
1122 for (timer = drv_sectohz(30); timer; timer--) {
1123 ql_8021_wr_32(ha, UNM_ROMUSB_ROM_ABYTE_CNT, 0);
1124 ql_8021_wr_32(ha, UNM_ROMUSB_ROM_INSTR_OPCODE,
1125 UNM_ROMUSB_ROM_RDSR_INSTR);
1126 if (ql_8021_wait_rom_done(ha)) {
1127 EL(ha, "Error waiting for rom done2\n");
1128 return (-1);
1129 }
1130
1131 /* Get status. */
1132 ql_8021_rd_32(ha, UNM_ROMUSB_ROM_RDATA, &status);
1133 if (!(status & BIT_0)) {
1134 return (0);
1135 }
1136 delay(1);
1137 }
1138
1139 EL(ha, "timeout status=%x\n", status);
1140 return (-1);
1141 }
1142
1591 dp = (uint8_t *)&data;
1592 for (i = 0; i < size; i++) {
1593 for (n = 0; n < 8; n++) {
1594 dp[n] = *bp++;
1595 }
1596 LITTLE_ENDIAN_64(&data);
1597 (void) ql_8021_pci_mem_write_2M(ha, flashaddr, &data, 8);
1598 flashaddr += 8;
1599 }
1600
1601 return (0);
1602 }
1603
1604 static int
1605 ql_8021_init_p3p(ql_adapter_state_t *ha)
1606 {
1607 uint32_t data;
1608
1609 /* ??? */
1610 ql_8021_wr_32(ha, UNM_PORT_MODE_ADDR, UNM_PORT_MODE_AUTO_NEG);
1611 delay(drv_sectohz(1));
1612
1613 /* CAM RAM Cold Boot Register */
1614 ql_8021_rd_32(ha, UNM_RAM_COLD_BOOT, &data);
1615 if (data == 0x55555555) {
1616 ql_8021_rd_32(ha, UNM_ROMUSB_GLB_SW_RESET, &data);
1617 if (data != 0x80000f) {
1618 EL(ha, "CRB_UNM_GLB_SW_RST=%x exit\n", data);
1619 return (-1);
1620 }
1621 ql_8021_wr_32(ha, UNM_RAM_COLD_BOOT, 0);
1622 }
1623 ql_8021_rd_32(ha, UNM_ROMUSB_GLB_PEGTUNE_DONE, &data);
1624 data |= 1;
1625 ql_8021_wr_32(ha, UNM_ROMUSB_GLB_PEGTUNE_DONE, data);
1626
1627 /*
1628 * ???
1629 * data = ha->pci_bus_addr | BIT_31;
1630 * ql_8021_wr_32(ha, UNM_BUS_DEV_NO, data);
1631 */
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