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--- old/usr/src/uts/common/sys/usb/hcd/uhci/uhcid.h
+++ new/usr/src/uts/common/sys/usb/hcd/uhci/uhcid.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26 #ifndef _SYS_USB_UHCID_H
27 27 #define _SYS_USB_UHCID_H
28 28
29 29
30 30 #ifdef __cplusplus
31 31 extern "C" {
32 32 #endif
33 33
34 34 /*
35 35 * Universal Host Controller Driver (UHCI)
36 36 *
37 37 * The UHCI driver is a driver which interfaces to the Universal
38 38 * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
39 39 * the Host Controller is defined by the Universal Host Controller Interface.
40 40 *
41 41 * This file contains the data structures for the UHCI driver.
42 42 */
43 43 #include <sys/types.h>
44 44 #include <sys/pci.h>
45 45 #include <sys/kstat.h>
46 46
47 47 #include <sys/usb/usba/usbai_version.h>
48 48 #include <sys/usb/usba.h>
49 49 #include <sys/usb/usba/usba_types.h>
50 50
51 51 #include <sys/usb/usba/genconsole.h>
52 52 #include <sys/usb/usba/hcdi.h>
53 53
54 54 #include <sys/usb/hubd/hub.h>
55 55 #include <sys/usb/usba/hubdi.h>
56 56 #include <sys/usb/hubd/hubdvar.h>
57 57
58 58 #include <sys/usb/hcd/uhci/uhci.h>
59 59
60 60 /* limit the xfer size for bulk */
61 61 #define UHCI_BULK_MAX_XFER_SIZE (124*1024) /* Max bulk xfer size */
62 62
63 63 /* Maximum allowable data transfer size per transaction */
64 64 #define UHCI_MAX_TD_XFER_SIZE 0x500 /* Maximum data per transaction */
65 65
66 66 /*
67 67 * Generic UHCI Macro definitions
68 68 */
69 69 #define UHCI_UNDERRUN_OCCURRED 0x1234
70 70 #define UHCI_OVERRUN_OCCURRED 0x5678
71 71 #define UHCI_PROP_MASK 0x01000020
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72 72 #define UHCI_RESET_DELAY 15000
73 73 #define UHCI_TIMEWAIT 10000
74 74
75 75 #define MAX_SOF_WAIT_COUNT 2
76 76 #define MAX_RH_PORTS 2
77 77 #define DISCONNECTED 2
78 78 #define POLLING_FREQ_7MS 7
79 79 #define PCI_CONF_IOBASE 0x20
80 80 #define PCI_CONF_IOBASE_MASK 0xffe0
81 81
82 -#define UHCI_ONE_SECOND drv_usectohz(1000000)
82 +#define UHCI_ONE_SECOND drv_sectohz(1)
83 83 #define UHCI_ONE_MS drv_usectohz(1000)
84 84 #define UHCI_32_MS drv_usectohz(32*1000)
85 85 #define UHCI_256_MS drv_usectohz(256*1000)
86 86 #define UHCI_MAX_INSTS 4
87 87
88 88 #define POLLED_RAW_BUF_SIZE 8
89 89
90 90 /* Default time out values for bulk and ctrl commands */
91 91 #define UHCI_CTRL_TIMEOUT 5
92 92 #define UHCI_BULK_TIMEOUT 60
93 93
94 94 /* UHCI root hub structure */
95 95 typedef struct uhci_root_hub_info {
96 96 uint_t rh_status; /* Last RH status */
97 97 uint_t rh_num_ports; /* #ports on the root */
98 98
99 99 /* Last status of ports */
100 100 uint_t rh_port_status[MAX_RH_PORTS];
101 101 uint_t rh_port_changes[MAX_RH_PORTS];
102 102 uint_t rh_port_state[MAX_RH_PORTS]; /* See below */
103 103
104 104 usba_pipe_handle_data_t *rh_intr_pipe_handle; /* RH intr pipe hndle */
105 105 usb_hub_descr_t rh_descr; /* RH descr's copy */
106 106 uint_t rh_pipe_state; /* RH intr pipe state */
107 107
108 108 usb_intr_req_t *rh_curr_intr_reqp; /* Current intr req */
109 109 usb_intr_req_t *rh_client_intr_req; /* save IN request */
110 110 } uhci_root_hub_info_t;
111 111
112 112 /*
113 113 * UHCI Host Controller per instance data structure
114 114 *
115 115 * The Host Controller Driver (HCD) maintains the state of Host Controller
116 116 * (HC). There is an uhci_state structure per instance of the UHCI
117 117 * host controller.
118 118 */
119 119 typedef struct uhci_state {
120 120 dev_info_t *uhci_dip; /* dip of HC */
121 121 uint_t uhci_instance;
122 122 usba_hcdi_ops_t *uhci_hcdi_ops; /* HCDI structure */
123 123
124 124 uint_t uhci_dma_addr_bind_flag;
125 125
126 126 /* UHCI Host Controller Software State information */
127 127 uint_t uhci_hc_soft_state;
128 128
129 129 hc_regs_t *uhci_regsp; /* Host ctlr regs */
130 130 ddi_acc_handle_t uhci_regs_handle; /* Reg handle */
131 131
132 132 ddi_acc_handle_t uhci_config_handle; /* Config space hndle */
133 133
134 134 /* Frame interval reg */
135 135 uint_t uhci_frame_interval;
136 136 ddi_dma_attr_t uhci_dma_attr; /* DMA attributes */
137 137
138 138 ddi_intr_handle_t *uhci_htable; /* intr handle */
139 139 int uhci_intr_type; /* intr type used */
140 140 int uhci_intr_cnt; /* # of intrs inuse */
141 141 uint_t uhci_intr_pri; /* intr priority */
142 142 int uhci_intr_cap; /* intr capabilities */
143 143 kmutex_t uhci_int_mutex; /* Mutex for struct */
144 144
145 145 frame_lst_table_t *uhci_frame_lst_tablep; /* Virtual HCCA ptr */
146 146 uhci_td_t *uhci_isoc_q_tailp[NUM_FRAME_LST_ENTRIES];
147 147
148 148 ddi_dma_cookie_t uhci_flt_cookie; /* DMA cookie */
149 149 ddi_dma_handle_t uhci_flt_dma_handle; /* DMA handle */
150 150 ddi_acc_handle_t uhci_flt_mem_handle; /* Memory handle */
151 151
152 152 /*
153 153 * There are two pools of memory. One pool contains the memory for
154 154 * the transfer descriptors and other pool contains the memory for
155 155 * the Queue Head pointers. The advantage of the pools is that it's
156 156 * easy to go back and forth between the iommu and the cpu addresses.
157 157 *
158 158 * The pools are protected by the int_mutex because the memory
159 159 * in the pools may be accessed by either the host controller or the
160 160 * host controller driver.
161 161 */
162 162
163 163 /* General transfer descriptor pool */
164 164 uhci_td_t *uhci_td_pool_addr; /* Start of the pool */
165 165 ddi_dma_cookie_t uhci_td_pool_cookie; /* DMA cookie */
166 166 ddi_dma_handle_t uhci_td_pool_dma_handle; /* DMA hndle */
167 167 ddi_acc_handle_t uhci_td_pool_mem_handle; /* Mem hndle */
168 168
169 169 /* Endpoint descriptor pool */
170 170 queue_head_t *uhci_qh_pool_addr; /* Start of the pool */
171 171 ddi_dma_cookie_t uhci_qh_pool_cookie; /* DMA cookie */
172 172 ddi_dma_handle_t uhci_qh_pool_dma_handle; /* DMA handle */
173 173 ddi_acc_handle_t uhci_qh_pool_mem_handle; /* Mem handle */
174 174
175 175 /* Semaphore to serialize opens and closes */
176 176 ksema_t uhci_ocsem;
177 177
178 178 /* Timeout id of the root hub status change pipe handler */
179 179 timeout_id_t uhci_timeout_id;
180 180
181 181 /* Timeout id of the ctrl/bulk/intr xfers timeout */
182 182 timeout_id_t uhci_cmd_timeout_id;
183 183
184 184 /*
185 185 * Bandwidth fields
186 186 *
187 187 * The uhci_bandwidth array keeps track of the allocated bandwidth
188 188 * for this host controller. The uhci_bandwidth_isoch_sum field
189 189 * represents the sum of the allocated isochronous bandwidth. The
190 190 * total bandwidth allocated for least allocated list out of the 32
191 191 * interrupt lists is represented by the uhci_bandwdith_intr_min
192 192 * field.
193 193 */
194 194 uint_t uhci_bandwidth[NUM_FRAME_LST_ENTRIES];
195 195 uint_t uhci_bandwidth_isoch_sum;
196 196 uint_t uhci_bandwidth_intr_min;
197 197
198 198 uhci_root_hub_info_t uhci_root_hub; /* Root hub info */
199 199
200 200 uhci_td_t *uhci_outst_tds_head;
201 201 uhci_td_t *uhci_outst_tds_tail;
202 202
203 203 queue_head_t *uhci_ctrl_xfers_q_head;
204 204 queue_head_t *uhci_ctrl_xfers_q_tail;
205 205 queue_head_t *uhci_bulk_xfers_q_head;
206 206 queue_head_t *uhci_bulk_xfers_q_tail;
207 207
208 208 kcondvar_t uhci_cv_SOF;
209 209 uchar_t uhci_cv_signal;
210 210
211 211 /* Polled I/O support */
212 212 frame_lst_table_t uhci_polled_save_IntTble[1024];
213 213 uint_t uhci_polled_count;
214 214 uint32_t uhci_polled_flag;
215 215
216 216 /* Software frame number */
217 217 usb_frame_number_t uhci_sw_frnum;
218 218
219 219 /* Number of pending bulk commands */
220 220 uint32_t uhci_pending_bulk_cmds;
221 221
222 222 /* logging support */
223 223 usb_log_handle_t uhci_log_hdl;
224 224
225 225 /*
226 226 * TD's used for the generation of interrupt
227 227 */
228 228 queue_head_t *uhci_isoc_qh;
229 229 uhci_td_t *uhci_sof_td;
230 230 uhci_td_t *uhci_isoc_td;
231 231
232 232 /*
233 233 * Keep io base address, for debugging purpose
234 234 */
235 235 uint_t uhci_iobase;
236 236
237 237 /*
238 238 * kstat structures
239 239 */
240 240 kstat_t *uhci_intrs_stats;
241 241 kstat_t *uhci_total_stats;
242 242 kstat_t *uhci_count_stats[USB_N_COUNT_KSTATS];
243 243 } uhci_state_t;
244 244
245 245
246 246 /*
247 247 * uhci_dma_addr_bind_flag values
248 248 *
249 249 * This flag indicates if the various DMA addresses allocated by the UHCI
250 250 * have been bound to their respective handles. This is needed to recover
251 251 * without errors from uhci_cleanup when it calls ddi_dma_unbind_handle()
252 252 */
253 253 #define UHCI_TD_POOL_BOUND 0x01 /* for TD pools */
254 254 #define UHCI_QH_POOL_BOUND 0x02 /* for QH pools */
255 255 #define UHCI_FLA_POOL_BOUND 0x04 /* for Host Ctrlr Framelist Area */
256 256
257 257 /*
258 258 * Definitions for uhci_polled_flag
259 259 * The flag is set to UHCI_POLLED_FLAG_FALSE by default. The flags is
260 260 * set to UHCI_POLLED_FLAG_TD_COMPL when shifting from normal mode to
261 261 * polled mode and if the normal TD is completed at that time. And the
262 262 * flag is set to UHCI_POLLED_FLAG_TRUE while exiting from the polled
263 263 * mode. In the timeout handler for root hub status change, this flag
264 264 * is checked. If set to UHCI_POLLED_FLAG_TRUE, the routine
265 265 * uhci_process_submitted_td_queue() to process the completed TD.
266 266 */
267 267 #define UHCI_POLLED_FLAG_FALSE 0
268 268 #define UHCI_POLLED_FLAG_TRUE 1
269 269 #define UHCI_POLLED_FLAG_TD_COMPL 2
270 270
271 271 /*
272 272 * Pipe private structure
273 273 *
274 274 * There is an instance of this structure per pipe. This structure holds
275 275 * HCD specific pipe information. A pointer to this structure is kept in
276 276 * the USBA pipe handle (usba_pipe_handle_data_t).
277 277 */
278 278 typedef struct uhci_pipe_private {
279 279 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to pipe handle */
280 280 queue_head_t *pp_qh; /* Pipe's ept */
281 281 uint_t pp_state; /* See below */
282 282 usb_pipe_policy_t pp_policy; /* Copy of the pipe policy */
283 283 uint_t pp_node; /* Node in lattice */
284 284 uchar_t pp_data_toggle; /* save data toggle bit */
285 285
286 286 /*
287 287 * Each pipe may have multiple transfer wrappers. Each transfer
288 288 * wrapper represents a USB transfer on the bus. A transfer is
289 289 * made up of one or more transactions.
290 290 */
291 291 struct uhci_trans_wrapper *pp_tw_head; /* Head of the list */
292 292 struct uhci_trans_wrapper *pp_tw_tail; /* Tail of the list */
293 293
294 294 /*
295 295 * Starting frame number at which next isoc TD will be inserted
296 296 * for this pipe
297 297 */
298 298 uint64_t pp_frame_num;
299 299
300 300 /*
301 301 * HCD gets Interrupt/Isochronous IN polling request only once and
302 302 * it has to insert next polling requests after completion of first
303 303 * request until either stop polling/pipe close is called. So HCD
304 304 * has to take copy of the original Interrupt/Isochronous IN request.
305 305 */
306 306 usb_opaque_t pp_client_periodic_in_reqp;
307 307 } uhci_pipe_private_t;
308 308
309 309 /* warlock directives, stable data */
310 310 _NOTE(MUTEX_PROTECTS_DATA(uhci_state_t::uhci_int_mutex, uhci_pipe_private_t))
311 311 _NOTE(LOCK_ORDER(uhci_state::uhci_int_mutex \
312 312 usba_pipe_handle_data::p_mutex \
313 313 usba_device::usb_mutex \
314 314 usba_ph_impl::usba_ph_mutex))
315 315 _NOTE(SCHEME_PROTECTS_DATA("private mutex", kstat_io))
316 316 _NOTE(SCHEME_PROTECTS_DATA("unshared", usb_isoc_pkt_descr))
317 317
318 318 /*
319 319 * Pipe states
320 320 *
321 321 * uhci pipe states will be similar to usba. Refer usbai.h.
322 322 */
323 323 #define UHCI_PIPE_STATE_IDLE 1 /* Pipe has opened,ready state */
324 324 #define UHCI_PIPE_STATE_ACTIVE 2 /* Polling the endpoint,busy state */
325 325
326 326 /*
327 327 * to indicate if we are in close/reset so that we can issue callbacks to
328 328 * IN packets that are pending
329 329 */
330 330 #define UHCI_IN_CLOSE 4
331 331 #define UHCI_IN_RESET 5
332 332 #define UHCI_IN_ERROR 6
333 333
334 334 /* Function prototype */
335 335 typedef void (*uhci_handler_function_t) (uhci_state_t *uhcip, uhci_td_t *td);
336 336
337 337 /*
338 338 * Transfer wrapper
339 339 *
340 340 * The transfer wrapper represents a USB transfer on the bus and there
341 341 * is one instance per USB transfer. A transfer is made up of one or
342 342 * more transactions. UHCI uses one TD for one transaction. So one
343 343 * transfer wrapper may have one or more TDs associated.
344 344 *
345 345 * Control and bulk pipes will have one transfer wrapper per transfer
346 346 * and where as Isochronous and Interrupt pipes will only have one
347 347 * transfer wrapper. The transfers wrapper are continually reused for
348 348 * the Interrupt and Isochronous pipes as those pipes are polled.
349 349 *
350 350 * Control, bulk and interrupt transfers will have one DMA buffer per
351 351 * transfer. The data to be transferred are contained in the DMA buffer
352 352 * which is virtually contiguous but physically discontiguous. When
353 353 * preparing the TDs for a USB transfer, the DMA cookies contained in
354 354 * the buffer need to be walked through to retrieve the DMA addresses.
355 355 *
356 356 * Isochronous transfers will have multiple DMA buffers per transfer
357 357 * with each isoc packet having a DMA buffer. And the DMA buffers should
358 358 * only contain one cookie each, so no cookie walking is necessary.
359 359 */
360 360 typedef struct uhci_trans_wrapper {
361 361 struct uhci_trans_wrapper *tw_next; /* Next wrapper */
362 362 uhci_pipe_private_t *tw_pipe_private;
363 363 size_t tw_length; /* Txfer length */
364 364 uint_t tw_tmp; /* Temp variable */
365 365 ddi_dma_handle_t tw_dmahandle; /* DMA handle */
366 366 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */
367 367 char *tw_buf; /* Buffer for txfer */
368 368 ddi_dma_cookie_t tw_cookie; /* DMA cookie */
369 369 uint_t tw_ncookies; /* DMA cookie count */
370 370 uint_t tw_cookie_idx; /* DMA cookie index */
371 371 size_t tw_dma_offs; /* DMA buffer offset */
372 372 int tw_ctrl_state; /* See below */
373 373 uhci_td_t *tw_hctd_head; /* Head TD */
374 374 uhci_td_t *tw_hctd_tail; /* Tail TD */
375 375 uint_t tw_direction; /* Direction of TD */
376 376 usb_flags_t tw_flags; /* Flags */
377 377
378 378 /*
379 379 * This is the function to call when this td is done. This way
380 380 * we don't have to look in the td to figure out what kind it is.
381 381 */
382 382 uhci_handler_function_t tw_handle_td;
383 383
384 384 /*
385 385 * This is the callback value used when processing a done td.
386 386 */
387 387 usb_opaque_t tw_handle_callback_value;
388 388
389 389 uint_t tw_bytes_xfered;
390 390 uint_t tw_bytes_pending;
391 391
392 392 /* Maximum amount of time for this command */
393 393 uint_t tw_timeout_cnt;
394 394
395 395 usb_isoc_req_t *tw_isoc_req;
396 396 uhci_bulk_isoc_xfer_t tw_xfer_info;
397 397 uhci_isoc_buf_t *tw_isoc_bufs; /* Isoc DMA buffers */
398 398 size_t tw_isoc_strtlen;
399 399
400 400 /* This is used to avoid multiple tw deallocation */
401 401 uint_t tw_claim;
402 402
403 403 /*
404 404 * Pointer to the data in case of send command
405 405 */
406 406 mblk_t *tw_data;
407 407
408 408 /* save a copy of current request */
409 409 usb_opaque_t tw_curr_xfer_reqp;
410 410 } uhci_trans_wrapper_t;
411 411
412 412 /* Macros for uhci DMA buffer */
413 413 #define UHCI_DMA_ATTR_ALIGN 0x800
414 414 #define UHCI_DMA_ATTR_SGLLEN 0x7fffffff
415 415 #define UHCI_CTRL_EPT_MAX_SIZE 64
416 416
417 417 /*
418 418 * Macro for allocation of Bulk and Isoc TD pools
419 419 *
420 420 * When a Bulk or Isoc transfer needs to allocate too many TDs,
421 421 * the allocation for one physical contiguous TD pool may fail
422 422 * due to the fragmentation of physical memory. The number of
423 423 * TDs in one pool should be limited so that a TD pool is within
424 424 * page size under this situation.
425 425 */
426 426 #if defined(__sparc)
427 427 #define UHCI_MAX_TD_NUM_PER_POOL 88
428 428 #else
429 429 #define UHCI_MAX_TD_NUM_PER_POOL 44
430 430 #endif
431 431
432 432 /* set timeout flag so as to decrement timeout_cnt only once */
433 433 #define TW_TIMEOUT_FLAG 0x1000
434 434
435 435 /* Macro for changing the data toggle */
436 436 #define ADJ_DATA_TOGGLE(pp) \
437 437 (pp)->pp_data_toggle = ((pp)->pp_data_toggle == 0) ? 1 : 0;
438 438
439 439 /*
440 440 * Macros for setting/getting information
441 441 */
442 442 #define Get_OpReg32(addr) ddi_get32(uhcip->uhci_regs_handle, \
443 443 (uint32_t *)&uhcip->uhci_regsp->addr)
444 444 #define Get_OpReg16(addr) ddi_get16(uhcip->uhci_regs_handle, \
445 445 (uint16_t *)&uhcip->uhci_regsp->addr)
446 446 #define Get_OpReg8(addr) ddi_get8(uhcip->uhci_regs_handle, \
447 447 (uchar_t *)&uhcip->uhci_regsp->addr)
448 448
449 449 #define Set_OpReg32(addr, val) ddi_put32(uhcip->uhci_regs_handle, \
450 450 ((uint32_t *)&uhcip->uhci_regsp->addr), \
451 451 ((int32_t)(val)))
452 452 #define Set_OpReg16(addr, val) ddi_put16(uhcip->uhci_regs_handle, \
453 453 ((uint16_t *)&uhcip->uhci_regsp->addr), \
454 454 ((int16_t)(val)))
455 455
456 456 #define QH_PADDR(addr) \
457 457 ((uint32_t)(uhcip->uhci_qh_pool_cookie.dmac_address + \
458 458 (uint32_t)((uintptr_t)(addr) - \
459 459 (uintptr_t)uhcip->uhci_qh_pool_addr)))
460 460
461 461
462 462 #define QH_VADDR(addr) \
463 463 ((void *)(((uint32_t)(addr) - \
464 464 (uint32_t)uhcip->uhci_qh_pool_cookie.dmac_address) + \
465 465 (char *)uhcip->uhci_qh_pool_addr))
466 466
467 467 #define TD_PADDR(addr) \
468 468 ((uint32_t)uhcip->uhci_td_pool_cookie.dmac_address + \
469 469 (uint32_t)((uintptr_t)(addr) - \
470 470 (uintptr_t)(uhcip->uhci_td_pool_addr)))
471 471
472 472 #define BULKTD_PADDR(x, addr)\
473 473 ((uint32_t)((uintptr_t)(addr) - (uintptr_t)x->pool_addr) + \
474 474 (uint32_t)(x)->cookie.dmac_address)
475 475
476 476 #define BULKTD_VADDR(x, addr)\
477 477 ((void *)(((uint32_t)(addr) - \
478 478 (uint32_t)(x)->cookie.dmac_address) + \
479 479 (char *)(x)->pool_addr))
480 480
481 481 #define ISOCTD_PADDR(x, addr)\
482 482 ((uint32_t)((uintptr_t)(addr) - (uintptr_t)(x)->pool_addr) + \
483 483 (uint32_t)(x)->cookie.dmac_address)
484 484
485 485 #define TD_VADDR(addr) \
486 486 ((void *)(((uint32_t)(addr) - \
487 487 (uint32_t)uhcip->uhci_td_pool_cookie.dmac_address) + \
488 488 (char *)uhcip->uhci_td_pool_addr))
489 489
490 490 /*
491 491 * If the terminate bit is cleared, there shouldn't be any
492 492 * race condition problems. If the host controller reads the
493 493 * bit before the driver has a chance to set the bit, the bit
494 494 * will be reread on the next frame.
495 495 */
496 496 #define UHCI_SET_TERMINATE_BIT(addr) \
497 497 SetQH32(uhcip, addr, GetQH32(uhcip, (addr)) | HC_END_OF_LIST)
498 498 #define UHCI_CLEAR_TERMINATE_BIT(addr) \
499 499 SetQH32(uhcip, addr, GetQH32(uhcip, (addr)) & ~HC_END_OF_LIST)
500 500
501 501 #define UHCI_XFER_TYPE(ept) ((ept)->bmAttributes & USB_EP_ATTR_MASK)
502 502 #define UHCI_XFER_DIR(ept) ((ept)->bEndpointAddress & \
503 503 USB_EP_DIR_MASK)
504 504
505 505 /*
506 506 * for HCD based kstats:
507 507 * uhci_intrs_stats_t structure
508 508 */
509 509 typedef struct uhci_intrs_stats {
510 510 struct kstat_named uhci_intrs_hc_halted;
511 511 struct kstat_named uhci_intrs_hc_process_err;
512 512 struct kstat_named uhci_intrs_host_sys_err;
513 513 struct kstat_named uhci_intrs_resume_detected;
514 514 struct kstat_named uhci_intrs_usb_err_intr;
515 515 struct kstat_named uhci_intrs_usb_intr;
516 516 struct kstat_named uhci_intrs_total;
517 517 struct kstat_named uhci_intrs_not_claimed;
518 518 } uhci_intrs_stats_t;
519 519
520 520 /*
521 521 * uhci defines for kstats
522 522 */
523 523 #define UHCI_INTRS_STATS(uhci) ((uhci)->uhci_intrs_stats)
524 524 #define UHCI_INTRS_STATS_DATA(uhci) \
525 525 ((uhci_intrs_stats_t *)UHCI_INTRS_STATS((uhci))->ks_data)
526 526
527 527 #define UHCI_TOTAL_STATS(uhci) ((uhci)->uhci_total_stats)
528 528 #define UHCI_TOTAL_STATS_DATA(uhci) (KSTAT_IO_PTR((uhci)->uhci_total_stats))
529 529 #define UHCI_CTRL_STATS(uhci) \
530 530 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_CONTROL]))
531 531 #define UHCI_BULK_STATS(uhci) \
532 532 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_BULK]))
533 533 #define UHCI_INTR_STATS(uhci) \
534 534 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_INTR]))
535 535 #define UHCI_ISOC_STATS(uhci) \
536 536 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_ISOCH]))
537 537
538 538 #define UHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB)
539 539
540 540 #define UHCI_PERIODIC_ENDPOINT(ept) \
541 541 (((((ept)->bmAttributes) & USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) || \
542 542 ((((ept)->bmAttributes) & USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
543 543
544 544 /*
545 545 * Host Contoller Software States
546 546 *
547 547 * UHCI_CTLR_INIT_STATE:
548 548 * The host controller soft state will be set to this during the
549 549 * uhci_attach.
550 550 *
551 551 * UHCI_CTLR_SUSPEND_STATE:
552 552 * The host controller soft state will be set to this during the
553 553 * uhci_cpr_suspend.
554 554 *
555 555 * UHCI_CTLR_OPERATIONAL_STATE:
556 556 * The host controller soft state will be set to this after moving
557 557 * host controller to operational state and host controller start
558 558 * generating SOF successfully.
559 559 *
560 560 * UHCI_CTLR_ERROR_STATE:
561 561 * The host controller soft state will be set to this during the
562 562 * hardware error or no SOF conditions.
563 563 *
564 564 * Under non-operational state, only pipe stop polling, pipe reset
565 565 * and pipe close are allowed. But all other entry points like pipe
566 566 * open, get/set pipe policy, cotrol send/receive, bulk send/receive
567 567 * isoch send/receive, start polling etc. will fail.
568 568 */
569 569 #define UHCI_CTLR_INIT_STATE 0 /* Initilization state */
570 570 #define UHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */
571 571 #define UHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */
572 572 #define UHCI_CTLR_ERROR_STATE 3 /* Hardware error */
573 573
574 574 /*
575 575 * Debug printing Masks
576 576 */
577 577 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */
578 578 #define PRINT_MASK_LISTS 0x00000002 /* List management */
579 579 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */
580 580 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */
581 581 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */
582 582 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */
583 583 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */
584 584 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */
585 585 #define PRINT_MASK_DUMPING 0x00000100 /* Dump HCD state info */
586 586 #define PRINT_MASK_ISOC 0x00000200 /* For ISOC xfers */
587 587
588 588 #define PRINT_MASK_ALL 0xFFFFFFFF
589 589
590 590 #ifdef __cplusplus
591 591 }
592 592 #endif
593 593
594 594 #endif /* _SYS_USB_UHCID_H */
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