3772
3773 (void) fd_unbind_handle(fdc);
3774 return (EIO);
3775 }
3776
3777 Set_Fifo(fdc, csb->csb_cmds[i]);
3778
3779 FDERRPRINT(FDEP_L1, FDEM_EXEC,
3780 (C, "fdexec: sent 0x%x, Msr 0x%x\n", csb->csb_cmds[i],
3781 Msr(fdc)));
3782
3783 }
3784
3785
3786 /*
3787 * Start watchdog timer on data transfer type commands - required
3788 * in case a diskette is not present or is unformatted
3789 */
3790 if (csb->csb_opflags & CSB_OFTIMEIT) {
3791 fdc->c_timeid = timeout(fdwatch, a,
3792 tosec * drv_usectohz(1000000));
3793 }
3794
3795 FDERRPRINT(FDEP_L1, FDEM_EXEC,
3796 (C, "fdexec: cmd sent, Msr 0x%x\n", Msr(fdc)));
3797
3798 /* If the operation has no results - then just return */
3799 if (csb->csb_opflags & CSB_OFNORESULTS) {
3800 if (fdc->c_fdtype & FDCTYPE_82077) {
3801 if (fdc->c_mtimeid == 0) {
3802 fdc->c_mtimeid = timeout(fdmotoff, a,
3803 Motoff_delay);
3804 }
3805 }
3806 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: O K ..\n"));
3807
3808 /*
3809 * Make sure the last byte is received well by the
3810 * controller. On faster CPU, it may still be busy
3811 * by the time another command comes here.
3812 */
4825 * when we bring the controller out of reset it will generate
4826 * a polling interrupt. fdintr() will field it and schedule
4827 * fd_lointr(). There will be no one sleeping but we are
4828 * expecting an interrupt so....
4829 */
4830 fdc->c_flags |= FDCFLG_WAITING;
4831
4832 /*
4833 * The reset bit must be cleared to take the 077 out of
4834 * reset state and the DMAGATE bit must be high to enable
4835 * interrupts.
4836 */
4837 /* LINTED */
4838 Set_dor(fdc, DMAGATE|RESET, 1);
4839
4840 FDERRPRINT(FDEP_L1, FDEM_ATTA,
4841 (C, "fdattach: Dor 0x%x\n", Dor(fdc)));
4842
4843 local_lbolt = ddi_get_lbolt();
4844 if (cv_timedwait(&fdc->c_iocv, &fdc->c_lolock,
4845 local_lbolt + drv_usectohz(1000000)) == -1) {
4846 return (-1);
4847 }
4848 break;
4849
4850 default:
4851 fdc->c_flags |= FDCFLG_WAITING;
4852
4853 /*
4854 * A timed wait is not used because it's possible for the timer
4855 * to go off before the controller has a chance to interrupt.
4856 */
4857 cv_wait(&fdc->c_iocv, &fdc->c_lolock);
4858 break;
4859 }
4860 csb = &fdc->c_csb;
4861
4862 /* setup common things in csb */
4863 csb->csb_unit = fdc->c_un->un_unit_no;
4864 csb->csb_nrslts = 0;
4865 csb->csb_opflags = CSB_OFNORESULTS;
|
3772
3773 (void) fd_unbind_handle(fdc);
3774 return (EIO);
3775 }
3776
3777 Set_Fifo(fdc, csb->csb_cmds[i]);
3778
3779 FDERRPRINT(FDEP_L1, FDEM_EXEC,
3780 (C, "fdexec: sent 0x%x, Msr 0x%x\n", csb->csb_cmds[i],
3781 Msr(fdc)));
3782
3783 }
3784
3785
3786 /*
3787 * Start watchdog timer on data transfer type commands - required
3788 * in case a diskette is not present or is unformatted
3789 */
3790 if (csb->csb_opflags & CSB_OFTIMEIT) {
3791 fdc->c_timeid = timeout(fdwatch, a,
3792 drv_sectohz(tosec));
3793 }
3794
3795 FDERRPRINT(FDEP_L1, FDEM_EXEC,
3796 (C, "fdexec: cmd sent, Msr 0x%x\n", Msr(fdc)));
3797
3798 /* If the operation has no results - then just return */
3799 if (csb->csb_opflags & CSB_OFNORESULTS) {
3800 if (fdc->c_fdtype & FDCTYPE_82077) {
3801 if (fdc->c_mtimeid == 0) {
3802 fdc->c_mtimeid = timeout(fdmotoff, a,
3803 Motoff_delay);
3804 }
3805 }
3806 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: O K ..\n"));
3807
3808 /*
3809 * Make sure the last byte is received well by the
3810 * controller. On faster CPU, it may still be busy
3811 * by the time another command comes here.
3812 */
4825 * when we bring the controller out of reset it will generate
4826 * a polling interrupt. fdintr() will field it and schedule
4827 * fd_lointr(). There will be no one sleeping but we are
4828 * expecting an interrupt so....
4829 */
4830 fdc->c_flags |= FDCFLG_WAITING;
4831
4832 /*
4833 * The reset bit must be cleared to take the 077 out of
4834 * reset state and the DMAGATE bit must be high to enable
4835 * interrupts.
4836 */
4837 /* LINTED */
4838 Set_dor(fdc, DMAGATE|RESET, 1);
4839
4840 FDERRPRINT(FDEP_L1, FDEM_ATTA,
4841 (C, "fdattach: Dor 0x%x\n", Dor(fdc)));
4842
4843 local_lbolt = ddi_get_lbolt();
4844 if (cv_timedwait(&fdc->c_iocv, &fdc->c_lolock,
4845 local_lbolt + drv_sectohz(1)) == -1) {
4846 return (-1);
4847 }
4848 break;
4849
4850 default:
4851 fdc->c_flags |= FDCFLG_WAITING;
4852
4853 /*
4854 * A timed wait is not used because it's possible for the timer
4855 * to go off before the controller has a chance to interrupt.
4856 */
4857 cv_wait(&fdc->c_iocv, &fdc->c_lolock);
4858 break;
4859 }
4860 csb = &fdc->c_csb;
4861
4862 /* setup common things in csb */
4863 csb->csb_unit = fdc->c_un->un_unit_no;
4864 csb->csb_nrslts = 0;
4865 csb->csb_opflags = CSB_OFNORESULTS;
|