425
426 /* Set the dip in the soft state */
427 softsp->dip = devi;
428
429 /* Set up the parent dip */
430 softsp->pdip = ddi_get_parent(softsp->dip);
431
432 DPRINTF(SYSCTRL_ATTACH_DEBUG, ("sysctrl: devi= 0x%p\n, softsp=0x%p\n",
433 (void *)devi, (void *)softsp));
434
435 /* First set all of the timeout values */
436 spur_timeout_hz = drv_usectohz(SPUR_TIMEOUT_USEC);
437 spur_long_timeout_hz = drv_usectohz(SPUR_LONG_TIMEOUT_USEC);
438 ac_timeout_hz = drv_usectohz(AC_TIMEOUT_USEC);
439 ps_fail_timeout_hz = drv_usectohz(PS_FAIL_TIMEOUT_USEC);
440 pps_fan_timeout_hz = drv_usectohz(PPS_FAN_TIMEOUT_USEC);
441 bd_insert_delay_hz = drv_usectohz(BRD_INSERT_DELAY_USEC);
442 bd_insert_retry_hz = drv_usectohz(BRD_INSERT_RETRY_USEC);
443 bd_remove_timeout_hz = drv_usectohz(BRD_REMOVE_TIMEOUT_USEC);
444 blink_led_timeout_hz = drv_usectohz(BLINK_LED_TIMEOUT_USEC);
445 overtemp_timeout_hz = drv_usectohz(OVERTEMP_TIMEOUT_SEC * MICROSEC);
446 keyswitch_timeout_hz = drv_usectohz(KEYSWITCH_TIMEOUT_USEC);
447
448 /*
449 * Map in the registers sets that OBP hands us. According
450 * to the sun4u device tree spec., the register sets are as
451 * follows:
452 *
453 * 0 Clock Frequency Registers (contains the bit
454 * for enabling the remote console reset)
455 * 1 Misc (has all the registers that we need
456 * 2 Clock Version Register
457 */
458 if (ddi_map_regs(softsp->dip, 0,
459 (caddr_t *)&softsp->clk_freq1, 0, 0)) {
460 cmn_err(CE_WARN, "sysctrl%d: unable to map clock frequency "
461 "registers", instance);
462 goto bad0;
463 }
464
465 if (ddi_map_regs(softsp->dip, 1,
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425
426 /* Set the dip in the soft state */
427 softsp->dip = devi;
428
429 /* Set up the parent dip */
430 softsp->pdip = ddi_get_parent(softsp->dip);
431
432 DPRINTF(SYSCTRL_ATTACH_DEBUG, ("sysctrl: devi= 0x%p\n, softsp=0x%p\n",
433 (void *)devi, (void *)softsp));
434
435 /* First set all of the timeout values */
436 spur_timeout_hz = drv_usectohz(SPUR_TIMEOUT_USEC);
437 spur_long_timeout_hz = drv_usectohz(SPUR_LONG_TIMEOUT_USEC);
438 ac_timeout_hz = drv_usectohz(AC_TIMEOUT_USEC);
439 ps_fail_timeout_hz = drv_usectohz(PS_FAIL_TIMEOUT_USEC);
440 pps_fan_timeout_hz = drv_usectohz(PPS_FAN_TIMEOUT_USEC);
441 bd_insert_delay_hz = drv_usectohz(BRD_INSERT_DELAY_USEC);
442 bd_insert_retry_hz = drv_usectohz(BRD_INSERT_RETRY_USEC);
443 bd_remove_timeout_hz = drv_usectohz(BRD_REMOVE_TIMEOUT_USEC);
444 blink_led_timeout_hz = drv_usectohz(BLINK_LED_TIMEOUT_USEC);
445 overtemp_timeout_hz = drv_sectohz(OVERTEMP_TIMEOUT_SEC);
446 keyswitch_timeout_hz = drv_usectohz(KEYSWITCH_TIMEOUT_USEC);
447
448 /*
449 * Map in the registers sets that OBP hands us. According
450 * to the sun4u device tree spec., the register sets are as
451 * follows:
452 *
453 * 0 Clock Frequency Registers (contains the bit
454 * for enabling the remote console reset)
455 * 1 Misc (has all the registers that we need
456 * 2 Clock Version Register
457 */
458 if (ddi_map_regs(softsp->dip, 0,
459 (caddr_t *)&softsp->clk_freq1, 0, 0)) {
460 cmn_err(CE_WARN, "sysctrl%d: unable to map clock frequency "
461 "registers", instance);
462 goto bad0;
463 }
464
465 if (ddi_map_regs(softsp->dip, 1,
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