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patch use-x2apic-feature
patch apic-simplify
patch apic-task-reg-write-dup

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          --- old/usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
          +++ new/usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
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  87   87  
  88   88  /* The default ops is local APIC (Memory Mapped IO) */
  89   89  apic_reg_ops_t *apic_reg_ops = &local_apic_regs_ops;
  90   90  
  91   91  /*
  92   92   * APIC register ops related data sturctures and functions.
  93   93   */
  94   94  void apic_send_EOI();
  95   95  void apic_send_directed_EOI(uint32_t irq);
  96   96  
  97      -#define X2APIC_CPUID_BIT        21
  98   97  #define X2APIC_ENABLE_BIT       10
  99   98  
 100   99  /*
 101  100   * Local APIC Implementation
 102  101   */
 103  102  static uint64_t
 104  103  local_apic_read(uint32_t reg)
 105  104  {
 106  105          return ((uint32_t)apicadr[reg]);
 107  106  }
 108  107  
 109  108  static void
 110  109  local_apic_write(uint32_t reg, uint64_t value)
 111  110  {
 112      -        apicadr[reg] = (uint32_t)value;
      111 +        LOCAL_APIC_WRITE_REG(reg, (uint32_t)value);
 113  112  }
 114  113  
 115  114  static int
 116  115  get_local_apic_pri(void)
 117  116  {
 118  117  #if defined(__amd64)
 119  118          return ((int)getcr8());
 120  119  #else
 121  120          if (apic_have_32bit_cr8)
 122  121                  return ((int)getcr8());
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 126  125  
 127  126  static void
 128  127  local_apic_write_task_reg(uint64_t value)
 129  128  {
 130  129  #if defined(__amd64)
 131  130          setcr8((ulong_t)(value >> APIC_IPL_SHIFT));
 132  131  #else
 133  132          if (apic_have_32bit_cr8)
 134  133                  setcr8((ulong_t)(value >> APIC_IPL_SHIFT));
 135  134          else
 136      -                apicadr[APIC_TASK_REG] = (uint32_t)value;
      135 +                LOCAL_APIC_WRITE_REG(APIC_TASK_REG, (uint32_t)value);
 137  136  #endif
 138  137  }
 139  138  
 140  139  static void
 141  140  local_apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1)
 142  141  {
 143  142          apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET;
 144  143          apicadr[APIC_INT_CMD1] = cmd1;
 145  144  }
 146  145  
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 226  225                          vector = apic_irq->airq_vector;
 227  226                          ioapic_write_eoi(ioapicindex, vector);
 228  227                  }
 229  228                  apic_irq = apic_irq->airq_next;
 230  229          }
 231  230  }
 232  231  
 233  232  int
 234  233  apic_detect_x2apic(void)
 235  234  {
 236      -        struct cpuid_regs cp;
 237      -
 238  235          if (x2apic_enable == 0)
 239  236                  return (0);
 240  237  
 241      -        cp.cp_eax = 1;
 242      -        (void) __cpuid_insn(&cp);
 243      -
 244      -        return ((cp.cp_ecx & (0x1 << X2APIC_CPUID_BIT)) ? 1 : 0);
      238 +        return is_x86_feature(x86_featureset, X86FSET_X2APIC);
 245  239  }
 246  240  
 247  241  void
 248  242  apic_enable_x2apic(void)
 249  243  {
 250  244          uint64_t apic_base_msr;
 251  245  
 252  246          if (apic_local_mode() == LOCAL_X2APIC) {
 253  247                  /* BIOS apparently has enabled X2APIC */
 254  248                  if (apic_mode != LOCAL_X2APIC)
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