1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _SYS_SGFRUTYPES_H
28 #define _SYS_SGFRUTYPES_H
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 /*
35 * sgfrutypes.h - Serengeti/WildCat/Lightweight8 common FRU definitions
36 *
37 * This header file contains the common FRU-ID definitions and macros for the
38 * Serengeti, WildCat and Lightweight8 platforms.
39 *
40 * - definitions of the various FRU types.
41 * - macros to generate FRU names.
42 *
43 * (Not to be confused with the header files for the SGFRU driver)
44 */
45
46 /*
47 * Known HPU/FRU types
48 *
49 * These FRU definitions are common to both the Serengeti and LightWeight8
50 * platforms. They are used by various macros used by both platforms as well
51 * as the LW8 specific SGENV (environmentals) driver.
52 */
53 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD (0x101)
54 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_STR \
55 "System Controller Board"
56 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_ID "SSC"
57 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_SHORTNAME "SSC"
58
59 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_F3800 (0x102)
60 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_F3800_STR \
61 "System Controller Board (F3800)"
62 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_F3800_ID "SSC"
63 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_F3800_SHORTNAME "SSC"
64
65
66 #define SG_HPU_TYPE_CPU_BOARD (0x201)
67 #define SG_HPU_TYPE_CPU_BOARD_STR "CPU Board"
68 #define SG_HPU_TYPE_CPU_BOARD_ID "SB"
69 #define SG_HPU_TYPE_CPU_BOARD_SHORTNAME "CPU"
70
71 #define SG_HPU_TYPE_WIB_BOARD (0x202)
72 #define SG_HPU_TYPE_WIB_BOARD_STR "WIB Board"
73 #define SG_HPU_TYPE_WIB_BOARD_ID "SB"
74 #define SG_HPU_TYPE_WIB_BOARD_SHORTNAME "WIB"
75
76 #define SG_HPU_TYPE_REPEATER_BOARD (0x301)
77 #define SG_HPU_TYPE_REPEATER_BOARD_STR "Repeater Board"
78 #define SG_HPU_TYPE_REPEATER_BOARD_ID "RP"
79
80 #define SG_HPU_TYPE_LOGIC_ANALYZER_BOARD (0x302)
81 #define SG_HPU_TYPE_LOGIC_ANALYZER_BOARD_STR "Logic Analyzer Board"
82 #define SG_HPU_TYPE_LOGIC_ANALYZER_BOARD_ID "RP"
83
84 #define SG_HPU_TYPE_REPEATER_BOARD_F3800 (0x303)
85 #define SG_HPU_TYPE_REPEATER_BOARD_F3800_STR "Repeater Board (F3800)"
86 #define SG_HPU_TYPE_REPEATER_BOARD_F3800_ID "RP"
87 #define SG_HPU_TYPE_REPEATER_BOARD_F3800_SHORTNAME "RP"
88
89
90 #define SG_HPU_TYPE_FAN_TRAY_F6800_IO (0x401)
91 #define SG_HPU_TYPE_FAN_TRAY_F6800_IO_STR "Fan Tray (F6800, I/O)"
92 #define SG_HPU_TYPE_FAN_TRAY_F6800_IO_ID "FT"
93 #define SG_HPU_TYPE_FAN_TRAY_F6800_IO_SHORTNAME "FAN"
94
95 #define SG_HPU_TYPE_FAN_TRAY_F6800_CPU (0x402)
96 #define SG_HPU_TYPE_FAN_TRAY_F6800_CPU_STR "Fan Tray (F6800, CPU)"
97 #define SG_HPU_TYPE_FAN_TRAY_F6800_CPU_ID "FT"
98 #define SG_HPU_TYPE_FAN_TRAY_F6800_CPU_SHORTNAME "FAN"
99
100 #define SG_HPU_TYPE_FAN_TRAY_RACK (0x403)
101 #define SG_HPU_TYPE_FAN_TRAY_RACK_STR "Fan Tray (Rack)"
102 #define SG_HPU_TYPE_FAN_TRAY_RACK_ID "FT"
103 #define SG_HPU_TYPE_FAN_TRAY_RACK_SHORTNAME "RACKFAN"
104
105 #define SG_HPU_TYPE_FAN_TRAY_F4810 (0x404)
106 #define SG_HPU_TYPE_FAN_TRAY_F4810_STR "Fan Tray (F4810)"
107 #define SG_HPU_TYPE_FAN_TRAY_F4810_ID "FT"
108 #define SG_HPU_TYPE_FAN_TRAY_F4810_SHORTNAME "FAN"
109
110 #define SG_HPU_TYPE_FAN_TRAY_F4800_IO (0x405)
111 #define SG_HPU_TYPE_FAN_TRAY_F4800_IO_STR "Fan Tray (F4800, I/O)"
112 #define SG_HPU_TYPE_FAN_TRAY_F4800_IO_ID "FT"
113 #define SG_HPU_TYPE_FAN_TRAY_F4800_IO_SHORTNAME "FAN"
114
115 #define SG_HPU_TYPE_FAN_TRAY_F4800_CPU (0x406)
116 #define SG_HPU_TYPE_FAN_TRAY_F4800_CPU_STR "Fan Tray (F4800, CPU)"
117 #define SG_HPU_TYPE_FAN_TRAY_F4800_CPU_ID "FT"
118 #define SG_HPU_TYPE_FAN_TRAY_F4800_CPU_SHORTNAME "FAN"
119
120 #define SG_HPU_TYPE_FAN_TRAY_F4800_TOP_IO (0x407)
121 #define SG_HPU_TYPE_FAN_TRAY_F4800_TOP_IO_STR \
122 "Fan Tray (F4800, Top I/O)"
123 #define SG_HPU_TYPE_FAN_TRAY_F4800_TOP_IO_ID "FT"
124 #define SG_HPU_TYPE_FAN_TRAY_F4800_TOP_IO_SHORTNAME "FAN"
125
126 #define SG_HPU_TYPE_FAN_TRAY_F3800 (0x408)
127 #define SG_HPU_TYPE_FAN_TRAY_F3800_STR "Fan Tray (F3800)"
128 #define SG_HPU_TYPE_FAN_TRAY_F3800_ID "FT"
129 #define SG_HPU_TYPE_FAN_TRAY_F3800_SHORTNAME "FAN"
130
131 #define SG_HPU_TYPE_FAN_TRAY_F4800_BOTTOM_IO (0x409)
132 #define SG_HPU_TYPE_FAN_TRAY_F4800_BOTTOM_IO_STR \
133 "Fan Tray (F4800, Bottom I/O)"
134 #define SG_HPU_TYPE_FAN_TRAY_F4800_BOTTOM_IO_ID "FT"
135 #define SG_HPU_TYPE_FAN_TRAY_F4800_BOTTOM_IO_SHORTNAME "FAN"
136
137
138 #define SG_HPU_TYPE_PCI_IO_BOARD (0x501)
139 #define SG_HPU_TYPE_PCI_IO_BOARD_STR "PCI I/O Board"
140 #define SG_HPU_TYPE_PCI_IO_BOARD_ID "IB"
141 #define SG_HPU_TYPE_PCI_IO_BOARD_SHORTNAME "PCIB"
142
143 #define SG_HPU_TYPE_CPCI_IO_BOARD (0x502)
144 #define SG_HPU_TYPE_CPCI_IO_BOARD_STR "CPCI I/O board"
145 #define SG_HPU_TYPE_CPCI_IO_BOARD_ID "IB"
146 #define SG_HPU_TYPE_CPCI_IO_BOARD_SHORTNAME "CPCB"
147
148 #define SG_HPU_TYPE_CPCI_IO_BOARD_F3800 (0x503)
149 #define SG_HPU_TYPE_CPCI_IO_BOARD_F3800_STR "CPCI I/O board (F3800)"
150 #define SG_HPU_TYPE_CPCI_IO_BOARD_F3800_ID "IB"
151
152 #define SG_HPU_TYPE_WCI_CPCI_IO_BOARD (0x504)
153 #define SG_HPU_TYPE_WCI_CPCI_IO_BOARD_STR "WCI cPCI I/O Board"
154 #define SG_HPU_TYPE_WCI_CPCI_IO_BOARD_ID "IB"
155
156 #define SG_HPU_TYPE_WCI_CPCI_IO_BOARD_F3800 (0x505)
157 #define SG_HPU_TYPE_WCI_CPCI_IO_BOARD_F3800_STR "WCI cPCI I/O Board (F3800)"
158 #define SG_HPU_TYPE_WCI_CPCI_IO_BOARD_F3800_ID "IB"
159
160
161 #define SG_HPU_TYPE_A123_POWER_SUPPLY (0x601)
162 #define SG_HPU_TYPE_A123_POWER_SUPPLY_STR "A123 Power Supply"
163 #define SG_HPU_TYPE_A123_POWER_SUPPLY_ID "PS"
164 #define SG_HPU_TYPE_A123_POWER_SUPPLY_SHORTNAME "PS"
165
166 #define SG_HPU_TYPE_A138_POWER_SUPPLY (0x602)
167 #define SG_HPU_TYPE_A138_POWER_SUPPLY_STR "A138 Power Supply"
168 #define SG_HPU_TYPE_A138_POWER_SUPPLY_ID "PS"
169 #define SG_HPU_TYPE_A138_POWER_SUPPLY_SHORTNAME "PS"
170
171 #define SG_HPU_TYPE_A145_POWER_SUPPLY (0x603)
172 #define SG_HPU_TYPE_A145_POWER_SUPPLY_STR "A145 Power Supply"
173 #define SG_HPU_TYPE_A145_POWER_SUPPLY_ID "PS"
174 #define SG_HPU_TYPE_A145_POWER_SUPPLY_SHORTNAME "PS"
175
176 #define SG_HPU_TYPE_A152_POWER_SUPPLY (0x604)
177 #define SG_HPU_TYPE_A152_POWER_SUPPLY_STR "A152 Power Supply"
178 #define SG_HPU_TYPE_A152_POWER_SUPPLY_ID "PS"
179 #define SG_HPU_TYPE_A152_POWER_SUPPLY_SHORTNAME "PS"
180
181 #define SG_HPU_TYPE_A153_POWER_SUPPLY (0x605)
182 #define SG_HPU_TYPE_A153_POWER_SUPPLY_STR "A153 Power Supply"
183 #define SG_HPU_TYPE_A153_POWER_SUPPLY_ID "PS"
184 #define SG_HPU_TYPE_A153_POWER_SUPPLY_SHORTNAME "PS"
185
186
187 #define SG_HPU_TYPE_SUN_FIRE_3800_CENTERPLANE (0x701) /* 0x701 */
188 #define SG_HPU_TYPE_SUN_FIRE_3800_CENTERPLANE_STR \
189 "Sun Fire 3800 Centerplane"
190 #define SG_HPU_TYPE_SUN_FIRE_3800_CENTERPLANE_ID "ID"
191 #define SG_HPU_TYPE_SUN_FIRE_3800_CENTERPLANE_SHORTNAME "ID"
192
193 #define SG_HPU_TYPE_SUN_FIRE_6800_CENTERPLANE (0x702) /* 0x702 */
194 #define SG_HPU_TYPE_SUN_FIRE_6800_CENTERPLANE_STR \
195 "Sun Fire 6800 Centerplane"
196 #define SG_HPU_TYPE_SUN_FIRE_6800_CENTERPLANE_ID "ID"
197 #define SG_HPU_TYPE_SUN_FIRE_6800_CENTERPLANE_SHORTNAME "ID"
198
199 #define SG_HPU_TYPE_SUN_FIRE_4810_CENTERPLANE (0x703) /* 0x703 */
200 #define SG_HPU_TYPE_SUN_FIRE_4810_CENTERPLANE_STR \
201 "Sun Fire 4810 Centerplane"
202 #define SG_HPU_TYPE_SUN_FIRE_4810_CENTERPLANE_ID "ID"
203 #define SG_HPU_TYPE_SUN_FIRE_4810_CENTERPLANE_SHORTNAME "ID"
204
205 #define SG_HPU_TYPE_SUN_FIRE_4800_CENTERPLANE (0x704) /* 0x704 */
206 #define SG_HPU_TYPE_SUN_FIRE_4800_CENTERPLANE_STR \
207 "Sun Fire 4800 Centerplane"
208 #define SG_HPU_TYPE_SUN_FIRE_4800_CENTERPLANE_ID "ID"
209 #define SG_HPU_TYPE_SUN_FIRE_4800_CENTERPLANE_SHORTNAME "ID"
210
211 #define SG_HPU_TYPE_SUN_FIRE_3800_REPLACEMENT_CENTERPLANE (0x705)
212 #define SG_HPU_TYPE_SUN_FIRE_3800_REPLACEMENT_CENTERPLANE_STR \
213 "Sun Fire 3800 Replacement Centerplane"
214 #define SG_HPU_TYPE_SUN_FIRE_3800_REPLACEMENT_CENTERPLANE_ID "ID"
215 #define SG_HPU_TYPE_SUN_FIRE_3800_REPLACEMENT_CENTERPLANE_SHORTNAME "ID"
216
217 #define SG_HPU_TYPE_SUN_FIRE_6800_REPLACEMENT_CENTERPLANE (0x706)
218 #define SG_HPU_TYPE_SUN_FIRE_6800_REPLACEMENT_CENTERPLANE_STR \
219 "Sun Fire 6800 Replacement Centerplane"
220 #define SG_HPU_TYPE_SUN_FIRE_6800_REPLACEMENT_CENTERPLANE_ID "ID"
221 #define SG_HPU_TYPE_SUN_FIRE_6800_REPLACEMENT_CENTERPLANE_SHORTNAME "ID"
222
223 #define SG_HPU_TYPE_SUN_FIRE_4810_REPLACEMENT_CENTERPLANE (0x707)
224 #define SG_HPU_TYPE_SUN_FIRE_4810_REPLACEMENT_CENTERPLANE_STR \
225 "Sun Fire 4810 Replacement Centerplane"
226 #define SG_HPU_TYPE_SUN_FIRE_4810_REPLACEMENT_CENTERPLANE_ID "ID"
227 #define SG_HPU_TYPE_SUN_FIRE_4810_REPLACEMENT_CENTERPLANE_SHORTNAME "ID"
228
229 #define SG_HPU_TYPE_SUN_FIRE_4800_REPLACEMENT_CENTERPLANE (0x708)
230 #define SG_HPU_TYPE_SUN_FIRE_4800_REPLACEMENT_CENTERPLANE_STR \
231 "Sun Fire 4800 Replacement Centerplane"
232 #define SG_HPU_TYPE_SUN_FIRE_4800_REPLACEMENT_CENTERPLANE_ID "ID"
233 #define SG_HPU_TYPE_SUN_FIRE_4800_REPLACEMENT_CENTERPLANE_SHORTNAME "ID"
234
235 #define SG_HPU_TYPE_SUN_FIRE_REPLACEMENT_ID_BOARD (0x709) /* 0x709 */
236 #define SG_HPU_TYPE_SUN_FIRE_REPLACEMENT_ID_BOARD_STR \
237 "Sun Fire Replacement ID Board"
238 #define SG_HPU_TYPE_SUN_FIRE_REPLACEMENT_ID_BOARD_ID "ID"
239 #define SG_HPU_TYPE_SUN_FIRE_REPLACEMENT_ID_BOARD_SHORTNAME "ID"
240
241
242 #define SG_HPU_TYPE_AC_SEQUENCER (0x900)
243 #define SG_HPU_TYPE_AC_SEQUENCER_STR "AC Sequencer"
244 #define SG_HPU_TYPE_AC_SEQUENCER_ID "AC"
245 #define SG_HPU_TYPE_AC_SEQUENCER_SHORTNAME "AC"
246
247
248 #define SG_HPU_TYPE_2MB_ECACHE_MODULE ((10<<8)|1) /* 0xA01 */
249 #define SG_HPU_TYPE_2MB_ECACHE_MODULE_STR \
250 "2MB Ecache module"
251
252 #define SG_HPU_TYPE_2MB_ECACHE_MODULE_SHORTNAME "ECACHE"
253
254 #define SG_HPU_TYPE_4MB_ECACHE_MODULE ((10<<8)|2) /* 0xA02 */
255 #define SG_HPU_TYPE_4MB_ECACHE_MODULE_STR \
256 "4MB Ecache module"
257
258 #define SG_HPU_TYPE_4MB_ECACHE_MODULE_SHORTNAME "ECACHE"
259
260 #define SG_HPU_TYPE_DRAM_SLOT ((11<<8)|0) /* 0xB00 */
261 #define SG_HPU_TYPE_DRAM_SLOT_STR \
262 "DRAM slot"
263
264 #define SG_HPU_TYPE_DRAM_SLOT_SHORTNAME "DIMM"
265
266 #define SG_HPU_TYPE_128MB_DRAM_MODULE ((11<<8)|1) /* 0xB01 */
267 #define SG_HPU_TYPE_128MB_DRAM_MODULE_STR \
268 "128MB DRAM module"
269
270 #define SG_HPU_TYPE_128MB_DRAM_MODULE_SHORTNAME "DIMM"
271
272 #define SG_HPU_TYPE_256MB_DRAM_MODULE ((11<<8)|2) /* 0xB02 */
273 #define SG_HPU_TYPE_256MB_DRAM_MODULE_STR \
274 "256MB DRAM module"
275
276 #define SG_HPU_TYPE_256MB_DRAM_MODULE_SHORTNAME "DIMM"
277
278 #define SG_HPU_TYPE_512MB_DRAM_MODULE ((11<<8)|3) /* 0xB03 */
279 #define SG_HPU_TYPE_512MB_DRAM_MODULE_STR \
280 "512MB DRAM module"
281
282 #define SG_HPU_TYPE_512MB_DRAM_MODULE_SHORTNAME "DIMM"
283
284 #define SG_HPU_TYPE_1GB_DRAM_MODULE ((11<<8)|4) /* 0xB04 */
285 #define SG_HPU_TYPE_1GB_DRAM_MODULE_STR \
286 "1GB DRAM module"
287
288 #define SG_HPU_TYPE_1GB_DRAM_MODULE_SHORTNAME "DIMM"
289
290 /*
291 * These macros are used to generate the FRU Names of the various boards etc.
292 * A string is passed in to each macro and by calling a number of the
293 * macros a FRU name in the HLLN format can be built up.
294 *
295 * Note: The string needs to be initialized to an empty string before the
296 * first of these macros is called to generate a FRU Name.
297 */
298 #define MAX_FRU_NAME_LEN 20
299
300 #define SG_SET_FRU_NAME_NODE(str, num) \
301 { \
302 char tmp_str[MAX_FRU_NAME_LEN]; \
303 (void) sprintf(tmp_str, "/N%d", num); \
304 (void) strcat(str, tmp_str); \
305 }
306
307 #define SG_SET_FRU_NAME_CPU_BOARD(str, num) \
308 { \
309 char tmp_str[MAX_FRU_NAME_LEN]; \
310 (void) sprintf(tmp_str, "/%s%d", SG_HPU_TYPE_CPU_BOARD_ID, num); \
311 (void) strcat(str, tmp_str); \
312 }
313
314 #define SG_SET_FRU_NAME_IO_BOARD(str, num) \
315 { \
316 char tmp_str[MAX_FRU_NAME_LEN]; \
317 (void) sprintf(tmp_str, "/%s%d", SG_HPU_TYPE_PCI_IO_BOARD_ID, num); \
318 (void) strcat(str, tmp_str); \
319 }
320
321 #define SG_SET_FRU_NAME_MODULE(str, num) \
322 { \
323 char tmp_str[MAX_FRU_NAME_LEN]; \
324 (void) sprintf(tmp_str, "/P%d", num); \
325 (void) strcat(str, tmp_str); \
326 }
327
328 #define SG_SET_FRU_NAME_CORE(str, num) \
329 { \
330 char tmp_str[MAX_FRU_NAME_LEN]; \
331 (void) sprintf(tmp_str, "/C%d", num); \
332 (void) strcat(str, tmp_str); \
333 }
334
335 #define SG_SET_FRU_NAME_BANK(str, num) \
336 { \
337 char tmp_str[MAX_FRU_NAME_LEN]; \
338 (void) sprintf(tmp_str, "/B%d", num); \
339 (void) strcat(str, tmp_str); \
340 }
341
342 #define SG_SET_FRU_NAME_DIMM(str, num) \
343 { \
344 char tmp_str[MAX_FRU_NAME_LEN]; \
345 (void) sprintf(tmp_str, "/D%d", num); \
346 (void) strcat(str, tmp_str); \
347 }
348
349
350 #ifdef __cplusplus
351 }
352 #endif
353
354 #endif /* _SYS_SGFRUTYPES_H */