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remove whole-process swapping
Long before Unix supported paging, it used process swapping to reclaim
memory. The code is there and in theory it runs when we get *extremely* low
on memory. In practice, it never runs since the definition of low-on-memory
is antiquated. (XXX: define what antiquated means)
You can check the number of swapout/swapin events with kstats:
$ kstat -p ::vm:swapin ::vm:swapout
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--- old/usr/src/uts/i86pc/os/mlsetup.c
+++ new/usr/src/uts/i86pc/os/mlsetup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2012 Gary Mills
23 23 *
24 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 26 */
27 27 /*
28 28 * Copyright (c) 2010, Intel Corporation.
29 29 * All rights reserved.
30 30 */
31 31
32 32 #include <sys/types.h>
33 33 #include <sys/sysmacros.h>
34 34 #include <sys/disp.h>
35 35 #include <sys/promif.h>
36 36 #include <sys/clock.h>
37 37 #include <sys/cpuvar.h>
38 38 #include <sys/stack.h>
39 39 #include <vm/as.h>
40 40 #include <vm/hat.h>
41 41 #include <sys/reboot.h>
42 42 #include <sys/avintr.h>
43 43 #include <sys/vtrace.h>
44 44 #include <sys/proc.h>
45 45 #include <sys/thread.h>
46 46 #include <sys/cpupart.h>
47 47 #include <sys/pset.h>
48 48 #include <sys/copyops.h>
49 49 #include <sys/pg.h>
50 50 #include <sys/disp.h>
51 51 #include <sys/debug.h>
52 52 #include <sys/sunddi.h>
53 53 #include <sys/x86_archext.h>
54 54 #include <sys/privregs.h>
55 55 #include <sys/machsystm.h>
56 56 #include <sys/ontrap.h>
57 57 #include <sys/bootconf.h>
58 58 #include <sys/boot_console.h>
59 59 #include <sys/kdi_machimpl.h>
60 60 #include <sys/archsystm.h>
61 61 #include <sys/promif.h>
62 62 #include <sys/pci_cfgspace.h>
63 63 #ifdef __xpv
64 64 #include <sys/hypervisor.h>
65 65 #else
66 66 #include <sys/xpv_support.h>
67 67 #endif
68 68
69 69 /*
70 70 * some globals for patching the result of cpuid
71 71 * to solve problems w/ creative cpu vendors
72 72 */
73 73
74 74 extern uint32_t cpuid_feature_ecx_include;
75 75 extern uint32_t cpuid_feature_ecx_exclude;
76 76 extern uint32_t cpuid_feature_edx_include;
77 77 extern uint32_t cpuid_feature_edx_exclude;
78 78
79 79 /*
80 80 * Set console mode
81 81 */
82 82 static void
83 83 set_console_mode(uint8_t val)
84 84 {
85 85 struct bop_regs rp = {0};
86 86
87 87 rp.eax.byte.ah = 0x0;
88 88 rp.eax.byte.al = val;
89 89 rp.ebx.word.bx = 0x0;
90 90
91 91 BOP_DOINT(bootops, 0x10, &rp);
92 92 }
93 93
94 94
95 95 /*
96 96 * Setup routine called right before main(). Interposing this function
97 97 * before main() allows us to call it in a machine-independent fashion.
98 98 */
99 99 void
100 100 mlsetup(struct regs *rp)
101 101 {
102 102 u_longlong_t prop_value;
103 103 extern struct classfuncs sys_classfuncs;
104 104 extern disp_t cpu0_disp;
105 105 extern char t0stack[];
106 106 extern int post_fastreboot;
107 107 extern uint64_t plat_dr_options;
108 108
109 109 ASSERT_STACK_ALIGNED();
110 110
111 111 /*
112 112 * initialize cpu_self
113 113 */
114 114 cpu[0]->cpu_self = cpu[0];
115 115
116 116 #if defined(__xpv)
117 117 /*
118 118 * Point at the hypervisor's virtual cpu structure
119 119 */
120 120 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
121 121 #endif
122 122
123 123 /*
124 124 * check if we've got special bits to clear or set
125 125 * when checking cpu features
126 126 */
127 127
128 128 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
129 129 cpuid_feature_ecx_include = 0;
130 130 else
131 131 cpuid_feature_ecx_include = (uint32_t)prop_value;
132 132
133 133 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
134 134 cpuid_feature_ecx_exclude = 0;
135 135 else
136 136 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
137 137
138 138 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
139 139 cpuid_feature_edx_include = 0;
140 140 else
141 141 cpuid_feature_edx_include = (uint32_t)prop_value;
142 142
143 143 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
144 144 cpuid_feature_edx_exclude = 0;
145 145 else
146 146 cpuid_feature_edx_exclude = (uint32_t)prop_value;
147 147
148 148 /*
149 149 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
150 150 */
151 151 init_desctbls();
152 152
153 153 /*
154 154 * lgrp_init() and possibly cpuid_pass1() need PCI config
155 155 * space access
156 156 */
157 157 #if defined(__xpv)
158 158 if (DOMAIN_IS_INITDOMAIN(xen_info))
159 159 pci_cfgspace_init();
160 160 #else
161 161 pci_cfgspace_init();
162 162 /*
163 163 * Initialize the platform type from CPU 0 to ensure that
164 164 * determine_platform() is only ever called once.
165 165 */
166 166 determine_platform();
167 167 #endif
168 168
169 169 /*
170 170 * The first lightweight pass (pass0) through the cpuid data
171 171 * was done in locore before mlsetup was called. Do the next
172 172 * pass in C code.
173 173 *
174 174 * The x86_featureset is initialized here based on the capabilities
175 175 * of the boot CPU. Note that if we choose to support CPUs that have
176 176 * different feature sets (at which point we would almost certainly
177 177 * want to set the feature bits to correspond to the feature
178 178 * minimum) this value may be altered.
179 179 */
180 180 cpuid_pass1(cpu[0], x86_featureset);
181 181
182 182 #if !defined(__xpv)
183 183 if ((get_hwenv() & HW_XEN_HVM) != 0)
184 184 xen_hvm_init();
185 185
186 186 /*
187 187 * Before we do anything with the TSCs, we need to work around
188 188 * Intel erratum BT81. On some CPUs, warm reset does not
189 189 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
190 190 * here. Other CPUs will clear it when we boot them later, and the
191 191 * resulting skew will be handled by tsc_sync_master()/_slave();
192 192 * note that such skew already exists and has to be handled anyway.
193 193 *
194 194 * We do this only on metal. This same problem can occur with a
195 195 * hypervisor that does not happen to virtualise a TSC that starts from
196 196 * zero, regardless of CPU type; however, we do not expect hypervisors
197 197 * that do not virtualise TSC that way to handle writes to TSC
198 198 * correctly, either.
199 199 */
200 200 if (get_hwenv() == HW_NATIVE &&
201 201 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
202 202 cpuid_getfamily(CPU) == 6 &&
203 203 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
204 204 is_x86_feature(x86_featureset, X86FSET_TSC)) {
205 205 (void) wrmsr(REG_TSC, 0UL);
206 206 }
207 207
208 208 /*
209 209 * Patch the tsc_read routine with appropriate set of instructions,
210 210 * depending on the processor family and architecure, to read the
211 211 * time-stamp counter while ensuring no out-of-order execution.
212 212 * Patch it while the kernel text is still writable.
213 213 *
214 214 * Note: tsc_read is not patched for intel processors whose family
215 215 * is >6 and for amd whose family >f (in case they don't support rdtscp
216 216 * instruction, unlikely). By default tsc_read will use cpuid for
217 217 * serialization in such cases. The following code needs to be
218 218 * revisited if intel processors of family >= f retains the
219 219 * instruction serialization nature of mfence instruction.
220 220 * Note: tsc_read is not patched for x86 processors which do
221 221 * not support "mfence". By default tsc_read will use cpuid for
222 222 * serialization in such cases.
223 223 *
224 224 * The Xen hypervisor does not correctly report whether rdtscp is
225 225 * supported or not, so we must assume that it is not.
226 226 */
227 227 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
228 228 is_x86_feature(x86_featureset, X86FSET_TSCP))
229 229 patch_tsc_read(X86_HAVE_TSCP);
230 230 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
231 231 cpuid_getfamily(CPU) <= 0xf &&
232 232 is_x86_feature(x86_featureset, X86FSET_SSE2))
233 233 patch_tsc_read(X86_TSC_MFENCE);
234 234 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
235 235 cpuid_getfamily(CPU) <= 6 &&
236 236 is_x86_feature(x86_featureset, X86FSET_SSE2))
237 237 patch_tsc_read(X86_TSC_LFENCE);
238 238
239 239 #endif /* !__xpv */
240 240
241 241 #if defined(__i386) && !defined(__xpv)
242 242 /*
243 243 * Some i386 processors do not implement the rdtsc instruction,
244 244 * or at least they do not implement it correctly. Patch them to
245 245 * return 0.
246 246 */
247 247 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
248 248 patch_tsc_read(X86_NO_TSC);
249 249 #endif /* __i386 && !__xpv */
250 250
251 251 #if defined(__amd64) && !defined(__xpv)
252 252 patch_memops(cpuid_getvendor(CPU));
253 253 #endif /* __amd64 && !__xpv */
254 254
255 255 #if !defined(__xpv)
256 256 /* XXPV what, if anything, should be dorked with here under xen? */
257 257
258 258 /*
259 259 * While we're thinking about the TSC, let's set up %cr4 so that
260 260 * userland can issue rdtsc, and initialize the TSC_AUX value
261 261 * (the cpuid) for the rdtscp instruction on appropriately
262 262 * capable hardware.
263 263 */
264 264 if (is_x86_feature(x86_featureset, X86FSET_TSC))
265 265 setcr4(getcr4() & ~CR4_TSD);
266 266
267 267 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
268 268 (void) wrmsr(MSR_AMD_TSCAUX, 0);
269 269
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270 270 if (is_x86_feature(x86_featureset, X86FSET_DE))
271 271 setcr4(getcr4() | CR4_DE);
272 272 #endif /* __xpv */
273 273
274 274 /*
275 275 * initialize t0
276 276 */
277 277 t0.t_stk = (caddr_t)rp - MINFRAME;
278 278 t0.t_stkbase = t0stack;
279 279 t0.t_pri = maxclsyspri - 3;
280 - t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
280 + t0.t_schedflag = 0;
281 281 t0.t_procp = &p0;
282 282 t0.t_plockp = &p0lock.pl_lock;
283 283 t0.t_lwp = &lwp0;
284 284 t0.t_forw = &t0;
285 285 t0.t_back = &t0;
286 286 t0.t_next = &t0;
287 287 t0.t_prev = &t0;
288 288 t0.t_cpu = cpu[0];
289 289 t0.t_disp_queue = &cpu0_disp;
290 290 t0.t_bind_cpu = PBIND_NONE;
291 291 t0.t_bind_pset = PS_NONE;
292 292 t0.t_bindflag = (uchar_t)default_binding_mode;
293 293 t0.t_cpupart = &cp_default;
294 294 t0.t_clfuncs = &sys_classfuncs.thread;
295 295 t0.t_copyops = NULL;
296 296 THREAD_ONPROC(&t0, CPU);
297 297
298 298 lwp0.lwp_thread = &t0;
299 299 lwp0.lwp_regs = (void *)rp;
300 300 lwp0.lwp_procp = &p0;
301 301 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
302 302
303 303 p0.p_exec = NULL;
304 304 p0.p_stat = SRUN;
305 305 p0.p_flag = SSYS;
306 306 p0.p_tlist = &t0;
307 307 p0.p_stksize = 2*PAGESIZE;
308 308 p0.p_stkpageszc = 0;
309 309 p0.p_as = &kas;
310 310 p0.p_lockp = &p0lock;
311 311 p0.p_brkpageszc = 0;
312 312 p0.p_t1_lgrpid = LGRP_NONE;
313 313 p0.p_tr_lgrpid = LGRP_NONE;
314 314 sigorset(&p0.p_ignore, &ignoredefault);
315 315
316 316 CPU->cpu_thread = &t0;
317 317 bzero(&cpu0_disp, sizeof (disp_t));
318 318 CPU->cpu_disp = &cpu0_disp;
319 319 CPU->cpu_disp->disp_cpu = CPU;
320 320 CPU->cpu_dispthread = &t0;
321 321 CPU->cpu_idle_thread = &t0;
322 322 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
323 323 CPU->cpu_dispatch_pri = t0.t_pri;
324 324
325 325 CPU->cpu_id = 0;
326 326
327 327 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
328 328
329 329 /*
330 330 * The kernel doesn't use LDTs unless a process explicitly requests one.
331 331 */
332 332 p0.p_ldt_desc = null_sdesc;
333 333
334 334 /*
335 335 * Initialize thread/cpu microstate accounting
336 336 */
337 337 init_mstate(&t0, LMS_SYSTEM);
338 338 init_cpu_mstate(CPU, CMS_SYSTEM);
339 339
340 340 /*
341 341 * Initialize lists of available and active CPUs.
342 342 */
343 343 cpu_list_init(CPU);
344 344
345 345 pg_cpu_bootstrap(CPU);
346 346
347 347 /*
348 348 * Now that we have taken over the GDT, IDT and have initialized
349 349 * active CPU list it's time to inform kmdb if present.
350 350 */
351 351 if (boothowto & RB_DEBUG)
352 352 kdi_idt_sync();
353 353
354 354 /*
355 355 * Explicitly set console to text mode (0x3) if this is a boot
356 356 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT.
357 357 */
358 358 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT)
359 359 set_console_mode(0x3);
360 360
361 361 /*
362 362 * If requested (boot -d) drop into kmdb.
363 363 *
364 364 * This must be done after cpu_list_init() on the 64-bit kernel
365 365 * since taking a trap requires that we re-compute gsbase based
366 366 * on the cpu list.
367 367 */
368 368 if (boothowto & RB_DEBUGENTER)
369 369 kmdb_enter();
370 370
371 371 cpu_vm_data_init(CPU);
372 372
373 373 rp->r_fp = 0; /* terminate kernel stack traces! */
374 374
375 375 prom_init("kernel", (void *)NULL);
376 376
377 377 /* User-set option overrides firmware value. */
378 378 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
379 379 plat_dr_options = (uint64_t)prop_value;
380 380 }
381 381 #if defined(__xpv)
382 382 /* No support of DR operations on xpv */
383 383 plat_dr_options = 0;
384 384 #else /* __xpv */
385 385 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
386 386 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
387 387 #ifndef __amd64
388 388 /* Only enable CPU/memory DR on 64 bits kernel. */
389 389 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
390 390 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
391 391 #endif /* __amd64 */
392 392 #endif /* __xpv */
393 393
394 394 /*
395 395 * Get value of "plat_dr_physmax" boot option.
396 396 * It overrides values calculated from MSCT or SRAT table.
397 397 */
398 398 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
399 399 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
400 400 }
401 401
402 402 /* Get value of boot_ncpus. */
403 403 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
404 404 boot_ncpus = NCPU;
405 405 } else {
406 406 boot_ncpus = (int)prop_value;
407 407 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
408 408 boot_ncpus = NCPU;
409 409 }
410 410
411 411 /*
412 412 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
413 413 * support CPU DR operations.
414 414 */
415 415 if (plat_dr_support_cpu() == 0) {
416 416 max_ncpus = boot_max_ncpus = boot_ncpus;
417 417 } else {
418 418 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
419 419 max_ncpus = NCPU;
420 420 } else {
421 421 max_ncpus = (int)prop_value;
422 422 if (max_ncpus <= 0 || max_ncpus > NCPU) {
423 423 max_ncpus = NCPU;
424 424 }
425 425 if (boot_ncpus > max_ncpus) {
426 426 boot_ncpus = max_ncpus;
427 427 }
428 428 }
429 429
430 430 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
431 431 boot_max_ncpus = boot_ncpus;
432 432 } else {
433 433 boot_max_ncpus = (int)prop_value;
434 434 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
435 435 boot_max_ncpus = boot_ncpus;
436 436 } else if (boot_max_ncpus > max_ncpus) {
437 437 boot_max_ncpus = max_ncpus;
438 438 }
439 439 }
440 440 }
441 441
442 442 /*
443 443 * Initialize the lgrp framework
444 444 */
445 445 lgrp_init(LGRP_INIT_STAGE1);
446 446
447 447 if (boothowto & RB_HALT) {
448 448 prom_printf("unix: kernel halted by -h flag\n");
449 449 prom_enter_mon();
450 450 }
451 451
452 452 ASSERT_STACK_ALIGNED();
453 453
454 454 /*
455 455 * Fill out cpu_ucode_info. Update microcode if necessary.
456 456 */
457 457 ucode_check(CPU);
458 458
459 459 if (workaround_errata(CPU) != 0)
460 460 panic("critical workaround(s) missing for boot cpu");
461 461 }
462 462
463 463
464 464 void
465 465 mach_modpath(char *path, const char *filename)
466 466 {
467 467 /*
468 468 * Construct the directory path from the filename.
469 469 */
470 470
471 471 int len;
472 472 char *p;
473 473 const char isastr[] = "/amd64";
474 474 size_t isalen = strlen(isastr);
475 475
476 476 if ((p = strrchr(filename, '/')) == NULL)
477 477 return;
478 478
479 479 while (p > filename && *(p - 1) == '/')
480 480 p--; /* remove trailing '/' characters */
481 481 if (p == filename)
482 482 p++; /* so "/" -is- the modpath in this case */
483 483
484 484 /*
485 485 * Remove optional isa-dependent directory name - the module
486 486 * subsystem will put this back again (!)
487 487 */
488 488 len = p - filename;
489 489 if (len > isalen &&
490 490 strncmp(&filename[len - isalen], isastr, isalen) == 0)
491 491 p -= isalen;
492 492
493 493 /*
494 494 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
495 495 */
496 496 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
497 497 (void) strncpy(path, filename, p - filename);
498 498 }
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